2 * Device tree file for Phytec phyCORE-RK3288 SoM
3 * Copyright (C) 2017 PHYTEC Messtechnik GmbH
4 * Author: Wadim Egorov <w.egorov@phytec.de>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/net/ti-dp83867.h>
46 #include "rk3288.dtsi"
49 model = "Phytec RK3288 phyCORE";
50 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
53 * Set the minimum memory size here and
54 * let the bootloader set the real size.
57 device_type = "memory";
66 ext_gmac: external-gmac-clock {
67 compatible = "fixed-clock";
69 clock-frequency = <125000000>;
70 clock-output-names = "ext_gmac";
74 compatible = "gpio-leds";
75 pinctrl-names = "default";
76 pinctrl-0 = <&user_led>;
80 gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
81 linux,default-trigger = "heartbeat";
82 default-state = "keep";
86 vdd_emmc_io: vdd-emmc-io {
87 compatible = "regulator-fixed";
88 regulator-name = "vdd_emmc_io";
89 regulator-min-microvolt = <1800000>;
90 regulator-max-microvolt = <1800000>;
91 vin-supply = <&vdd_3v3_io>;
94 vdd_in_otg_out: vdd-in-otg-out {
95 compatible = "regulator-fixed";
96 regulator-name = "vdd_in_otg_out";
99 regulator-min-microvolt = <5000000>;
100 regulator-max-microvolt = <5000000>;
103 vdd_misc_1v8: vdd-misc-1v8 {
104 compatible = "regulator-fixed";
105 regulator-name = "vdd_misc_1v8";
108 regulator-min-microvolt = <1800000>;
109 regulator-max-microvolt = <1800000>;
114 cpu0-supply = <&vdd_cpu>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
142 vmmc-supply = <&vdd_3v3_io>;
143 vqmmc-supply = <&vdd_emmc_io>;
147 assigned-clocks = <&cru SCLK_MAC>;
148 assigned-clock-parents = <&ext_gmac>;
149 clock_in_out = "input";
150 pinctrl-names = "default";
151 pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>;
152 phy-handle = <&phy0>;
153 phy-supply = <&vdd_eth_2v5>;
154 phy-mode = "rgmii-id";
155 snps,reset-active-low;
156 snps,reset-delays-us = <0 10000 1000000>;
157 snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
162 compatible = "snps,dwmac-mdio";
163 #address-cells = <1>;
166 phy0: ethernet-phy@0 {
167 compatible = "ethernet-phy-ieee802.3-c22";
169 interrupt-parent = <&gpio4>;
170 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
171 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
172 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
173 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
174 enet-phy-lane-no-swap;
180 ddc-i2c-bus = <&i2c5>;
185 sdcard-supply = <&vdd_io_sd>;
186 flash0-supply = <&vdd_emmc_io>;
187 flash1-supply = <&vdd_misc_1v8>;
188 gpio1830-supply = <&vdd_3v3_io>;
189 gpio30-supply = <&vdd_3v3_io>;
190 bb-supply = <&vdd_3v3_io>;
191 dvp-supply = <&vdd_3v3_io>;
192 lcdc-supply = <&vdd_3v3_io>;
193 wifi-supply = <&vdd_3v3_io>;
194 audio-supply = <&vdd_3v3_io>;
199 clock-frequency = <400000>;
202 compatible = "rockchip,rk818";
204 interrupt-parent = <&gpio0>;
205 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pmic_int>;
208 rockchip,system-power-controller;
212 vcc1-supply = <&vdd_sys>;
213 vcc2-supply = <&vdd_sys>;
214 vcc3-supply = <&vdd_sys>;
215 vcc4-supply = <&vdd_sys>;
216 boost-supply = <&vdd_in_otg_out>;
217 vcc6-supply = <&vdd_sys>;
218 vcc7-supply = <&vdd_misc_1v8>;
219 vcc8-supply = <&vdd_misc_1v8>;
220 vcc9-supply = <&vdd_3v3_io>;
221 vddio-supply = <&vdd_3v3_io>;
225 regulator-name = "vdd_log";
228 regulator-min-microvolt = <1100000>;
229 regulator-max-microvolt = <1100000>;
230 regulator-state-mem {
231 regulator-off-in-suspend;
236 regulator-name = "vdd_gpu";
239 regulator-min-microvolt = <800000>;
240 regulator-max-microvolt = <1250000>;
241 regulator-state-mem {
242 regulator-on-in-suspend;
243 regulator-suspend-microvolt = <1000000>;
248 regulator-name = "vcc_ddr";
251 regulator-state-mem {
252 regulator-on-in-suspend;
256 vdd_3v3_io: DCDC_REG4 {
257 regulator-name = "vdd_3v3_io";
260 regulator-min-microvolt = <3300000>;
261 regulator-max-microvolt = <3300000>;
262 regulator-state-mem {
263 regulator-on-in-suspend;
264 regulator-suspend-microvolt = <3300000>;
268 vdd_sys: DCDC_BOOST {
269 regulator-name = "vdd_sys";
272 regulator-min-microvolt = <5000000>;
273 regulator-max-microvolt = <5000000>;
274 regulator-state-mem {
275 regulator-on-in-suspend;
276 regulator-suspend-microvolt = <5000000>;
282 regulator-name = "vdd_sd";
285 regulator-state-mem {
286 regulator-off-in-suspend;
291 vdd_eth_2v5: LDO_REG2 {
292 regulator-name = "vdd_eth_2v5";
295 regulator-min-microvolt = <2500000>;
296 regulator-max-microvolt = <2500000>;
297 regulator-state-mem {
298 regulator-on-in-suspend;
299 regulator-suspend-microvolt = <2500000>;
305 regulator-name = "vdd_1v0";
308 regulator-min-microvolt = <1000000>;
309 regulator-max-microvolt = <1000000>;
310 regulator-state-mem {
311 regulator-on-in-suspend;
312 regulator-suspend-microvolt = <1000000>;
317 vdd_1v8_lcd_ldo: LDO_REG4 {
318 regulator-name = "vdd_1v8_lcd_ldo";
321 regulator-min-microvolt = <1800000>;
322 regulator-max-microvolt = <1800000>;
323 regulator-state-mem {
324 regulator-on-in-suspend;
325 regulator-suspend-microvolt = <1800000>;
330 vdd_1v0_lcd: LDO_REG6 {
331 regulator-name = "vdd_1v0_lcd";
334 regulator-min-microvolt = <1000000>;
335 regulator-max-microvolt = <1000000>;
336 regulator-state-mem {
337 regulator-on-in-suspend;
338 regulator-suspend-microvolt = <1000000>;
343 vdd_1v8_ldo: LDO_REG7 {
344 regulator-name = "vdd_1v8_ldo";
347 regulator-min-microvolt = <1800000>;
348 regulator-max-microvolt = <1800000>;
349 regulator-state-mem {
350 regulator-off-in-suspend;
351 regulator-suspend-microvolt = <1800000>;
356 vdd_io_sd: LDO_REG9 {
357 regulator-name = "vdd_io_sd";
360 regulator-min-microvolt = <3300000>;
361 regulator-max-microvolt = <3300000>;
362 regulator-state-mem {
363 regulator-on-in-suspend;
364 regulator-suspend-microvolt = <3300000>;
371 i2c_eeprom: eeprom@50 {
372 compatible = "atmel,24c32";
377 vdd_cpu: regulator@60 {
378 compatible = "fcs,fan53555";
380 fcs,suspend-voltage-selector = <1>;
383 regulator-enable-ramp-delay = <300>;
384 regulator-name = "vdd_cpu";
385 regulator-min-microvolt = <800000>;
386 regulator-max-microvolt = <1430000>;
387 regulator-ramp-delay = <8000>;
388 vin-supply = <&vdd_sys>;
393 pcfg_output_high: pcfg-output-high {
399 * We run eMMC at max speed; bump up drive strength.
400 * We also have external pulls, so disable the internal ones.
403 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>;
407 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>;
410 emmc_bus8: emmc-bus8 {
411 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>,
412 <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
413 <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>,
414 <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>,
415 <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>,
416 <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>,
417 <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>,
418 <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>;
424 rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>;
428 rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
434 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>;
440 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
443 /* Pin for switching state between sleep and non-sleep state */
444 pmic_sleep: pmic-sleep {
445 rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
456 vref-supply = <&vdd_1v8_ldo>;
462 serial_flash: flash@0 {
463 compatible = "micron,n25q128a13", "jedec,spi-nor";
465 spi-max-frequency = <50000000>;
467 #address-cells = <1>;
475 rockchip,hw-tshut-mode = <0>;
476 rockchip,hw-tshut-polarity = <0>;