arch/arm/boot/dts/rk322x.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3228-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 / {
  49         #address-cells = <1>;
  50         #size-cells = <1>;
  51
  52         interrupt-parent = <&gic>;
  53
  54         aliases {
  55                 serial0 = &uart0;
  56                 serial1 = &uart1;
  57                 serial2 = &uart2;
  58                 spi0 = &spi0;
  59         };
  60
  61         cpus {
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64
  65                 cpu0: cpu@f00 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a7";
  68                         reg = <0xf00>;
  69                         resets = <&cru SRST_CORE0>;
  70                         operating-points-v2 = <&cpu0_opp_table>;
  71                         #cooling-cells = <2>; /* min followed by max */
  72                         clock-latency = <40000>;
  73                         clocks = <&cru ARMCLK>;
  74                         enable-method = "psci";
  75                 };
  76
  77                 cpu1: cpu@f01 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a7";
  80                         reg = <0xf01>;
  81                         resets = <&cru SRST_CORE1>;
  82                         operating-points-v2 = <&cpu0_opp_table>;
  83                         enable-method = "psci";
  84                 };
  85
  86                 cpu2: cpu@f02 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a7";
  89                         reg = <0xf02>;
  90                         resets = <&cru SRST_CORE2>;
  91                         operating-points-v2 = <&cpu0_opp_table>;
  92                         enable-method = "psci";
  93                 };
  94
  95                 cpu3: cpu@f03 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a7";
  98                         reg = <0xf03>;
  99                         resets = <&cru SRST_CORE3>;
 100                         operating-points-v2 = <&cpu0_opp_table>;
 101                         enable-method = "psci";
 102                 };
 103         };
 104
 105         cpu0_opp_table: opp_table0 {
 106                 compatible = "operating-points-v2";
 107                 opp-shared;
 108
 109                 opp-408000000 {
 110                         opp-hz = /bits/ 64 <408000000>;
 111                         opp-microvolt = <950000>;
 112                         clock-latency-ns = <40000>;
 113                         opp-suspend;
 114                 };
 115                 opp-600000000 {
 116                         opp-hz = /bits/ 64 <600000000>;
 117                         opp-microvolt = <975000>;
 118                 };
 119                 opp-816000000 {
 120                         opp-hz = /bits/ 64 <816000000>;
 121                         opp-microvolt = <1000000>;
 122                 };
 123                 opp-1008000000 {
 124                         opp-hz = /bits/ 64 <1008000000>;
 125                         opp-microvolt = <1175000>;
 126                 };
 127                 opp-1200000000 {
 128                         opp-hz = /bits/ 64 <1200000000>;
 129                         opp-microvolt = <1275000>;
 130                 };
 131         };
 132
 133         amba {
 134                 compatible = "simple-bus";
 135                 #address-cells = <1>;
 136                 #size-cells = <1>;
 137                 ranges;
 138
 139                 pdma: pdma@110f0000 {
 140                         compatible = "arm,pl330", "arm,primecell";
 141                         reg = <0x110f0000 0x4000>;
 142                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 143                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 144                         #dma-cells = <1>;
 145                         clocks = <&cru ACLK_DMAC>;
 146                         clock-names = "apb_pclk";
 147                 };
 148         };
 149
 150         arm-pmu {
 151                 compatible = "arm,cortex-a7-pmu";
 152                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 155                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 156                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 157         };
 158
 159         psci {
 160                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 161                 method = "smc";
 162         };
 163
 164         timer {
 165                 compatible = "arm,armv7-timer";
 166                 arm,cpu-registers-not-fw-configured;
 167                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 168                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 169                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 170                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 171                 clock-frequency = <24000000>;
 172         };
 173
 174         xin24m: oscillator {
 175                 compatible = "fixed-clock";
 176                 clock-frequency = <24000000>;
 177                 clock-output-names = "xin24m";
 178                 #clock-cells = <0>;
 179         };
 180
 181         i2s1: i2s1@100b0000 {
 182                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 183                 reg = <0x100b0000 0x4000>;
 184                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 185                 #address-cells = <1>;
 186                 #size-cells = <0>;
 187                 clock-names = "i2s_clk", "i2s_hclk";
 188                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 189                 dmas = <&pdma 14>, <&pdma 15>;
 190                 dma-names = "tx", "rx";
 191                 pinctrl-names = "default";
 192                 pinctrl-0 = <&i2s1_bus>;
 193                 status = "disabled";
 194         };
 195
 196         i2s0: i2s0@100c0000 {
 197                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 198                 reg = <0x100c0000 0x4000>;
 199                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 200                 #address-cells = <1>;
 201                 #size-cells = <0>;
 202                 clock-names = "i2s_clk", "i2s_hclk";
 203                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 204                 dmas = <&pdma 11>, <&pdma 12>;
 205                 dma-names = "tx", "rx";
 206                 status = "disabled";
 207         };
 208
 209         spdif: spdif@100d0000 {
 210                 compatible = "rockchip,rk3228-spdif";
 211                 reg = <0x100d0000 0x1000>;
 212                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 214                 clock-names = "mclk", "hclk";
 215                 dmas = <&pdma 10>;
 216                 dma-names = "tx";
 217                 pinctrl-names = "default";
 218                 pinctrl-0 = <&spdif_tx>;
 219                 status = "disabled";
 220         };
 221
 222         i2s2: i2s2@100e0000 {
 223                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 224                 reg = <0x100e0000 0x4000>;
 225                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 226                 #address-cells = <1>;
 227                 #size-cells = <0>;
 228                 clock-names = "i2s_clk", "i2s_hclk";
 229                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 230                 dmas = <&pdma 0>, <&pdma 1>;
 231                 dma-names = "tx", "rx";
 232                 status = "disabled";
 233         };
 234
 235         grf: syscon@11000000 {
 236                 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
 237                 reg = <0x11000000 0x1000>;
 238                 #address-cells = <1>;
 239                 #size-cells = <1>;
 240
 241                 io_domains: io-domains {
 242                         compatible = "rockchip,rk3228-io-voltage-domain";
 243                         status = "disabled";
 244                 };
 245
 246                 u2phy0: usb2-phy@760 {
 247                         compatible = "rockchip,rk3228-usb2phy";
 248                         reg = <0x0760 0x0c>;
 249                         clocks = <&cru SCLK_OTGPHY0>;
 250                         clock-names = "phyclk";
 251                         clock-output-names = "usb480m_phy0";
 252                         #clock-cells = <0>;
 253                         status = "disabled";
 254
 255                         u2phy0_otg: otg-port {
 256                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 257                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 258                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 259                                 interrupt-names = "otg-bvalid", "otg-id",
 260                                                   "linestate";
 261                                 #phy-cells = <0>;
 262                                 status = "disabled";
 263                         };
 264
 265                         u2phy0_host: host-port {
 266                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 267                                 interrupt-names = "linestate";
 268                                 #phy-cells = <0>;
 269                                 status = "disabled";
 270                         };
 271                 };
 272
 273                 u2phy1: usb2-phy@800 {
 274                         compatible = "rockchip,rk3228-usb2phy";
 275                         reg = <0x0800 0x0c>;
 276                         clocks = <&cru SCLK_OTGPHY1>;
 277                         clock-names = "phyclk";
 278                         clock-output-names = "usb480m_phy1";
 279                         #clock-cells = <0>;
 280                         status = "disabled";
 281
 282                         u2phy1_otg: otg-port {
 283                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 284                                 interrupt-names = "linestate";
 285                                 #phy-cells = <0>;
 286                                 status = "disabled";
 287                         };
 288
 289                         u2phy1_host: host-port {
 290                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 291                                 interrupt-names = "linestate";
 292                                 #phy-cells = <0>;
 293                                 status = "disabled";
 294                         };
 295                 };
 296         };
 297
 298         uart0: serial@11010000 {
 299                 compatible = "snps,dw-apb-uart";
 300                 reg = <0x11010000 0x100>;
 301                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 302                 clock-frequency = <24000000>;
 303                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 304                 clock-names = "baudclk", "apb_pclk";
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 307                 reg-shift = <2>;
 308                 reg-io-width = <4>;
 309                 status = "disabled";
 310         };
 311
 312         uart1: serial@11020000 {
 313                 compatible = "snps,dw-apb-uart";
 314                 reg = <0x11020000 0x100>;
 315                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 316                 clock-frequency = <24000000>;
 317                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 318                 clock-names = "baudclk", "apb_pclk";
 319                 pinctrl-names = "default";
 320                 pinctrl-0 = <&uart1_xfer>;
 321                 reg-shift = <2>;
 322                 reg-io-width = <4>;
 323                 status = "disabled";
 324         };
 325
 326         uart2: serial@11030000 {
 327                 compatible = "snps,dw-apb-uart";
 328                 reg = <0x11030000 0x100>;
 329                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 330                 clock-frequency = <24000000>;
 331                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 332                 clock-names = "baudclk", "apb_pclk";
 333                 pinctrl-names = "default";
 334                 pinctrl-0 = <&uart2_xfer>;
 335                 reg-shift = <2>;
 336                 reg-io-width = <4>;
 337                 status = "disabled";
 338         };
 339
 340         efuse: efuse@11040000 {
 341                 compatible = "rockchip,rk3228-efuse";
 342                 reg = <0x11040000 0x20>;
 343                 clocks = <&cru PCLK_EFUSE_256>;
 344                 clock-names = "pclk_efuse";
 345                 #address-cells = <1>;
 346                 #size-cells = <1>;
 347
 348                 /* Data cells */
 349                 efuse_id: id@7 {
 350                         reg = <0x7 0x10>;
 351                 };
 352                 cpu_leakage: cpu_leakage@17 {
 353                         reg = <0x17 0x1>;
 354                 };
 355         };
 356
 357         i2c0: i2c@11050000 {
 358                 compatible = "rockchip,rk3228-i2c";
 359                 reg = <0x11050000 0x1000>;
 360                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363                 clock-names = "i2c";
 364                 clocks = <&cru PCLK_I2C0>;
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&i2c0_xfer>;
 367                 status = "disabled";
 368         };
 369
 370         i2c1: i2c@11060000 {
 371                 compatible = "rockchip,rk3228-i2c";
 372                 reg = <0x11060000 0x1000>;
 373                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376                 clock-names = "i2c";
 377                 clocks = <&cru PCLK_I2C1>;
 378                 pinctrl-names = "default";
 379                 pinctrl-0 = <&i2c1_xfer>;
 380                 status = "disabled";
 381         };
 382
 383         i2c2: i2c@11070000 {
 384                 compatible = "rockchip,rk3228-i2c";
 385                 reg = <0x11070000 0x1000>;
 386                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389                 clock-names = "i2c";
 390                 clocks = <&cru PCLK_I2C2>;
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&i2c2_xfer>;
 393                 status = "disabled";
 394         };
 395
 396         i2c3: i2c@11080000 {
 397                 compatible = "rockchip,rk3228-i2c";
 398                 reg = <0x11080000 0x1000>;
 399                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 clock-names = "i2c";
 403                 clocks = <&cru PCLK_I2C3>;
 404                 pinctrl-names = "default";
 405                 pinctrl-0 = <&i2c3_xfer>;
 406                 status = "disabled";
 407         };
 408
 409         spi0: spi@11090000 {
 410                 compatible = "rockchip,rk3228-spi";
 411                 reg = <0x11090000 0x1000>;
 412                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 413                 #address-cells = <1>;
 414                 #size-cells = <0>;
 415                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 416                 clock-names = "spiclk", "apb_pclk";
 417                 pinctrl-names = "default";
 418                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 419                 status = "disabled";
 420         };
 421
 422         wdt: watchdog@110a0000 {
 423                 compatible = "snps,dw-wdt";
 424                 reg = <0x110a0000 0x100>;
 425                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&cru PCLK_CPU>;
 427                 status = "disabled";
 428         };
 429
 430         pwm0: pwm@110b0000 {
 431                 compatible = "rockchip,rk3288-pwm";
 432                 reg = <0x110b0000 0x10>;
 433                 #pwm-cells = <3>;
 434                 clocks = <&cru PCLK_PWM>;
 435                 clock-names = "pwm";
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&pwm0_pin>;
 438                 status = "disabled";
 439         };
 440
 441         pwm1: pwm@110b0010 {
 442                 compatible = "rockchip,rk3288-pwm";
 443                 reg = <0x110b0010 0x10>;
 444                 #pwm-cells = <3>;
 445                 clocks = <&cru PCLK_PWM>;
 446                 clock-names = "pwm";
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&pwm1_pin>;
 449                 status = "disabled";
 450         };
 451
 452         pwm2: pwm@110b0020 {
 453                 compatible = "rockchip,rk3288-pwm";
 454                 reg = <0x110b0020 0x10>;
 455                 #pwm-cells = <3>;
 456                 clocks = <&cru PCLK_PWM>;
 457                 clock-names = "pwm";
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&pwm2_pin>;
 460                 status = "disabled";
 461         };
 462
 463         pwm3: pwm@110b0030 {
 464                 compatible = "rockchip,rk3288-pwm";
 465                 reg = <0x110b0030 0x10>;
 466                 #pwm-cells = <2>;
 467                 clocks = <&cru PCLK_PWM>;
 468                 clock-names = "pwm";
 469                 pinctrl-names = "default";
 470                 pinctrl-0 = <&pwm3_pin>;
 471                 status = "disabled";
 472         };
 473
 474         timer: timer@110c0000 {
 475                 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
 476                 reg = <0x110c0000 0x20>;
 477                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 478                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 479                 clock-names = "timer", "pclk";
 480         };
 481
 482         cru: clock-controller@110e0000 {
 483                 compatible = "rockchip,rk3228-cru";
 484                 reg = <0x110e0000 0x1000>;
 485                 rockchip,grf = <&grf>;
 486                 #clock-cells = <1>;
 487                 #reset-cells = <1>;
 488                 assigned-clocks =
 489                         <&cru PLL_GPLL>, <&cru ARMCLK>,
 490                         <&cru PLL_CPLL>, <&cru ACLK_PERI>,
 491                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 492                         <&cru ACLK_CPU>, <&cru HCLK_CPU>,
 493                         <&cru PCLK_CPU>;
 494                 assigned-clock-rates =
 495                         <594000000>, <816000000>,
 496                         <500000000>, <150000000>,
 497                         <150000000>, <75000000>,
 498                         <150000000>, <150000000>,
 499                         <75000000>;
 500         };
 501
 502         thermal-zones {
 503                 cpu_thermal: cpu-thermal {
 504                         polling-delay-passive = <100>; /* milliseconds */
 505                         polling-delay = <5000>; /* milliseconds */
 506
 507                         thermal-sensors = <&tsadc 0>;
 508
 509                         trips {
 510                                 cpu_alert0: cpu_alert0 {
 511                                         temperature = <70000>; /* millicelsius */
 512                                         hysteresis = <2000>; /* millicelsius */
 513                                         type = "passive";
 514                                 };
 515                                 cpu_alert1: cpu_alert1 {
 516                                         temperature = <75000>; /* millicelsius */
 517                                         hysteresis = <2000>; /* millicelsius */
 518                                         type = "passive";
 519                                 };
 520                                 cpu_crit: cpu_crit {
 521                                         temperature = <90000>; /* millicelsius */
 522                                         hysteresis = <2000>; /* millicelsius */
 523                                         type = "critical";
 524                                 };
 525                         };
 526
 527                         cooling-maps {
 528                                 map0 {
 529                                         trip = <&cpu_alert0>;
 530                                         cooling-device =
 531                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 532                                 };
 533                                 map1 {
 534                                         trip = <&cpu_alert1>;
 535                                         cooling-device =
 536                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 537                                 };
 538                         };
 539                 };
 540         };
 541
 542         tsadc: tsadc@11150000 {
 543                 compatible = "rockchip,rk3228-tsadc";
 544                 reg = <0x11150000 0x100>;
 545                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 546                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 547                 clock-names = "tsadc", "apb_pclk";
 548                 assigned-clocks = <&cru SCLK_TSADC>;
 549                 assigned-clock-rates = <32768>;
 550                 resets = <&cru SRST_TSADC>;
 551                 reset-names = "tsadc-apb";
 552                 pinctrl-names = "init", "default", "sleep";
 553                 pinctrl-0 = <&otp_gpio>;
 554                 pinctrl-1 = <&otp_out>;
 555                 pinctrl-2 = <&otp_gpio>;
 556                 #thermal-sensor-cells = <0>;
 557                 rockchip,hw-tshut-temp = <95000>;
 558                 status = "disabled";
 559         };
 560
 561         gpu: gpu@20000000 {
 562                 compatible = "rockchip,rk3228-mali", "arm,mali-400";
 563                 reg = <0x20000000 0x10000>;
 564                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 565                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 566                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 567                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 568                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 569                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 570                 interrupt-names = "gp",
 571                                   "gpmmu",
 572                                   "pp0",
 573                                   "ppmmu0",
 574                                   "pp1",
 575                                   "ppmmu1";
 576                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 577                 clock-names = "core", "bus";
 578                 resets = <&cru SRST_GPU_A>;
 579                 status = "disabled";
 580         };
 581
 582         vpu_mmu: iommu@20020800 {
 583                 compatible = "rockchip,iommu";
 584                 reg = <0x20020800 0x100>;
 585                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 586                 interrupt-names = "vpu_mmu";
 587                 iommu-cells = <0>;
 588                 status = "disabled";
 589         };
 590
 591         vdec_mmu: iommu@20030480 {
 592                 compatible = "rockchip,iommu";
 593                 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
 594                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 595                 interrupt-names = "vdec_mmu";
 596                 iommu-cells = <0>;
 597                 status = "disabled";
 598         };
 599
 600         vop_mmu: iommu@20053f00 {
 601                 compatible = "rockchip,iommu";
 602                 reg = <0x20053f00 0x100>;
 603                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 604                 interrupt-names = "vop_mmu";
 605                 iommu-cells = <0>;
 606                 status = "disabled";
 607         };
 608
 609         iep_mmu: iommu@20070800 {
 610                 compatible = "rockchip,iommu";
 611                 reg = <0x20070800 0x100>;
 612                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 613                 interrupt-names = "iep_mmu";
 614                 iommu-cells = <0>;
 615                 status = "disabled";
 616         };
 617
 618         sdmmc: dwmmc@30000000 {
 619                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 620                 reg = <0x30000000 0x4000>;
 621                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 622                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 623                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 624                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 625                 fifo-depth = <0x100>;
 626                 pinctrl-names = "default";
 627                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
 628                 status = "disabled";
 629         };
 630
 631         sdio: dwmmc@30010000 {
 632                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 633                 reg = <0x30010000 0x4000>;
 634                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 635                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 636                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 637                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 638                 fifo-depth = <0x100>;
 639                 pinctrl-names = "default";
 640                 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
 641                 status = "disabled";
 642         };
 643
 644         emmc: dwmmc@30020000 {
 645                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 646                 reg = <0x30020000 0x4000>;
 647                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 648                 clock-frequency = <37500000>;
 649                 max-frequency = <37500000>;
 650                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 651                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 652                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 653                 bus-width = <8>;
 654                 default-sample-phase = <158>;
 655                 fifo-depth = <0x100>;
 656                 pinctrl-names = "default";
 657                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 658                 resets = <&cru SRST_EMMC>;
 659                 reset-names = "reset";
 660                 status = "disabled";
 661         };
 662
 663         usb_otg: usb@30040000 {
 664                 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
 665                              "snps,dwc2";
 666                 reg = <0x30040000 0x40000>;
 667                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 668                 clocks = <&cru HCLK_OTG>;
 669                 clock-names = "otg";
 670                 dr_mode = "otg";
 671                 g-np-tx-fifo-size = <16>;
 672                 g-rx-fifo-size = <280>;
 673                 g-tx-fifo-size = <256 128 128 64 32 16>;
 674                 g-use-dma;
 675                 phys = <&u2phy0_otg>;
 676                 phy-names = "usb2-phy";
 677                 status = "disabled";
 678         };
 679
 680         usb_host0_ehci: usb@30080000 {
 681                 compatible = "generic-ehci";
 682                 reg = <0x30080000 0x20000>;
 683                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 684                 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
 685                 clock-names = "usbhost", "utmi";
 686                 phys = <&u2phy0_host>;
 687                 phy-names = "usb";
 688                 status = "disabled";
 689         };
 690
 691         usb_host0_ohci: usb@300a0000 {
 692                 compatible = "generic-ohci";
 693                 reg = <0x300a0000 0x20000>;
 694                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 695                 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
 696                 clock-names = "usbhost", "utmi";
 697                 phys = <&u2phy0_host>;
 698                 phy-names = "usb";
 699                 status = "disabled";
 700         };
 701
 702         usb_host1_ehci: usb@300c0000 {
 703                 compatible = "generic-ehci";
 704                 reg = <0x300c0000 0x20000>;
 705                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 706                 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
 707                 clock-names = "usbhost", "utmi";
 708                 phys = <&u2phy1_otg>;
 709                 phy-names = "usb";
 710                 status = "disabled";
 711         };
 712
 713         usb_host1_ohci: usb@300e0000 {
 714                 compatible = "generic-ohci";
 715                 reg = <0x300e0000 0x20000>;
 716                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 717                 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
 718                 clock-names = "usbhost", "utmi";
 719                 phys = <&u2phy1_otg>;
 720                 phy-names = "usb";
 721                 status = "disabled";
 722         };
 723
 724         usb_host2_ehci: usb@30100000 {
 725                 compatible = "generic-ehci";
 726                 reg = <0x30100000 0x20000>;
 727                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 728                 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
 729                 phys = <&u2phy1_host>;
 730                 phy-names = "usb";
 731                 clock-names = "usbhost", "utmi";
 732                 status = "disabled";
 733         };
 734
 735         usb_host2_ohci: usb@30120000 {
 736                 compatible = "generic-ohci";
 737                 reg = <0x30120000 0x20000>;
 738                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 739                 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
 740                 clock-names = "usbhost", "utmi";
 741                 phys = <&u2phy1_host>;
 742                 phy-names = "usb";
 743                 status = "disabled";
 744         };
 745
 746         gmac: ethernet@30200000 {
 747                 compatible = "rockchip,rk3228-gmac";
 748                 reg = <0x30200000 0x10000>;
 749                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 750                 interrupt-names = "macirq";
 751                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 752                         <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
 753                         <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
 754                         <&cru PCLK_GMAC>;
 755                 clock-names = "stmmaceth", "mac_clk_rx",
 756                         "mac_clk_tx", "clk_mac_ref",
 757                         "clk_mac_refout", "aclk_mac",
 758                         "pclk_mac";
 759                 resets = <&cru SRST_GMAC>;
 760                 reset-names = "stmmaceth";
 761                 rockchip,grf = <&grf>;
 762                 status = "disabled";
 763         };
 764
 765         gic: interrupt-controller@32010000 {
 766                 compatible = "arm,gic-400";
 767                 interrupt-controller;
 768                 #interrupt-cells = <3>;
 769                 #address-cells = <0>;
 770
 771                 reg = <0x32011000 0x1000>,
 772                       <0x32012000 0x2000>,
 773                       <0x32014000 0x2000>,
 774                       <0x32016000 0x2000>;
 775                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 776         };
 777
 778         pinctrl: pinctrl {
 779                 compatible = "rockchip,rk3228-pinctrl";
 780                 rockchip,grf = <&grf>;
 781                 #address-cells = <1>;
 782                 #size-cells = <1>;
 783                 ranges;
 784
 785                 gpio0: gpio0@11110000 {
 786                         compatible = "rockchip,gpio-bank";
 787                         reg = <0x11110000 0x100>;
 788                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 789                         clocks = <&cru PCLK_GPIO0>;
 790
 791                         gpio-controller;
 792                         #gpio-cells = <2>;
 793
 794                         interrupt-controller;
 795                         #interrupt-cells = <2>;
 796                 };
 797
 798                 gpio1: gpio1@11120000 {
 799                         compatible = "rockchip,gpio-bank";
 800                         reg = <0x11120000 0x100>;
 801                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 802                         clocks = <&cru PCLK_GPIO1>;
 803
 804                         gpio-controller;
 805                         #gpio-cells = <2>;
 806
 807                         interrupt-controller;
 808                         #interrupt-cells = <2>;
 809                 };
 810
 811                 gpio2: gpio2@11130000 {
 812                         compatible = "rockchip,gpio-bank";
 813                         reg = <0x11130000 0x100>;
 814                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 815                         clocks = <&cru PCLK_GPIO2>;
 816
 817                         gpio-controller;
 818                         #gpio-cells = <2>;
 819
 820                         interrupt-controller;
 821                         #interrupt-cells = <2>;
 822                 };
 823
 824                 gpio3: gpio3@11140000 {
 825                         compatible = "rockchip,gpio-bank";
 826                         reg = <0x11140000 0x100>;
 827                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 828                         clocks = <&cru PCLK_GPIO3>;
 829
 830                         gpio-controller;
 831                         #gpio-cells = <2>;
 832
 833                         interrupt-controller;
 834                         #interrupt-cells = <2>;
 835                 };
 836
 837                 pcfg_pull_up: pcfg-pull-up {
 838                         bias-pull-up;
 839                 };
 840
 841                 pcfg_pull_down: pcfg-pull-down {
 842                         bias-pull-down;
 843                 };
 844
 845                 pcfg_pull_none: pcfg-pull-none {
 846                         bias-disable;
 847                 };
 848
 849                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 850                         drive-strength = <12>;
 851                 };
 852
 853                 sdmmc {
 854                         sdmmc_clk: sdmmc-clk {
 855                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
 856                         };
 857
 858                         sdmmc_cmd: sdmmc-cmd {
 859                                 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
 860                         };
 861
 862                         sdmmc_bus4: sdmmc-bus4 {
 863                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
 864                                                 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
 865                                                 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
 866                                                 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
 867                         };
 868                 };
 869
 870                 sdio {
 871                         sdio_clk: sdio-clk {
 872                                 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
 873                         };
 874
 875                         sdio_cmd: sdio-cmd {
 876                                 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
 877                         };
 878
 879                         sdio_bus4: sdio-bus4 {
 880                                 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
 881                                                 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
 882                                                 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
 883                                                 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
 884                         };
 885                 };
 886
 887                 emmc {
 888                         emmc_clk: emmc-clk {
 889                                 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
 890                         };
 891
 892                         emmc_cmd: emmc-cmd {
 893                                 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
 894                         };
 895
 896                         emmc_bus8: emmc-bus8 {
 897                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
 898                                                 <1 25 RK_FUNC_2 &pcfg_pull_none>,
 899                                                 <1 26 RK_FUNC_2 &pcfg_pull_none>,
 900                                                 <1 27 RK_FUNC_2 &pcfg_pull_none>,
 901                                                 <1 28 RK_FUNC_2 &pcfg_pull_none>,
 902                                                 <1 29 RK_FUNC_2 &pcfg_pull_none>,
 903                                                 <1 30 RK_FUNC_2 &pcfg_pull_none>,
 904                                                 <1 31 RK_FUNC_2 &pcfg_pull_none>;
 905                         };
 906                 };
 907
 908                 gmac {
 909                         rgmii_pins: rgmii-pins {
 910                                 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
 911                                                 <2 12 RK_FUNC_1 &pcfg_pull_none>,
 912                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>,
 913                                                 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 914                                                 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 915                                                 <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 916                                                 <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 917                                                 <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 918                                                 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 919                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
 920                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
 921                                                 <2 21 RK_FUNC_2 &pcfg_pull_none>,
 922                                                 <2 20 RK_FUNC_2 &pcfg_pull_none>,
 923                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>,
 924                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>;
 925                         };
 926
 927                         rmii_pins: rmii-pins {
 928                                 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
 929                                                 <2 12 RK_FUNC_1 &pcfg_pull_none>,
 930                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>,
 931                                                 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 932                                                 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 933                                                 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 934                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
 935                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
 936                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
 937                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>;
 938                         };
 939
 940                         phy_pins: phy-pins {
 941                                 rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
 942                                                 <2 8 RK_FUNC_2 &pcfg_pull_none>;
 943                         };
 944                 };
 945
 946                 i2c0 {
 947                         i2c0_xfer: i2c0-xfer {
 948                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 949                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 950                         };
 951                 };
 952
 953                 i2c1 {
 954                         i2c1_xfer: i2c1-xfer {
 955                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 956                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 957                         };
 958                 };
 959
 960                 i2c2 {
 961                         i2c2_xfer: i2c2-xfer {
 962                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 963                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 964                         };
 965                 };
 966
 967                 i2c3 {
 968                         i2c3_xfer: i2c3-xfer {
 969                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 970                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 971                         };
 972                 };
 973
 974                 spi-0 {
 975                         spi0_clk: spi0-clk {
 976                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>;
 977                         };
 978                         spi0_cs0: spi0-cs0 {
 979                                 rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>;
 980                         };
 981                         spi0_tx: spi0-tx {
 982                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
 983                         };
 984                         spi0_rx: spi0-rx {
 985                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
 986                         };
 987                         spi0_cs1: spi0-cs1 {
 988                                 rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>;
 989                         };
 990                 };
 991
 992                 spi-1 {
 993                         spi1_clk: spi1-clk {
 994                                 rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>;
 995                         };
 996                         spi1_cs0: spi1-cs0 {
 997                                 rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>;
 998                         };
 999                         spi1_rx: spi1-rx {
1000                                 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>;
1001                         };
1002                         spi1_tx: spi1-tx {
1003                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>;
1004                         };
1005                         spi1_cs1: spi1-cs1 {
1006                                 rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>;
1007                         };
1008                 };
1009
1010                 i2s1 {
1011                         i2s1_bus: i2s1-bus {
1012                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
1013                                                 <0 9 RK_FUNC_1 &pcfg_pull_none>,
1014                                                 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1015                                                 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1016                                                 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1017                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1018                                                 <1 2 RK_FUNC_2 &pcfg_pull_none>,
1019                                                 <1 4 RK_FUNC_2 &pcfg_pull_none>,
1020                                                 <1 5 RK_FUNC_2 &pcfg_pull_none>;
1021                         };
1022                 };
1023
1024                 pwm0 {
1025                         pwm0_pin: pwm0-pin {
1026                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
1027                         };
1028                 };
1029
1030                 pwm1 {
1031                         pwm1_pin: pwm1-pin {
1032                                 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
1033                         };
1034                 };
1035
1036                 pwm2 {
1037                         pwm2_pin: pwm2-pin {
1038                                 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
1039                         };
1040                 };
1041
1042                 pwm3 {
1043                         pwm3_pin: pwm3-pin {
1044                                 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
1045                         };
1046                 };
1047
1048                 spdif {
1049                         spdif_tx: spdif-tx {
1050                                 rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>;
1051                         };
1052                 };
1053
1054                 tsadc {
1055                         otp_gpio: otp-gpio {
1056                                 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
1057                         };
1058
1059                         otp_out: otp-out {
1060                                 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
1061                         };
1062                 };
1063
1064                 uart0 {
1065                         uart0_xfer: uart0-xfer {
1066                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
1067                                                 <2 27 RK_FUNC_1 &pcfg_pull_none>;
1068                         };
1069
1070                         uart0_cts: uart0-cts {
1071                                 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
1072                         };
1073
1074                         uart0_rts: uart0-rts {
1075                                 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
1076                         };
1077                 };
1078
1079                 uart1 {
1080                         uart1_xfer: uart1-xfer {
1081                                 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
1082                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>;
1083                         };
1084
1085                         uart1_cts: uart1-cts {
1086                                 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
1087                         };
1088
1089                         uart1_rts: uart1-rts {
1090                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
1091                         };
1092                 };
1093
1094                 uart2 {
1095                         uart2_xfer: uart2-xfer {
1096                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1097                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
1098                         };
1099
1100                         uart21_xfer: uart21-xfer {
1101                                 rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
1102                                                 <1 9 RK_FUNC_2 &pcfg_pull_none>;
1103                         };
1104
1105                         uart2_cts: uart2-cts {
1106                                 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
1107                         };
1108
1109                         uart2_rts: uart2-rts {
1110                                 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
1111                         };
1112                 };
1113         };
1114 };