arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/power/r8a7794-sysc.h>
  16
  17 / {
  18         compatible = "renesas,r8a7794";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 spi0 = &qspi;
  33                 vin0 = &vin0;
  34                 vin1 = &vin1;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a7";
  44                         reg = <0>;
  45                         clock-frequency = <1000000000>;
  46                         power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
  47                         next-level-cache = <&L2_CA7>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <1>;
  54                         clock-frequency = <1000000000>;
  55                         power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
  56                         next-level-cache = <&L2_CA7>;
  57                 };
  58
  59                 L2_CA7: cache-controller@0 {
  60                         compatible = "cache";
  61                         reg = <0>;
  62                         power-domains = <&sysc R8A7794_PD_CA7_SCU>;
  63                         cache-unified;
  64                         cache-level = <2>;
  65                 };
  66         };
  67
  68         gic: interrupt-controller@f1001000 {
  69                 compatible = "arm,gic-400";
  70                 #interrupt-cells = <3>;
  71                 #address-cells = <0>;
  72                 interrupt-controller;
  73                 reg = <0 0xf1001000 0 0x1000>,
  74                         <0 0xf1002000 0 0x1000>,
  75                         <0 0xf1004000 0 0x2000>,
  76                         <0 0xf1006000 0 0x2000>;
  77                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  78         };
  79
  80         gpio0: gpio@e6050000 {
  81                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  82                 reg = <0 0xe6050000 0 0x50>;
  83                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  84                 #gpio-cells = <2>;
  85                 gpio-controller;
  86                 gpio-ranges = <&pfc 0 0 32>;
  87                 #interrupt-cells = <2>;
  88                 interrupt-controller;
  89                 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
  90                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
  91         };
  92
  93         gpio1: gpio@e6051000 {
  94                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  95                 reg = <0 0xe6051000 0 0x50>;
  96                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  97                 #gpio-cells = <2>;
  98                 gpio-controller;
  99                 gpio-ranges = <&pfc 0 32 26>;
 100                 #interrupt-cells = <2>;
 101                 interrupt-controller;
 102                 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
 103                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 104         };
 105
 106         gpio2: gpio@e6052000 {
 107                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 108                 reg = <0 0xe6052000 0 0x50>;
 109                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 110                 #gpio-cells = <2>;
 111                 gpio-controller;
 112                 gpio-ranges = <&pfc 0 64 32>;
 113                 #interrupt-cells = <2>;
 114                 interrupt-controller;
 115                 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
 116                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 117         };
 118
 119         gpio3: gpio@e6053000 {
 120                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 121                 reg = <0 0xe6053000 0 0x50>;
 122                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 123                 #gpio-cells = <2>;
 124                 gpio-controller;
 125                 gpio-ranges = <&pfc 0 96 32>;
 126                 #interrupt-cells = <2>;
 127                 interrupt-controller;
 128                 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
 129                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 130         };
 131
 132         gpio4: gpio@e6054000 {
 133                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 134                 reg = <0 0xe6054000 0 0x50>;
 135                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 136                 #gpio-cells = <2>;
 137                 gpio-controller;
 138                 gpio-ranges = <&pfc 0 128 32>;
 139                 #interrupt-cells = <2>;
 140                 interrupt-controller;
 141                 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
 142                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 143         };
 144
 145         gpio5: gpio@e6055000 {
 146                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 147                 reg = <0 0xe6055000 0 0x50>;
 148                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 149                 #gpio-cells = <2>;
 150                 gpio-controller;
 151                 gpio-ranges = <&pfc 0 160 28>;
 152                 #interrupt-cells = <2>;
 153                 interrupt-controller;
 154                 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
 155                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 156         };
 157
 158         gpio6: gpio@e6055400 {
 159                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 160                 reg = <0 0xe6055400 0 0x50>;
 161                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 162                 #gpio-cells = <2>;
 163                 gpio-controller;
 164                 gpio-ranges = <&pfc 0 192 26>;
 165                 #interrupt-cells = <2>;
 166                 interrupt-controller;
 167                 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
 168                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 169         };
 170
 171         cmt0: timer@ffca0000 {
 172                 compatible = "renesas,cmt-48-gen2";
 173                 reg = <0 0xffca0000 0 0x1004>;
 174                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
 177                 clock-names = "fck";
 178                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 179
 180                 renesas,channels-mask = <0x60>;
 181
 182                 status = "disabled";
 183         };
 184
 185         cmt1: timer@e6130000 {
 186                 compatible = "renesas,cmt-48-gen2";
 187                 reg = <0 0xe6130000 0 0x1004>;
 188                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 196                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
 197                 clock-names = "fck";
 198                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 199
 200                 renesas,channels-mask = <0xff>;
 201
 202                 status = "disabled";
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv7-timer";
 207                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 208                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 210                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 211         };
 212
 213         irqc0: interrupt-controller@e61c0000 {
 214                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
 215                 #interrupt-cells = <2>;
 216                 interrupt-controller;
 217                 reg = <0 0xe61c0000 0 0x200>;
 218                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 223                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 224                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
 229                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 230         };
 231
 232         pfc: pin-controller@e6060000 {
 233                 compatible = "renesas,pfc-r8a7794";
 234                 reg = <0 0xe6060000 0 0x11c>;
 235         };
 236
 237         dmac0: dma-controller@e6700000 {
 238                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 239                 reg = <0 0xe6700000 0 0x20000>;
 240                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 241                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 242                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 243                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 244                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 245                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 246                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 247                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 248                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 249                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 250                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 251                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 252                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 253                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 254                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 255                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 256                 interrupt-names = "error",
 257                                 "ch0", "ch1", "ch2", "ch3",
 258                                 "ch4", "ch5", "ch6", "ch7",
 259                                 "ch8", "ch9", "ch10", "ch11",
 260                                 "ch12", "ch13", "ch14";
 261                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 262                 clock-names = "fck";
 263                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 264                 #dma-cells = <1>;
 265                 dma-channels = <15>;
 266         };
 267
 268         dmac1: dma-controller@e6720000 {
 269                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 270                 reg = <0 0xe6720000 0 0x20000>;
 271                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 272                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 273                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 274                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 275                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 276                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 277                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 278                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 279                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 280                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 281                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 282                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 283                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 284                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 285                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 286                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 287                 interrupt-names = "error",
 288                                 "ch0", "ch1", "ch2", "ch3",
 289                                 "ch4", "ch5", "ch6", "ch7",
 290                                 "ch8", "ch9", "ch10", "ch11",
 291                                 "ch12", "ch13", "ch14";
 292                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 293                 clock-names = "fck";
 294                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 295                 #dma-cells = <1>;
 296                 dma-channels = <15>;
 297         };
 298
 299         audma0: dma-controller@ec700000 {
 300                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 301                 reg = <0 0xec700000 0 0x10000>;
 302                 interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 303                                  GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 304                                  GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 305                                  GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 306                                  GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 307                                  GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 308                                  GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 309                                  GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 310                                  GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 311                                  GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 312                                  GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 313                                  GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 314                                  GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 315                                  GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 316                 interrupt-names = "error",
 317                                   "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
 318                                   "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
 319                                   "ch12";
 320                 clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
 321                 clock-names = "fck";
 322                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 323                 #dma-cells = <1>;
 324                 dma-channels = <13>;
 325         };
 326
 327         scifa0: serial@e6c40000 {
 328                 compatible = "renesas,scifa-r8a7794",
 329                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 330                 reg = <0 0xe6c40000 0 64>;
 331                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 332                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 333                 clock-names = "fck";
 334                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 335                        <&dmac1 0x21>, <&dmac1 0x22>;
 336                 dma-names = "tx", "rx", "tx", "rx";
 337                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 338                 status = "disabled";
 339         };
 340
 341         scifa1: serial@e6c50000 {
 342                 compatible = "renesas,scifa-r8a7794",
 343                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 344                 reg = <0 0xe6c50000 0 64>;
 345                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 346                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 347                 clock-names = "fck";
 348                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 349                        <&dmac1 0x25>, <&dmac1 0x26>;
 350                 dma-names = "tx", "rx", "tx", "rx";
 351                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 352                 status = "disabled";
 353         };
 354
 355         scifa2: serial@e6c60000 {
 356                 compatible = "renesas,scifa-r8a7794",
 357                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 358                 reg = <0 0xe6c60000 0 64>;
 359                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 360                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 361                 clock-names = "fck";
 362                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 363                        <&dmac1 0x27>, <&dmac1 0x28>;
 364                 dma-names = "tx", "rx", "tx", "rx";
 365                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 366                 status = "disabled";
 367         };
 368
 369         scifa3: serial@e6c70000 {
 370                 compatible = "renesas,scifa-r8a7794",
 371                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 372                 reg = <0 0xe6c70000 0 64>;
 373                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 374                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 375                 clock-names = "fck";
 376                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 377                        <&dmac1 0x1b>, <&dmac1 0x1c>;
 378                 dma-names = "tx", "rx", "tx", "rx";
 379                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 380                 status = "disabled";
 381         };
 382
 383         scifa4: serial@e6c78000 {
 384                 compatible = "renesas,scifa-r8a7794",
 385                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 386                 reg = <0 0xe6c78000 0 64>;
 387                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 388                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 389                 clock-names = "fck";
 390                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 391                        <&dmac1 0x1f>, <&dmac1 0x20>;
 392                 dma-names = "tx", "rx", "tx", "rx";
 393                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 394                 status = "disabled";
 395         };
 396
 397         scifa5: serial@e6c80000 {
 398                 compatible = "renesas,scifa-r8a7794",
 399                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 400                 reg = <0 0xe6c80000 0 64>;
 401                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 402                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 403                 clock-names = "fck";
 404                 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 405                        <&dmac1 0x23>, <&dmac1 0x24>;
 406                 dma-names = "tx", "rx", "tx", "rx";
 407                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 408                 status = "disabled";
 409         };
 410
 411         scifb0: serial@e6c20000 {
 412                 compatible = "renesas,scifb-r8a7794",
 413                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 414                 reg = <0 0xe6c20000 0 0x100>;
 415                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 416                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 417                 clock-names = "fck";
 418                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 419                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 420                 dma-names = "tx", "rx", "tx", "rx";
 421                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 422                 status = "disabled";
 423         };
 424
 425         scifb1: serial@e6c30000 {
 426                 compatible = "renesas,scifb-r8a7794",
 427                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 428                 reg = <0 0xe6c30000 0 0x100>;
 429                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 430                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 431                 clock-names = "fck";
 432                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 433                        <&dmac1 0x19>, <&dmac1 0x1a>;
 434                 dma-names = "tx", "rx", "tx", "rx";
 435                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 436                 status = "disabled";
 437         };
 438
 439         scifb2: serial@e6ce0000 {
 440                 compatible = "renesas,scifb-r8a7794",
 441                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 442                 reg = <0 0xe6ce0000 0 0x100>;
 443                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 444                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 445                 clock-names = "fck";
 446                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 447                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 448                 dma-names = "tx", "rx", "tx", "rx";
 449                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 450                 status = "disabled";
 451         };
 452
 453         scif0: serial@e6e60000 {
 454                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 455                              "renesas,scif";
 456                 reg = <0 0xe6e60000 0 64>;
 457                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 458                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
 459                          <&scif_clk>;
 460                 clock-names = "fck", "brg_int", "scif_clk";
 461                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 462                        <&dmac1 0x29>, <&dmac1 0x2a>;
 463                 dma-names = "tx", "rx", "tx", "rx";
 464                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 465                 status = "disabled";
 466         };
 467
 468         scif1: serial@e6e68000 {
 469                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 470                              "renesas,scif";
 471                 reg = <0 0xe6e68000 0 64>;
 472                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 473                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
 474                          <&scif_clk>;
 475                 clock-names = "fck", "brg_int", "scif_clk";
 476                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 477                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 478                 dma-names = "tx", "rx", "tx", "rx";
 479                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 480                 status = "disabled";
 481         };
 482
 483         scif2: serial@e6e58000 {
 484                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 485                              "renesas,scif";
 486                 reg = <0 0xe6e58000 0 64>;
 487                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 488                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
 489                          <&scif_clk>;
 490                 clock-names = "fck", "brg_int", "scif_clk";
 491                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 492                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 493                 dma-names = "tx", "rx", "tx", "rx";
 494                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 495                 status = "disabled";
 496         };
 497
 498         scif3: serial@e6ea8000 {
 499                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 500                              "renesas,scif";
 501                 reg = <0 0xe6ea8000 0 64>;
 502                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 503                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
 504                          <&scif_clk>;
 505                 clock-names = "fck", "brg_int", "scif_clk";
 506                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 507                        <&dmac1 0x2f>, <&dmac1 0x30>;
 508                 dma-names = "tx", "rx", "tx", "rx";
 509                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 510                 status = "disabled";
 511         };
 512
 513         scif4: serial@e6ee0000 {
 514                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 515                              "renesas,scif";
 516                 reg = <0 0xe6ee0000 0 64>;
 517                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 518                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
 519                          <&scif_clk>;
 520                 clock-names = "fck", "brg_int", "scif_clk";
 521                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 522                        <&dmac1 0xfb>, <&dmac1 0xfc>;
 523                 dma-names = "tx", "rx", "tx", "rx";
 524                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 525                 status = "disabled";
 526         };
 527
 528         scif5: serial@e6ee8000 {
 529                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 530                              "renesas,scif";
 531                 reg = <0 0xe6ee8000 0 64>;
 532                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 533                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
 534                          <&scif_clk>;
 535                 clock-names = "fck", "brg_int", "scif_clk";
 536                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 537                        <&dmac1 0xfd>, <&dmac1 0xfe>;
 538                 dma-names = "tx", "rx", "tx", "rx";
 539                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 540                 status = "disabled";
 541         };
 542
 543         hscif0: serial@e62c0000 {
 544                 compatible = "renesas,hscif-r8a7794",
 545                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 546                 reg = <0 0xe62c0000 0 96>;
 547                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 548                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
 549                          <&scif_clk>;
 550                 clock-names = "fck", "brg_int", "scif_clk";
 551                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 552                        <&dmac1 0x39>, <&dmac1 0x3a>;
 553                 dma-names = "tx", "rx", "tx", "rx";
 554                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 555                 status = "disabled";
 556         };
 557
 558         hscif1: serial@e62c8000 {
 559                 compatible = "renesas,hscif-r8a7794",
 560                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 561                 reg = <0 0xe62c8000 0 96>;
 562                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 563                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
 564                          <&scif_clk>;
 565                 clock-names = "fck", "brg_int", "scif_clk";
 566                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 567                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 568                 dma-names = "tx", "rx", "tx", "rx";
 569                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 570                 status = "disabled";
 571         };
 572
 573         hscif2: serial@e62d0000 {
 574                 compatible = "renesas,hscif-r8a7794",
 575                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 576                 reg = <0 0xe62d0000 0 96>;
 577                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 578                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
 579                          <&scif_clk>;
 580                 clock-names = "fck", "brg_int", "scif_clk";
 581                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 582                        <&dmac1 0x3b>, <&dmac1 0x3c>;
 583                 dma-names = "tx", "rx", "tx", "rx";
 584                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 585                 status = "disabled";
 586         };
 587
 588         ether: ethernet@ee700000 {
 589                 compatible = "renesas,ether-r8a7794";
 590                 reg = <0 0xee700000 0 0x400>;
 591                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 592                 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
 593                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 594                 phy-mode = "rmii";
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 status = "disabled";
 598         };
 599
 600         avb: ethernet@e6800000 {
 601                 compatible = "renesas,etheravb-r8a7794",
 602                              "renesas,etheravb-rcar-gen2";
 603                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 604                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 605                 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
 606                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 607                 #address-cells = <1>;
 608                 #size-cells = <0>;
 609                 status = "disabled";
 610         };
 611
 612         /* The memory map in the User's Manual maps the cores to bus numbers */
 613         i2c0: i2c@e6508000 {
 614                 compatible = "renesas,i2c-r8a7794";
 615                 reg = <0 0xe6508000 0 0x40>;
 616                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 617                 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
 618                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 619                 #address-cells = <1>;
 620                 #size-cells = <0>;
 621                 i2c-scl-internal-delay-ns = <6>;
 622                 status = "disabled";
 623         };
 624
 625         i2c1: i2c@e6518000 {
 626                 compatible = "renesas,i2c-r8a7794";
 627                 reg = <0 0xe6518000 0 0x40>;
 628                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 629                 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
 630                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 631                 #address-cells = <1>;
 632                 #size-cells = <0>;
 633                 i2c-scl-internal-delay-ns = <6>;
 634                 status = "disabled";
 635         };
 636
 637         i2c2: i2c@e6530000 {
 638                 compatible = "renesas,i2c-r8a7794";
 639                 reg = <0 0xe6530000 0 0x40>;
 640                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 641                 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
 642                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 643                 #address-cells = <1>;
 644                 #size-cells = <0>;
 645                 i2c-scl-internal-delay-ns = <6>;
 646                 status = "disabled";
 647         };
 648
 649         i2c3: i2c@e6540000 {
 650                 compatible = "renesas,i2c-r8a7794";
 651                 reg = <0 0xe6540000 0 0x40>;
 652                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 653                 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
 654                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 i2c-scl-internal-delay-ns = <6>;
 658                 status = "disabled";
 659         };
 660
 661         i2c4: i2c@e6520000 {
 662                 compatible = "renesas,i2c-r8a7794";
 663                 reg = <0 0xe6520000 0 0x40>;
 664                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 665                 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
 666                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 667                 #address-cells = <1>;
 668                 #size-cells = <0>;
 669                 i2c-scl-internal-delay-ns = <6>;
 670                 status = "disabled";
 671         };
 672
 673         i2c5: i2c@e6528000 {
 674                 compatible = "renesas,i2c-r8a7794";
 675                 reg = <0 0xe6528000 0 0x40>;
 676                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 677                 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
 678                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 679                 #address-cells = <1>;
 680                 #size-cells = <0>;
 681                 i2c-scl-internal-delay-ns = <6>;
 682                 status = "disabled";
 683         };
 684
 685         i2c6: i2c@e6500000 {
 686                 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
 687                 reg = <0 0xe6500000 0 0x425>;
 688                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 689                 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
 690                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 691                        <&dmac1 0x61>, <&dmac1 0x62>;
 692                 dma-names = "tx", "rx", "tx", "rx";
 693                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 694                 #address-cells = <1>;
 695                 #size-cells = <0>;
 696                 status = "disabled";
 697         };
 698
 699         i2c7: i2c@e6510000 {
 700                 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
 701                 reg = <0 0xe6510000 0 0x425>;
 702                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 703                 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
 704                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 705                        <&dmac1 0x65>, <&dmac1 0x66>;
 706                 dma-names = "tx", "rx", "tx", "rx";
 707                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 708                 #address-cells = <1>;
 709                 #size-cells = <0>;
 710                 status = "disabled";
 711         };
 712
 713         mmcif0: mmc@ee200000 {
 714                 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
 715                 reg = <0 0xee200000 0 0x80>;
 716                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 717                 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
 718                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 719                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 720                 dma-names = "tx", "rx", "tx", "rx";
 721                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 722                 reg-io-width = <4>;
 723                 status = "disabled";
 724         };
 725
 726         sdhi0: sd@ee100000 {
 727                 compatible = "renesas,sdhi-r8a7794";
 728                 reg = <0 0xee100000 0 0x328>;
 729                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 730                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
 731                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 732                        <&dmac1 0xcd>, <&dmac1 0xce>;
 733                 dma-names = "tx", "rx", "tx", "rx";
 734                 max-frequency = <195000000>;
 735                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 736                 status = "disabled";
 737         };
 738
 739         sdhi1: sd@ee140000 {
 740                 compatible = "renesas,sdhi-r8a7794";
 741                 reg = <0 0xee140000 0 0x100>;
 742                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 743                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
 744                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 745                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 746                 dma-names = "tx", "rx", "tx", "rx";
 747                 max-frequency = <97500000>;
 748                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 749                 status = "disabled";
 750         };
 751
 752         sdhi2: sd@ee160000 {
 753                 compatible = "renesas,sdhi-r8a7794";
 754                 reg = <0 0xee160000 0 0x100>;
 755                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 756                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
 757                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 758                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 759                 dma-names = "tx", "rx", "tx", "rx";
 760                 max-frequency = <97500000>;
 761                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 762                 status = "disabled";
 763         };
 764
 765         qspi: spi@e6b10000 {
 766                 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
 767                 reg = <0 0xe6b10000 0 0x2c>;
 768                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 769                 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
 770                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 771                        <&dmac1 0x17>, <&dmac1 0x18>;
 772                 dma-names = "tx", "rx", "tx", "rx";
 773                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 774                 num-cs = <1>;
 775                 #address-cells = <1>;
 776                 #size-cells = <0>;
 777                 status = "disabled";
 778         };
 779
 780         vin0: video@e6ef0000 {
 781                 compatible = "renesas,vin-r8a7794";
 782                 reg = <0 0xe6ef0000 0 0x1000>;
 783                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 784                 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
 785                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 786                 status = "disabled";
 787         };
 788
 789         vin1: video@e6ef1000 {
 790                 compatible = "renesas,vin-r8a7794";
 791                 reg = <0 0xe6ef1000 0 0x1000>;
 792                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 793                 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
 794                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 795                 status = "disabled";
 796         };
 797
 798         pci0: pci@ee090000 {
 799                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 800                 device_type = "pci";
 801                 reg = <0 0xee090000 0 0xc00>,
 802                       <0 0xee080000 0 0x1100>;
 803                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 804                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 805                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 806                 status = "disabled";
 807
 808                 bus-range = <0 0>;
 809                 #address-cells = <3>;
 810                 #size-cells = <2>;
 811                 #interrupt-cells = <1>;
 812                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 813                 interrupt-map-mask = <0xff00 0 0 0x7>;
 814                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 815                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 816                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 817
 818                 usb@0,1 {
 819                         reg = <0x800 0 0 0 0>;
 820                         device_type = "pci";
 821                         phys = <&usb0 0>;
 822                         phy-names = "usb";
 823                 };
 824
 825                 usb@0,2 {
 826                         reg = <0x1000 0 0 0 0>;
 827                         device_type = "pci";
 828                         phys = <&usb0 0>;
 829                         phy-names = "usb";
 830                 };
 831         };
 832
 833         pci1: pci@ee0d0000 {
 834                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 835                 device_type = "pci";
 836                 reg = <0 0xee0d0000 0 0xc00>,
 837                       <0 0xee0c0000 0 0x1100>;
 838                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 839                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 840                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 841                 status = "disabled";
 842
 843                 bus-range = <1 1>;
 844                 #address-cells = <3>;
 845                 #size-cells = <2>;
 846                 #interrupt-cells = <1>;
 847                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 848                 interrupt-map-mask = <0xff00 0 0 0x7>;
 849                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 850                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 851                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 852
 853                 usb@0,1 {
 854                         reg = <0x800 0 0 0 0>;
 855                         device_type = "pci";
 856                         phys = <&usb2 0>;
 857                         phy-names = "usb";
 858                 };
 859
 860                 usb@0,2 {
 861                         reg = <0x1000 0 0 0 0>;
 862                         device_type = "pci";
 863                         phys = <&usb2 0>;
 864                         phy-names = "usb";
 865                 };
 866         };
 867
 868         hsusb: usb@e6590000 {
 869                 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
 870                 reg = <0 0xe6590000 0 0x100>;
 871                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 872                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 873                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 874                 renesas,buswait = <4>;
 875                 phys = <&usb0 1>;
 876                 phy-names = "usb";
 877                 status = "disabled";
 878         };
 879
 880         usbphy: usb-phy@e6590100 {
 881                 compatible = "renesas,usb-phy-r8a7794";
 882                 reg = <0 0xe6590100 0 0x100>;
 883                 #address-cells = <1>;
 884                 #size-cells = <0>;
 885                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 886                 clock-names = "usbhs";
 887                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 888                 status = "disabled";
 889
 890                 usb0: usb-channel@0 {
 891                         reg = <0>;
 892                         #phy-cells = <1>;
 893                 };
 894                 usb2: usb-channel@2 {
 895                         reg = <2>;
 896                         #phy-cells = <1>;
 897                 };
 898         };
 899
 900         vsp1@fe928000 {
 901                 compatible = "renesas,vsp1";
 902                 reg = <0 0xfe928000 0 0x8000>;
 903                 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 904                 clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>;
 905                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 906         };
 907
 908         vsp1@fe930000 {
 909                 compatible = "renesas,vsp1";
 910                 reg = <0 0xfe930000 0 0x8000>;
 911                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 912                 clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>;
 913                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 914         };
 915
 916         du: display@feb00000 {
 917                 compatible = "renesas,du-r8a7794";
 918                 reg = <0 0xfeb00000 0 0x40000>;
 919                 reg-names = "du";
 920                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 921                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 922                 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
 923                          <&mstp7_clks R8A7794_CLK_DU0>;
 924                 clock-names = "du.0", "du.1";
 925                 status = "disabled";
 926
 927                 ports {
 928                         #address-cells = <1>;
 929                         #size-cells = <0>;
 930
 931                         port@0 {
 932                                 reg = <0>;
 933                                 du_out_rgb0: endpoint {
 934                                 };
 935                         };
 936                         port@1 {
 937                                 reg = <1>;
 938                                 du_out_rgb1: endpoint {
 939                                 };
 940                         };
 941                 };
 942         };
 943
 944         can0: can@e6e80000 {
 945                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 946                 reg = <0 0xe6e80000 0 0x1000>;
 947                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 948                 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
 949                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 950                 clock-names = "clkp1", "clkp2", "can_clk";
 951                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 952                 status = "disabled";
 953         };
 954
 955         can1: can@e6e88000 {
 956                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 957                 reg = <0 0xe6e88000 0 0x1000>;
 958                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 959                 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
 960                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 961                 clock-names = "clkp1", "clkp2", "can_clk";
 962                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 963                 status = "disabled";
 964         };
 965
 966         clocks {
 967                 #address-cells = <2>;
 968                 #size-cells = <2>;
 969                 ranges;
 970
 971                 /* External root clock */
 972                 extal_clk: extal {
 973                         compatible = "fixed-clock";
 974                         #clock-cells = <0>;
 975                         /* This value must be overriden by the board. */
 976                         clock-frequency = <0>;
 977                 };
 978
 979                 /* External USB clock - can be overridden by the board */
 980                 usb_extal_clk: usb_extal {
 981                         compatible = "fixed-clock";
 982                         #clock-cells = <0>;
 983                         clock-frequency = <48000000>;
 984                 };
 985
 986                 /* External CAN clock */
 987                 can_clk: can {
 988                         compatible = "fixed-clock";
 989                         #clock-cells = <0>;
 990                         /* This value must be overridden by the board. */
 991                         clock-frequency = <0>;
 992                 };
 993
 994                 /* External SCIF clock */
 995                 scif_clk: scif {
 996                         compatible = "fixed-clock";
 997                         #clock-cells = <0>;
 998                         /* This value must be overridden by the board. */
 999                         clock-frequency = <0>;
1000                 };
1001
1002                 /*
1003                  * The external audio clocks are configured  as 0 Hz fixed
1004                  * frequency clocks by default.  Boards that provide audio
1005                  * clocks should override them.
1006                  */
1007                 audio_clka: audio_clka {
1008                         compatible = "fixed-clock";
1009                         #clock-cells = <0>;
1010                         clock-frequency = <0>;
1011                 };
1012                 audio_clkb: audio_clkb {
1013                         compatible = "fixed-clock";
1014                         #clock-cells = <0>;
1015                         clock-frequency = <0>;
1016                 };
1017                 audio_clkc: audio_clkc {
1018                         compatible = "fixed-clock";
1019                         #clock-cells = <0>;
1020                         clock-frequency = <0>;
1021                 };
1022
1023                 /* Special CPG clocks */
1024                 cpg_clocks: cpg_clocks@e6150000 {
1025                         compatible = "renesas,r8a7794-cpg-clocks",
1026                                      "renesas,rcar-gen2-cpg-clocks";
1027                         reg = <0 0xe6150000 0 0x1000>;
1028                         clocks = <&extal_clk &usb_extal_clk>;
1029                         #clock-cells = <1>;
1030                         clock-output-names = "main", "pll0", "pll1", "pll3",
1031                                              "lb", "qspi", "sdh", "sd0", "rcan";
1032                         #power-domain-cells = <0>;
1033                 };
1034                 /* Variable factor clocks */
1035                 sd2_clk: sd2@e6150078 {
1036                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1037                         reg = <0 0xe6150078 0 4>;
1038                         clocks = <&pll1_div2_clk>;
1039                         #clock-cells = <0>;
1040                 };
1041                 sd3_clk: sd3@e615026c {
1042                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1043                         reg = <0 0xe615026c 0 4>;
1044                         clocks = <&pll1_div2_clk>;
1045                         #clock-cells = <0>;
1046                 };
1047                 mmc0_clk: mmc0@e6150240 {
1048                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1049                         reg = <0 0xe6150240 0 4>;
1050                         clocks = <&pll1_div2_clk>;
1051                         #clock-cells = <0>;
1052                 };
1053
1054                 /* Fixed factor clocks */
1055                 pll1_div2_clk: pll1_div2 {
1056                         compatible = "fixed-factor-clock";
1057                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1058                         #clock-cells = <0>;
1059                         clock-div = <2>;
1060                         clock-mult = <1>;
1061                 };
1062                 zg_clk: zg {
1063                         compatible = "fixed-factor-clock";
1064                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1065                         #clock-cells = <0>;
1066                         clock-div = <6>;
1067                         clock-mult = <1>;
1068                 };
1069                 zx_clk: zx {
1070                         compatible = "fixed-factor-clock";
1071                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1072                         #clock-cells = <0>;
1073                         clock-div = <3>;
1074                         clock-mult = <1>;
1075                 };
1076                 zs_clk: zs {
1077                         compatible = "fixed-factor-clock";
1078                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1079                         #clock-cells = <0>;
1080                         clock-div = <6>;
1081                         clock-mult = <1>;
1082                 };
1083                 hp_clk: hp {
1084                         compatible = "fixed-factor-clock";
1085                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1086                         #clock-cells = <0>;
1087                         clock-div = <12>;
1088                         clock-mult = <1>;
1089                 };
1090                 i_clk: i {
1091                         compatible = "fixed-factor-clock";
1092                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1093                         #clock-cells = <0>;
1094                         clock-div = <2>;
1095                         clock-mult = <1>;
1096                 };
1097                 b_clk: b {
1098                         compatible = "fixed-factor-clock";
1099                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1100                         #clock-cells = <0>;
1101                         clock-div = <12>;
1102                         clock-mult = <1>;
1103                 };
1104                 p_clk: p {
1105                         compatible = "fixed-factor-clock";
1106                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1107                         #clock-cells = <0>;
1108                         clock-div = <24>;
1109                         clock-mult = <1>;
1110                 };
1111                 cl_clk: cl {
1112                         compatible = "fixed-factor-clock";
1113                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1114                         #clock-cells = <0>;
1115                         clock-div = <48>;
1116                         clock-mult = <1>;
1117                 };
1118                 m2_clk: m2 {
1119                         compatible = "fixed-factor-clock";
1120                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1121                         #clock-cells = <0>;
1122                         clock-div = <8>;
1123                         clock-mult = <1>;
1124                 };
1125                 rclk_clk: rclk {
1126                         compatible = "fixed-factor-clock";
1127                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1128                         #clock-cells = <0>;
1129                         clock-div = <(48 * 1024)>;
1130                         clock-mult = <1>;
1131                 };
1132                 oscclk_clk: oscclk {
1133                         compatible = "fixed-factor-clock";
1134                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1135                         #clock-cells = <0>;
1136                         clock-div = <(12 * 1024)>;
1137                         clock-mult = <1>;
1138                 };
1139                 zb3_clk: zb3 {
1140                         compatible = "fixed-factor-clock";
1141                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1142                         #clock-cells = <0>;
1143                         clock-div = <4>;
1144                         clock-mult = <1>;
1145                 };
1146                 zb3d2_clk: zb3d2 {
1147                         compatible = "fixed-factor-clock";
1148                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1149                         #clock-cells = <0>;
1150                         clock-div = <8>;
1151                         clock-mult = <1>;
1152                 };
1153                 ddr_clk: ddr {
1154                         compatible = "fixed-factor-clock";
1155                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1156                         #clock-cells = <0>;
1157                         clock-div = <8>;
1158                         clock-mult = <1>;
1159                 };
1160                 mp_clk: mp {
1161                         compatible = "fixed-factor-clock";
1162                         clocks = <&pll1_div2_clk>;
1163                         #clock-cells = <0>;
1164                         clock-div = <15>;
1165                         clock-mult = <1>;
1166                 };
1167                 cp_clk: cp {
1168                         compatible = "fixed-factor-clock";
1169                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1170                         #clock-cells = <0>;
1171                         clock-div = <48>;
1172                         clock-mult = <1>;
1173                 };
1174
1175                 acp_clk: acp {
1176                         compatible = "fixed-factor-clock";
1177                         clocks = <&extal_clk>;
1178                         #clock-cells = <0>;
1179                         clock-div = <2>;
1180                         clock-mult = <1>;
1181                 };
1182
1183                 /* Gate clocks */
1184                 mstp0_clks: mstp0_clks@e6150130 {
1185                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1186                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1187                         clocks = <&mp_clk>;
1188                         #clock-cells = <1>;
1189                         clock-indices = <R8A7794_CLK_MSIOF0>;
1190                         clock-output-names = "msiof0";
1191                 };
1192                 mstp1_clks: mstp1_clks@e6150134 {
1193                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1194                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1195                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1196                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1197                                  <&zs_clk>, <&zs_clk>;
1198                         #clock-cells = <1>;
1199                         clock-indices = <
1200                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1201                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1202                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1203                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
1204                         >;
1205                         clock-output-names =
1206                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1207                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
1208                 };
1209                 mstp2_clks: mstp2_clks@e6150138 {
1210                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1211                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1212                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1213                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1214                                  <&zs_clk>, <&zs_clk>;
1215                         #clock-cells = <1>;
1216                         clock-indices = <
1217                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1218                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1219                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
1220                                 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
1221                         >;
1222                         clock-output-names =
1223                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1224                                 "scifb1", "msiof1", "scifb2",
1225                                 "sys-dmac1", "sys-dmac0";
1226                 };
1227                 mstp3_clks: mstp3_clks@e615013c {
1228                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1229                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1230                         clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1231                                  <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
1232                                  <&hp_clk>, <&hp_clk>;
1233                         #clock-cells = <1>;
1234                         clock-indices = <
1235                                 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1236                                 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
1237                                 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
1238                                 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1239                         >;
1240                         clock-output-names =
1241                                 "sdhi2", "sdhi1", "sdhi0",
1242                                 "mmcif0", "i2c6", "i2c7",
1243                                 "cmt1", "usbdmac0", "usbdmac1";
1244                 };
1245                 mstp4_clks: mstp4_clks@e6150140 {
1246                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1247                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1248                         clocks = <&cp_clk>;
1249                         #clock-cells = <1>;
1250                         clock-indices = <R8A7794_CLK_IRQC>;
1251                         clock-output-names = "irqc";
1252                 };
1253                 mstp5_clks: mstp5_clks@e6150144 {
1254                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1255                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1256                         clocks = <&hp_clk>, <&p_clk>;
1257                         #clock-cells = <1>;
1258                         clock-indices = <R8A7794_CLK_AUDIO_DMAC0
1259                                          R8A7794_CLK_PWM>;
1260                         clock-output-names = "audmac0", "pwm";
1261                 };
1262                 mstp7_clks: mstp7_clks@e615014c {
1263                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1264                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1265                         clocks = <&mp_clk>, <&hp_clk>,
1266                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1267                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1268                                  <&zx_clk>;
1269                         #clock-cells = <1>;
1270                         clock-indices = <
1271                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1272                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1273                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1274                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1275                                 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
1276                         >;
1277                         clock-output-names =
1278                                 "ehci", "hsusb",
1279                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1280                                 "scif3", "scif2", "scif1", "scif0", "du0";
1281                 };
1282                 mstp8_clks: mstp8_clks@e6150990 {
1283                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1284                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1285                         clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
1286                         #clock-cells = <1>;
1287                         clock-indices = <
1288                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1289                                 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
1290                         >;
1291                         clock-output-names =
1292                                 "vin1", "vin0", "etheravb", "ether";
1293                 };
1294                 mstp9_clks: mstp9_clks@e6150994 {
1295                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1296                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1297                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1298                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
1299                                  <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
1300                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1301                                  <&hp_clk>, <&hp_clk>;
1302                         #clock-cells = <1>;
1303                         clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1304                                          R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1305                                          R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1306                                          R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
1307                                          R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
1308                                          R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1309                                          R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1310                                          R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1311                         clock-output-names =
1312                                 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1313                                 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
1314                                 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1315                 };
1316                 mstp10_clks: mstp10_clks@e6150998 {
1317                         compatible = "renesas,r8a7794-mstp-clocks",
1318                                      "renesas,cpg-mstp-clocks";
1319                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1320                         clocks = <&p_clk>,
1321                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1322                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1323                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1324                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1325                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1326                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1327                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1328                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1329                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1330                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1331                                  <&p_clk>,
1332                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1333                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1334                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1335                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1336                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1337                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1338                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1339                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1340                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1341                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>;
1342                         #clock-cells = <1>;
1343                         clock-indices = <R8A7794_CLK_SSI_ALL
1344                                          R8A7794_CLK_SSI9 R8A7794_CLK_SSI8
1345                                          R8A7794_CLK_SSI7 R8A7794_CLK_SSI6
1346                                          R8A7794_CLK_SSI5 R8A7794_CLK_SSI4
1347                                          R8A7794_CLK_SSI3 R8A7794_CLK_SSI2
1348                                          R8A7794_CLK_SSI1 R8A7794_CLK_SSI0
1349                                          R8A7794_CLK_SCU_ALL
1350                                          R8A7794_CLK_SCU_DVC1
1351                                          R8A7794_CLK_SCU_DVC0
1352                                          R8A7794_CLK_SCU_CTU1_MIX1
1353                                          R8A7794_CLK_SCU_CTU0_MIX0
1354                                          R8A7794_CLK_SCU_SRC6
1355                                          R8A7794_CLK_SCU_SRC5
1356                                          R8A7794_CLK_SCU_SRC4
1357                                          R8A7794_CLK_SCU_SRC3
1358                                          R8A7794_CLK_SCU_SRC2
1359                                          R8A7794_CLK_SCU_SRC1>;
1360                         clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7",
1361                                              "ssi6", "ssi5", "ssi4", "ssi3",
1362                                              "ssi2", "ssi1", "ssi0",
1363                                              "scu-all", "scu-dvc1", "scu-dvc0",
1364                                              "scu-ctu1-mix1", "scu-ctu0-mix0",
1365                                              "scu-src6", "scu-src5", "scu-src4",
1366                                              "scu-src3", "scu-src2", "scu-src1";
1367                 };
1368                 mstp11_clks: mstp11_clks@e615099c {
1369                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1370                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1371                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1372                         #clock-cells = <1>;
1373                         clock-indices = <
1374                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1375                         >;
1376                         clock-output-names = "scifa3", "scifa4", "scifa5";
1377                 };
1378         };
1379
1380         rst: reset-controller@e6160000 {
1381                 compatible = "renesas,r8a7794-rst";
1382                 reg = <0 0xe6160000 0 0x0100>;
1383         };
1384
1385         prr: chipid@ff000044 {
1386                 compatible = "renesas,prr";
1387                 reg = <0 0xff000044 0 4>;
1388         };
1389
1390         sysc: system-controller@e6180000 {
1391                 compatible = "renesas,r8a7794-sysc";
1392                 reg = <0 0xe6180000 0 0x0200>;
1393                 #power-domain-cells = <1>;
1394         };
1395
1396         ipmmu_sy0: mmu@e6280000 {
1397                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1398                 reg = <0 0xe6280000 0 0x1000>;
1399                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1400                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1401                 #iommu-cells = <1>;
1402                 status = "disabled";
1403         };
1404
1405         ipmmu_sy1: mmu@e6290000 {
1406                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1407                 reg = <0 0xe6290000 0 0x1000>;
1408                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1409                 #iommu-cells = <1>;
1410                 status = "disabled";
1411         };
1412
1413         ipmmu_ds: mmu@e6740000 {
1414                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1415                 reg = <0 0xe6740000 0 0x1000>;
1416                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1417                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1418                 #iommu-cells = <1>;
1419                 status = "disabled";
1420         };
1421
1422         ipmmu_mp: mmu@ec680000 {
1423                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1424                 reg = <0 0xec680000 0 0x1000>;
1425                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1426                 #iommu-cells = <1>;
1427                 status = "disabled";
1428         };
1429
1430         ipmmu_mx: mmu@fe951000 {
1431                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1432                 reg = <0 0xfe951000 0 0x1000>;
1433                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1434                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1435                 #iommu-cells = <1>;
1436                 status = "disabled";
1437         };
1438
1439         ipmmu_gp: mmu@e62a0000 {
1440                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1441                 reg = <0 0xe62a0000 0 0x1000>;
1442                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1443                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1444                 #iommu-cells = <1>;
1445                 status = "disabled";
1446         };
1447
1448         rcar_sound: sound@ec500000 {
1449                 /*
1450                  * #sound-dai-cells is required
1451                  *
1452                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1453                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1454                  */
1455                 compatible = "renesas,rcar_sound-r8a7794",
1456                              "renesas,rcar_sound-gen2";
1457                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1458                         <0 0xec5a0000 0 0x100>,  /* ADG */
1459                         <0 0xec540000 0 0x1000>, /* SSIU */
1460                         <0 0xec541000 0 0x280>,  /* SSI */
1461                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
1462                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1463
1464                 clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1465                          <&mstp10_clks R8A7794_CLK_SSI9>,
1466                          <&mstp10_clks R8A7794_CLK_SSI8>,
1467                          <&mstp10_clks R8A7794_CLK_SSI7>,
1468                          <&mstp10_clks R8A7794_CLK_SSI6>,
1469                          <&mstp10_clks R8A7794_CLK_SSI5>,
1470                          <&mstp10_clks R8A7794_CLK_SSI4>,
1471                          <&mstp10_clks R8A7794_CLK_SSI3>,
1472                          <&mstp10_clks R8A7794_CLK_SSI2>,
1473                          <&mstp10_clks R8A7794_CLK_SSI1>,
1474                          <&mstp10_clks R8A7794_CLK_SSI0>,
1475                          <&mstp10_clks R8A7794_CLK_SCU_SRC6>,
1476                          <&mstp10_clks R8A7794_CLK_SCU_SRC5>,
1477                          <&mstp10_clks R8A7794_CLK_SCU_SRC4>,
1478                          <&mstp10_clks R8A7794_CLK_SCU_SRC3>,
1479                          <&mstp10_clks R8A7794_CLK_SCU_SRC2>,
1480                          <&mstp10_clks R8A7794_CLK_SCU_SRC1>,
1481                          <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
1482                          <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
1483                          <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
1484                          <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
1485                          <&mstp10_clks R8A7794_CLK_SCU_DVC0>,
1486                          <&mstp10_clks R8A7794_CLK_SCU_DVC1>,
1487                          <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
1488                          <&m2_clk>;
1489                 clock-names = "ssi-all",
1490                               "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1491                               "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1492                               "src.6", "src.5", "src.4", "src.3", "src.2",
1493                               "src.1",
1494                               "ctu.0", "ctu.1",
1495                               "mix.0", "mix.1",
1496                               "dvc.0", "dvc.1",
1497                               "clk_a", "clk_b", "clk_c", "clk_i";
1498                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1499
1500                 status = "disabled";
1501
1502                 rcar_sound,dvc {
1503                         dvc0: dvc-0 {
1504                                 dmas = <&audma0 0xbc>;
1505                                 dma-names = "tx";
1506                         };
1507                         dvc1: dvc-1 {
1508                                 dmas = <&audma0 0xbe>;
1509                                 dma-names = "tx";
1510                         };
1511                 };
1512
1513                 rcar_sound,mix {
1514                         mix0: mix-0 { };
1515                         mix1: mix-1 { };
1516                 };
1517
1518                 rcar_sound,ctu {
1519                         ctu00: ctu-0 { };
1520                         ctu01: ctu-1 { };
1521                         ctu02: ctu-2 { };
1522                         ctu03: ctu-3 { };
1523                         ctu10: ctu-4 { };
1524                         ctu11: ctu-5 { };
1525                         ctu12: ctu-6 { };
1526                         ctu13: ctu-7 { };
1527                 };
1528
1529                 rcar_sound,src {
1530                         src-0 {
1531                                 status = "disabled";
1532                         };
1533                         src1: src-1 {
1534                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1535                                 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1536                                 dma-names = "rx", "tx";
1537                         };
1538                         src2: src-2 {
1539                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1540                                 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1541                                 dma-names = "rx", "tx";
1542                         };
1543                         src3: src-3 {
1544                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1545                                 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1546                                 dma-names = "rx", "tx";
1547                         };
1548                         src4: src-4 {
1549                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1550                                 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1551                                 dma-names = "rx", "tx";
1552                         };
1553                         src5: src-5 {
1554                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1555                                 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1556                                 dma-names = "rx", "tx";
1557                         };
1558                         src6: src-6 {
1559                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1560                                 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1561                                 dma-names = "rx", "tx";
1562                         };
1563                 };
1564
1565                 rcar_sound,ssi {
1566                         ssi0: ssi-0 {
1567                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1568                                 dmas = <&audma0 0x01>, <&audma0 0x02>,
1569                                        <&audma0 0x15>, <&audma0 0x16>;
1570                                 dma-names = "rx", "tx", "rxu", "txu";
1571                         };
1572                         ssi1: ssi-1 {
1573                                 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1574                                 dmas = <&audma0 0x03>, <&audma0 0x04>,
1575                                        <&audma0 0x49>, <&audma0 0x4a>;
1576                                 dma-names = "rx", "tx", "rxu", "txu";
1577                         };
1578                         ssi2: ssi-2 {
1579                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1580                                 dmas = <&audma0 0x05>, <&audma0 0x06>,
1581                                        <&audma0 0x63>, <&audma0 0x64>;
1582                                 dma-names = "rx", "tx", "rxu", "txu";
1583                         };
1584                         ssi3: ssi-3 {
1585                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1586                                 dmas = <&audma0 0x07>, <&audma0 0x08>,
1587                                        <&audma0 0x6f>, <&audma0 0x70>;
1588                                 dma-names = "rx", "tx", "rxu", "txu";
1589                         };
1590                         ssi4: ssi-4 {
1591                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1592                                 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1593                                        <&audma0 0x71>, <&audma0 0x72>;
1594                                 dma-names = "rx", "tx", "rxu", "txu";
1595                         };
1596                         ssi5: ssi-5 {
1597                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1598                                 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1599                                        <&audma0 0x73>, <&audma0 0x74>;
1600                                 dma-names = "rx", "tx", "rxu", "txu";
1601                         };
1602                         ssi6: ssi-6 {
1603                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1604                                 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1605                                        <&audma0 0x75>, <&audma0 0x76>;
1606                                 dma-names = "rx", "tx", "rxu", "txu";
1607                         };
1608                         ssi7: ssi-7 {
1609                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1610                                 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1611                                        <&audma0 0x79>, <&audma0 0x7a>;
1612                                 dma-names = "rx", "tx", "rxu", "txu";
1613                         };
1614                         ssi8: ssi-8 {
1615                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1616                                 dmas = <&audma0 0x11>, <&audma0 0x12>,
1617                                        <&audma0 0x7b>, <&audma0 0x7c>;
1618                                 dma-names = "rx", "tx", "rxu", "txu";
1619                         };
1620                         ssi9: ssi-9 {
1621                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1622                                 dmas = <&audma0 0x13>, <&audma0 0x14>,
1623                                        <&audma0 0x7d>, <&audma0 0x7e>;
1624                                 dma-names = "rx", "tx", "rxu", "txu";
1625                         };
1626                 };
1627         };
1628 };