arch/arm/boot/dts/r8a7793.dtsi

   1 /*
   2  * Device Tree Source for the r8a7793 SoC
   3  *
   4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7793-clock.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14 #include <dt-bindings/power/r8a7793-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a7793";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 i2c6 = &i2c6;
  30                 i2c7 = &i2c7;
  31                 i2c8 = &i2c8;
  32                 spi0 = &qspi;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38                 enable-method = "renesas,apmu";
  39
  40                 cpu0: cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0>;
  44                         clock-frequency = <1500000000>;
  45                         voltage-tolerance = <1>; /* 1% */
  46                         clocks = <&cpg_clocks R8A7793_CLK_Z>;
  47                         clock-latency = <300000>; /* 300 us */
  48                         power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
  49
  50                         /* kHz - uV - OPPs unknown yet */
  51                         operating-points = <1500000 1000000>,
  52                                            <1312500 1000000>,
  53                                            <1125000 1000000>,
  54                                            < 937500 1000000>,
  55                                            < 750000 1000000>,
  56                                            < 375000 1000000>;
  57                         next-level-cache = <&L2_CA15>;
  58                 };
  59
  60                 cpu1: cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a15";
  63                         reg = <1>;
  64                         clock-frequency = <1500000000>;
  65                         power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
  66                 };
  67
  68                 L2_CA15: cache-controller-0 {
  69                         compatible = "cache";
  70                         power-domains = <&sysc R8A7793_PD_CA15_SCU>;
  71                         cache-unified;
  72                         cache-level = <2>;
  73                 };
  74         };
  75
  76         apmu@e6152000 {
  77                 compatible = "renesas,r8a7793-apmu", "renesas,apmu";
  78                 reg = <0 0xe6152000 0 0x188>;
  79                 cpus = <&cpu0 &cpu1>;
  80         };
  81
  82         thermal-zones {
  83                 cpu_thermal: cpu-thermal {
  84                         polling-delay-passive   = <0>;
  85                         polling-delay           = <0>;
  86
  87                         thermal-sensors = <&thermal>;
  88
  89                         trips {
  90                                 cpu-crit {
  91                                         temperature     = <115000>;
  92                                         hysteresis      = <0>;
  93                                         type            = "critical";
  94                                 };
  95                         };
  96                         cooling-maps {
  97                         };
  98                 };
  99         };
 100
 101         gic: interrupt-controller@f1001000 {
 102                 compatible = "arm,gic-400";
 103                 #interrupt-cells = <3>;
 104                 #address-cells = <0>;
 105                 interrupt-controller;
 106                 reg = <0 0xf1001000 0 0x1000>,
 107                         <0 0xf1002000 0 0x2000>,
 108                         <0 0xf1004000 0 0x2000>,
 109                         <0 0xf1006000 0 0x2000>;
 110                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 111                 clocks = <&mstp4_clks R8A7793_CLK_INTC_SYS>;
 112                 clock-names = "clk";
 113                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 114         };
 115
 116         gpio0: gpio@e6050000 {
 117                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 118                 reg = <0 0xe6050000 0 0x50>;
 119                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 120                 #gpio-cells = <2>;
 121                 gpio-controller;
 122                 gpio-ranges = <&pfc 0 0 32>;
 123                 #interrupt-cells = <2>;
 124                 interrupt-controller;
 125                 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
 126                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 127         };
 128
 129         gpio1: gpio@e6051000 {
 130                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 131                 reg = <0 0xe6051000 0 0x50>;
 132                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 133                 #gpio-cells = <2>;
 134                 gpio-controller;
 135                 gpio-ranges = <&pfc 0 32 26>;
 136                 #interrupt-cells = <2>;
 137                 interrupt-controller;
 138                 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
 139                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 140         };
 141
 142         gpio2: gpio@e6052000 {
 143                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 144                 reg = <0 0xe6052000 0 0x50>;
 145                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 146                 #gpio-cells = <2>;
 147                 gpio-controller;
 148                 gpio-ranges = <&pfc 0 64 32>;
 149                 #interrupt-cells = <2>;
 150                 interrupt-controller;
 151                 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
 152                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 153         };
 154
 155         gpio3: gpio@e6053000 {
 156                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 157                 reg = <0 0xe6053000 0 0x50>;
 158                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 159                 #gpio-cells = <2>;
 160                 gpio-controller;
 161                 gpio-ranges = <&pfc 0 96 32>;
 162                 #interrupt-cells = <2>;
 163                 interrupt-controller;
 164                 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
 165                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 166         };
 167
 168         gpio4: gpio@e6054000 {
 169                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 170                 reg = <0 0xe6054000 0 0x50>;
 171                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 172                 #gpio-cells = <2>;
 173                 gpio-controller;
 174                 gpio-ranges = <&pfc 0 128 32>;
 175                 #interrupt-cells = <2>;
 176                 interrupt-controller;
 177                 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
 178                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 179         };
 180
 181         gpio5: gpio@e6055000 {
 182                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 183                 reg = <0 0xe6055000 0 0x50>;
 184                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 185                 #gpio-cells = <2>;
 186                 gpio-controller;
 187                 gpio-ranges = <&pfc 0 160 32>;
 188                 #interrupt-cells = <2>;
 189                 interrupt-controller;
 190                 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
 191                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 192         };
 193
 194         gpio6: gpio@e6055400 {
 195                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 196                 reg = <0 0xe6055400 0 0x50>;
 197                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 198                 #gpio-cells = <2>;
 199                 gpio-controller;
 200                 gpio-ranges = <&pfc 0 192 32>;
 201                 #interrupt-cells = <2>;
 202                 interrupt-controller;
 203                 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
 204                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 205         };
 206
 207         gpio7: gpio@e6055800 {
 208                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 209                 reg = <0 0xe6055800 0 0x50>;
 210                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 211                 #gpio-cells = <2>;
 212                 gpio-controller;
 213                 gpio-ranges = <&pfc 0 224 26>;
 214                 #interrupt-cells = <2>;
 215                 interrupt-controller;
 216                 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
 217                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 218         };
 219
 220         thermal: thermal@e61f0000 {
 221                 compatible =    "renesas,thermal-r8a7793",
 222                                 "renesas,rcar-gen2-thermal",
 223                                 "renesas,rcar-thermal";
 224                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 225                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 226                 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
 227                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 228                 #thermal-sensor-cells = <0>;
 229         };
 230
 231         timer {
 232                 compatible = "arm,armv7-timer";
 233                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 234                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 235                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 236                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 237         };
 238
 239         cmt0: timer@ffca0000 {
 240                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 241                 reg = <0 0xffca0000 0 0x1004>;
 242                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 243                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 244                 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
 245                 clock-names = "fck";
 246                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 247
 248                 renesas,channels-mask = <0x60>;
 249
 250                 status = "disabled";
 251         };
 252
 253         cmt1: timer@e6130000 {
 254                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 255                 reg = <0 0xe6130000 0 0x1004>;
 256                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 264                 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
 265                 clock-names = "fck";
 266                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 267
 268                 renesas,channels-mask = <0xff>;
 269
 270                 status = "disabled";
 271         };
 272
 273         irqc0: interrupt-controller@e61c0000 {
 274                 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
 275                 #interrupt-cells = <2>;
 276                 interrupt-controller;
 277                 reg = <0 0xe61c0000 0 0x200>;
 278                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
 289                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 290         };
 291
 292         dmac0: dma-controller@e6700000 {
 293                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 294                 reg = <0 0xe6700000 0 0x20000>;
 295                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 296                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 297                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 298                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 299                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 300                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 301                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 302                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 303                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 304                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 305                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 306                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 307                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 308                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 309                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 310                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 311                 interrupt-names = "error",
 312                                 "ch0", "ch1", "ch2", "ch3",
 313                                 "ch4", "ch5", "ch6", "ch7",
 314                                 "ch8", "ch9", "ch10", "ch11",
 315                                 "ch12", "ch13", "ch14";
 316                 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
 317                 clock-names = "fck";
 318                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 319                 #dma-cells = <1>;
 320                 dma-channels = <15>;
 321         };
 322
 323         dmac1: dma-controller@e6720000 {
 324                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 325                 reg = <0 0xe6720000 0 0x20000>;
 326                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 327                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 328                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 329                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 330                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 331                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 332                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 333                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 334                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 335                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 336                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 337                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 338                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 339                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 340                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 341                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 342                 interrupt-names = "error",
 343                                 "ch0", "ch1", "ch2", "ch3",
 344                                 "ch4", "ch5", "ch6", "ch7",
 345                                 "ch8", "ch9", "ch10", "ch11",
 346                                 "ch12", "ch13", "ch14";
 347                 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
 348                 clock-names = "fck";
 349                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 350                 #dma-cells = <1>;
 351                 dma-channels = <15>;
 352         };
 353
 354         audma0: dma-controller@ec700000 {
 355                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 356                 reg = <0 0xec700000 0 0x10000>;
 357                 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 358                               GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 359                               GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 360                               GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 361                               GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 362                               GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 363                               GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 364                               GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 365                               GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 366                               GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 367                               GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 368                               GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 369                               GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 370                               GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 371                 interrupt-names = "error",
 372                                 "ch0", "ch1", "ch2", "ch3",
 373                                 "ch4", "ch5", "ch6", "ch7",
 374                                 "ch8", "ch9", "ch10", "ch11",
 375                                 "ch12";
 376                 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
 377                 clock-names = "fck";
 378                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 379                 #dma-cells = <1>;
 380                 dma-channels = <13>;
 381         };
 382
 383         audma1: dma-controller@ec720000 {
 384                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 385                 reg = <0 0xec720000 0 0x10000>;
 386                 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
 387                               GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
 388                               GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
 389                               GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
 390                               GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
 391                               GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
 392                               GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
 393                               GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
 394                               GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
 395                               GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
 396                               GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
 397                               GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
 398                               GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
 399                               GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 400                 interrupt-names = "error",
 401                                 "ch0", "ch1", "ch2", "ch3",
 402                                 "ch4", "ch5", "ch6", "ch7",
 403                                 "ch8", "ch9", "ch10", "ch11",
 404                                 "ch12";
 405                 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
 406                 clock-names = "fck";
 407                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 408                 #dma-cells = <1>;
 409                 dma-channels = <13>;
 410         };
 411
 412         /* The memory map in the User's Manual maps the cores to bus numbers */
 413         i2c0: i2c@e6508000 {
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
 417                 reg = <0 0xe6508000 0 0x40>;
 418                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 419                 clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
 420                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 421                 i2c-scl-internal-delay-ns = <6>;
 422                 status = "disabled";
 423         };
 424
 425         i2c1: i2c@e6518000 {
 426                 #address-cells = <1>;
 427                 #size-cells = <0>;
 428                 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
 429                 reg = <0 0xe6518000 0 0x40>;
 430                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 431                 clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
 432                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 433                 i2c-scl-internal-delay-ns = <6>;
 434                 status = "disabled";
 435         };
 436
 437         i2c2: i2c@e6530000 {
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
 441                 reg = <0 0xe6530000 0 0x40>;
 442                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
 444                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 445                 i2c-scl-internal-delay-ns = <6>;
 446                 status = "disabled";
 447         };
 448
 449         i2c3: i2c@e6540000 {
 450                 #address-cells = <1>;
 451                 #size-cells = <0>;
 452                 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
 453                 reg = <0 0xe6540000 0 0x40>;
 454                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 455                 clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
 456                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 457                 i2c-scl-internal-delay-ns = <6>;
 458                 status = "disabled";
 459         };
 460
 461         i2c4: i2c@e6520000 {
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
 465                 reg = <0 0xe6520000 0 0x40>;
 466                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 467                 clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
 468                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 469                 i2c-scl-internal-delay-ns = <6>;
 470                 status = "disabled";
 471         };
 472
 473         i2c5: i2c@e6528000 {
 474                 /* doesn't need pinmux */
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
 478                 reg = <0 0xe6528000 0 0x40>;
 479                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 480                 clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
 481                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 482                 i2c-scl-internal-delay-ns = <110>;
 483                 status = "disabled";
 484         };
 485
 486         i2c6: i2c@e60b0000 {
 487                 /* doesn't need pinmux */
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
 491                              "renesas,rmobile-iic";
 492                 reg = <0 0xe60b0000 0 0x425>;
 493                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 494                 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
 495                 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
 496                        <&dmac1 0x77>, <&dmac1 0x78>;
 497                 dma-names = "tx", "rx", "tx", "rx";
 498                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 499                 status = "disabled";
 500         };
 501
 502         i2c7: i2c@e6500000 {
 503                 #address-cells = <1>;
 504                 #size-cells = <0>;
 505                 compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
 506                              "renesas,rmobile-iic";
 507                 reg = <0 0xe6500000 0 0x425>;
 508                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 509                 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
 510                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 511                        <&dmac1 0x61>, <&dmac1 0x62>;
 512                 dma-names = "tx", "rx", "tx", "rx";
 513                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 514                 status = "disabled";
 515         };
 516
 517         i2c8: i2c@e6510000 {
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
 521                              "renesas,rmobile-iic";
 522                 reg = <0 0xe6510000 0 0x425>;
 523                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 524                 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
 525                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 526                        <&dmac1 0x65>, <&dmac1 0x66>;
 527                 dma-names = "tx", "rx", "tx", "rx";
 528                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 529                 status = "disabled";
 530         };
 531
 532         pfc: pin-controller@e6060000 {
 533                 compatible = "renesas,pfc-r8a7793";
 534                 reg = <0 0xe6060000 0 0x250>;
 535         };
 536
 537         sdhi0: sd@ee100000 {
 538                 compatible = "renesas,sdhi-r8a7793";
 539                 reg = <0 0xee100000 0 0x328>;
 540                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 541                 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
 542                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 543                        <&dmac1 0xcd>, <&dmac1 0xce>;
 544                 dma-names = "tx", "rx", "tx", "rx";
 545                 max-frequency = <195000000>;
 546                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 547                 status = "disabled";
 548         };
 549
 550         sdhi1: sd@ee140000 {
 551                 compatible = "renesas,sdhi-r8a7793";
 552                 reg = <0 0xee140000 0 0x100>;
 553                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 554                 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
 555                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 556                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 557                 dma-names = "tx", "rx", "tx", "rx";
 558                 max-frequency = <97500000>;
 559                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 560                 status = "disabled";
 561         };
 562
 563         sdhi2: sd@ee160000 {
 564                 compatible = "renesas,sdhi-r8a7793";
 565                 reg = <0 0xee160000 0 0x100>;
 566                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 567                 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
 568                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 569                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 570                 dma-names = "tx", "rx", "tx", "rx";
 571                 max-frequency = <97500000>;
 572                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 573                 status = "disabled";
 574         };
 575
 576         mmcif0: mmc@ee200000 {
 577                 compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
 578                 reg = <0 0xee200000 0 0x80>;
 579                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 580                 clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>;
 581                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 582                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 583                 dma-names = "tx", "rx", "tx", "rx";
 584                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 585                 reg-io-width = <4>;
 586                 status = "disabled";
 587                 max-frequency = <97500000>;
 588         };
 589
 590         scifa0: serial@e6c40000 {
 591                 compatible = "renesas,scifa-r8a7793",
 592                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 593                 reg = <0 0xe6c40000 0 64>;
 594                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 595                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
 596                 clock-names = "fck";
 597                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 598                        <&dmac1 0x21>, <&dmac1 0x22>;
 599                 dma-names = "tx", "rx", "tx", "rx";
 600                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 601                 status = "disabled";
 602         };
 603
 604         scifa1: serial@e6c50000 {
 605                 compatible = "renesas,scifa-r8a7793",
 606                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 607                 reg = <0 0xe6c50000 0 64>;
 608                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 609                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
 610                 clock-names = "fck";
 611                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 612                        <&dmac1 0x25>, <&dmac1 0x26>;
 613                 dma-names = "tx", "rx", "tx", "rx";
 614                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 615                 status = "disabled";
 616         };
 617
 618         scifa2: serial@e6c60000 {
 619                 compatible = "renesas,scifa-r8a7793",
 620                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 621                 reg = <0 0xe6c60000 0 64>;
 622                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 623                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
 624                 clock-names = "fck";
 625                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 626                        <&dmac1 0x27>, <&dmac1 0x28>;
 627                 dma-names = "tx", "rx", "tx", "rx";
 628                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 629                 status = "disabled";
 630         };
 631
 632         scifa3: serial@e6c70000 {
 633                 compatible = "renesas,scifa-r8a7793",
 634                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 635                 reg = <0 0xe6c70000 0 64>;
 636                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 637                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
 638                 clock-names = "fck";
 639                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 640                        <&dmac1 0x1b>, <&dmac1 0x1c>;
 641                 dma-names = "tx", "rx", "tx", "rx";
 642                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 643                 status = "disabled";
 644         };
 645
 646         scifa4: serial@e6c78000 {
 647                 compatible = "renesas,scifa-r8a7793",
 648                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 649                 reg = <0 0xe6c78000 0 64>;
 650                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 651                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
 652                 clock-names = "fck";
 653                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 654                        <&dmac1 0x1f>, <&dmac1 0x20>;
 655                 dma-names = "tx", "rx", "tx", "rx";
 656                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 657                 status = "disabled";
 658         };
 659
 660         scifa5: serial@e6c80000 {
 661                 compatible = "renesas,scifa-r8a7793",
 662                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 663                 reg = <0 0xe6c80000 0 64>;
 664                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 665                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
 666                 clock-names = "fck";
 667                 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 668                        <&dmac1 0x23>, <&dmac1 0x24>;
 669                 dma-names = "tx", "rx", "tx", "rx";
 670                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 671                 status = "disabled";
 672         };
 673
 674         scifb0: serial@e6c20000 {
 675                 compatible = "renesas,scifb-r8a7793",
 676                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 677                 reg = <0 0xe6c20000 0 0x100>;
 678                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 679                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
 680                 clock-names = "fck";
 681                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 682                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 683                 dma-names = "tx", "rx", "tx", "rx";
 684                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 685                 status = "disabled";
 686         };
 687
 688         scifb1: serial@e6c30000 {
 689                 compatible = "renesas,scifb-r8a7793",
 690                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 691                 reg = <0 0xe6c30000 0 0x100>;
 692                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 693                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
 694                 clock-names = "fck";
 695                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 696                        <&dmac1 0x19>, <&dmac1 0x1a>;
 697                 dma-names = "tx", "rx", "tx", "rx";
 698                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 699                 status = "disabled";
 700         };
 701
 702         scifb2: serial@e6ce0000 {
 703                 compatible = "renesas,scifb-r8a7793",
 704                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 705                 reg = <0 0xe6ce0000 0 0x100>;
 706                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 707                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
 708                 clock-names = "fck";
 709                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 710                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 711                 dma-names = "tx", "rx", "tx", "rx";
 712                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 713                 status = "disabled";
 714         };
 715
 716         scif0: serial@e6e60000 {
 717                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 718                              "renesas,scif";
 719                 reg = <0 0xe6e60000 0 64>;
 720                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 721                 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
 722                          <&scif_clk>;
 723                 clock-names = "fck", "brg_int", "scif_clk";
 724                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 725                        <&dmac1 0x29>, <&dmac1 0x2a>;
 726                 dma-names = "tx", "rx", "tx", "rx";
 727                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 728                 status = "disabled";
 729         };
 730
 731         scif1: serial@e6e68000 {
 732                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 733                              "renesas,scif";
 734                 reg = <0 0xe6e68000 0 64>;
 735                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 736                 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
 737                          <&scif_clk>;
 738                 clock-names = "fck", "brg_int", "scif_clk";
 739                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 740                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 741                 dma-names = "tx", "rx", "tx", "rx";
 742                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 743                 status = "disabled";
 744         };
 745
 746         scif2: serial@e6e58000 {
 747                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 748                              "renesas,scif";
 749                 reg = <0 0xe6e58000 0 64>;
 750                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 751                 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
 752                          <&scif_clk>;
 753                 clock-names = "fck", "brg_int", "scif_clk";
 754                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 755                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 756                 dma-names = "tx", "rx", "tx", "rx";
 757                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 758                 status = "disabled";
 759         };
 760
 761         scif3: serial@e6ea8000 {
 762                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 763                              "renesas,scif";
 764                 reg = <0 0xe6ea8000 0 64>;
 765                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 766                 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
 767                          <&scif_clk>;
 768                 clock-names = "fck", "brg_int", "scif_clk";
 769                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 770                        <&dmac1 0x2f>, <&dmac1 0x30>;
 771                 dma-names = "tx", "rx", "tx", "rx";
 772                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 773                 status = "disabled";
 774         };
 775
 776         scif4: serial@e6ee0000 {
 777                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 778                              "renesas,scif";
 779                 reg = <0 0xe6ee0000 0 64>;
 780                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 781                 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
 782                          <&scif_clk>;
 783                 clock-names = "fck", "brg_int", "scif_clk";
 784                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 785                        <&dmac1 0xfb>, <&dmac1 0xfc>;
 786                 dma-names = "tx", "rx", "tx", "rx";
 787                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 788                 status = "disabled";
 789         };
 790
 791         scif5: serial@e6ee8000 {
 792                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 793                              "renesas,scif";
 794                 reg = <0 0xe6ee8000 0 64>;
 795                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 796                 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
 797                          <&scif_clk>;
 798                 clock-names = "fck", "brg_int", "scif_clk";
 799                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 800                        <&dmac1 0xfd>, <&dmac1 0xfe>;
 801                 dma-names = "tx", "rx", "tx", "rx";
 802                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 803                 status = "disabled";
 804         };
 805
 806         hscif0: serial@e62c0000 {
 807                 compatible = "renesas,hscif-r8a7793",
 808                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 809                 reg = <0 0xe62c0000 0 96>;
 810                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 811                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
 812                          <&scif_clk>;
 813                 clock-names = "fck", "brg_int", "scif_clk";
 814                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 815                        <&dmac1 0x39>, <&dmac1 0x3a>;
 816                 dma-names = "tx", "rx", "tx", "rx";
 817                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 818                 status = "disabled";
 819         };
 820
 821         hscif1: serial@e62c8000 {
 822                 compatible = "renesas,hscif-r8a7793",
 823                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 824                 reg = <0 0xe62c8000 0 96>;
 825                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 826                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
 827                          <&scif_clk>;
 828                 clock-names = "fck", "brg_int", "scif_clk";
 829                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 830                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 831                 dma-names = "tx", "rx", "tx", "rx";
 832                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 833                 status = "disabled";
 834         };
 835
 836         hscif2: serial@e62d0000 {
 837                 compatible = "renesas,hscif-r8a7793",
 838                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 839                 reg = <0 0xe62d0000 0 96>;
 840                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 841                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
 842                          <&scif_clk>;
 843                 clock-names = "fck", "brg_int", "scif_clk";
 844                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 845                        <&dmac1 0x3b>, <&dmac1 0x3c>;
 846                 dma-names = "tx", "rx", "tx", "rx";
 847                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 848                 status = "disabled";
 849         };
 850
 851         icram0: sram@e63a0000 {
 852                 compatible = "mmio-sram";
 853                 reg = <0 0xe63a0000 0 0x12000>;
 854         };
 855
 856         icram1: sram@e63c0000 {
 857                 compatible = "mmio-sram";
 858                 reg = <0 0xe63c0000 0 0x1000>;
 859         };
 860
 861         ether: ethernet@ee700000 {
 862                 compatible = "renesas,ether-r8a7793";
 863                 reg = <0 0xee700000 0 0x400>;
 864                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 865                 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
 866                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 867                 phy-mode = "rmii";
 868                 #address-cells = <1>;
 869                 #size-cells = <0>;
 870                 status = "disabled";
 871         };
 872
 873         vin0: video@e6ef0000 {
 874                 compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
 875                 reg = <0 0xe6ef0000 0 0x1000>;
 876                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 877                 clocks = <&mstp8_clks R8A7793_CLK_VIN0>;
 878                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 879                 status = "disabled";
 880         };
 881
 882         vin1: video@e6ef1000 {
 883                 compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
 884                 reg = <0 0xe6ef1000 0 0x1000>;
 885                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 886                 clocks = <&mstp8_clks R8A7793_CLK_VIN1>;
 887                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 888                 status = "disabled";
 889         };
 890
 891         vin2: video@e6ef2000 {
 892                 compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
 893                 reg = <0 0xe6ef2000 0 0x1000>;
 894                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 895                 clocks = <&mstp8_clks R8A7793_CLK_VIN2>;
 896                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 897                 status = "disabled";
 898         };
 899
 900         qspi: spi@e6b10000 {
 901                 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
 902                 reg = <0 0xe6b10000 0 0x2c>;
 903                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 904                 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
 905                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 906                        <&dmac1 0x17>, <&dmac1 0x18>;
 907                 dma-names = "tx", "rx", "tx", "rx";
 908                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 909                 num-cs = <1>;
 910                 #address-cells = <1>;
 911                 #size-cells = <0>;
 912                 status = "disabled";
 913         };
 914
 915         du: display@feb00000 {
 916                 compatible = "renesas,du-r8a7793";
 917                 reg = <0 0xfeb00000 0 0x40000>,
 918                       <0 0xfeb90000 0 0x1c>;
 919                 reg-names = "du", "lvds.0";
 920                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 921                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 922                 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
 923                          <&mstp7_clks R8A7793_CLK_DU1>,
 924                          <&mstp7_clks R8A7793_CLK_LVDS0>;
 925                 clock-names = "du.0", "du.1", "lvds.0";
 926                 status = "disabled";
 927
 928                 ports {
 929                         #address-cells = <1>;
 930                         #size-cells = <0>;
 931
 932                         port@0 {
 933                                 reg = <0>;
 934                                 du_out_rgb: endpoint {
 935                                 };
 936                         };
 937                         port@1 {
 938                                 reg = <1>;
 939                                 du_out_lvds0: endpoint {
 940                                 };
 941                         };
 942                 };
 943         };
 944
 945         can0: can@e6e80000 {
 946                 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
 947                 reg = <0 0xe6e80000 0 0x1000>;
 948                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 949                 clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
 950                          <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
 951                 clock-names = "clkp1", "clkp2", "can_clk";
 952                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 953                 status = "disabled";
 954         };
 955
 956         can1: can@e6e88000 {
 957                 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
 958                 reg = <0 0xe6e88000 0 0x1000>;
 959                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 960                 clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
 961                          <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
 962                 clock-names = "clkp1", "clkp2", "can_clk";
 963                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 964                 status = "disabled";
 965         };
 966
 967         clocks {
 968                 #address-cells = <2>;
 969                 #size-cells = <2>;
 970                 ranges;
 971
 972                 /* External root clock */
 973                 extal_clk: extal {
 974                         compatible = "fixed-clock";
 975                         #clock-cells = <0>;
 976                         /* This value must be overridden by the board. */
 977                         clock-frequency = <0>;
 978                 };
 979
 980                 /*
 981                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 982                  * default. Boards that provide audio clocks should override them.
 983                  */
 984                 audio_clk_a: audio_clk_a {
 985                         compatible = "fixed-clock";
 986                         #clock-cells = <0>;
 987                         clock-frequency = <0>;
 988                 };
 989                 audio_clk_b: audio_clk_b {
 990                         compatible = "fixed-clock";
 991                         #clock-cells = <0>;
 992                         clock-frequency = <0>;
 993                 };
 994                 audio_clk_c: audio_clk_c {
 995                         compatible = "fixed-clock";
 996                         #clock-cells = <0>;
 997                         clock-frequency = <0>;
 998                 };
 999
1000                 /* External USB clock - can be overridden by the board */
1001                 usb_extal_clk: usb_extal {
1002                         compatible = "fixed-clock";
1003                         #clock-cells = <0>;
1004                         clock-frequency = <48000000>;
1005                 };
1006
1007                 /* External CAN clock */
1008                 can_clk: can {
1009                         compatible = "fixed-clock";
1010                         #clock-cells = <0>;
1011                         /* This value must be overridden by the board. */
1012                         clock-frequency = <0>;
1013                 };
1014
1015                 /* External SCIF clock */
1016                 scif_clk: scif {
1017                         compatible = "fixed-clock";
1018                         #clock-cells = <0>;
1019                         /* This value must be overridden by the board. */
1020                         clock-frequency = <0>;
1021                 };
1022
1023                 /* Special CPG clocks */
1024                 cpg_clocks: cpg_clocks@e6150000 {
1025                         compatible = "renesas,r8a7793-cpg-clocks",
1026                                      "renesas,rcar-gen2-cpg-clocks";
1027                         reg = <0 0xe6150000 0 0x1000>;
1028                         clocks = <&extal_clk &usb_extal_clk>;
1029                         #clock-cells = <1>;
1030                         clock-output-names = "main", "pll0", "pll1", "pll3",
1031                                              "lb", "qspi", "sdh", "sd0", "z",
1032                                              "rcan", "adsp";
1033                         #power-domain-cells = <0>;
1034                 };
1035
1036                 /* Variable factor clocks */
1037                 sd2_clk: sd2@e6150078 {
1038                         compatible = "renesas,r8a7793-div6-clock",
1039                                      "renesas,cpg-div6-clock";
1040                         reg = <0 0xe6150078 0 4>;
1041                         clocks = <&pll1_div2_clk>;
1042                         #clock-cells = <0>;
1043                 };
1044                 sd3_clk: sd3@e615026c {
1045                         compatible = "renesas,r8a7793-div6-clock",
1046                                      "renesas,cpg-div6-clock";
1047                         reg = <0 0xe615026c 0 4>;
1048                         clocks = <&pll1_div2_clk>;
1049                         #clock-cells = <0>;
1050                 };
1051                 mmc0_clk: mmc0@e6150240 {
1052                         compatible = "renesas,r8a7793-div6-clock",
1053                                      "renesas,cpg-div6-clock";
1054                         reg = <0 0xe6150240 0 4>;
1055                         clocks = <&pll1_div2_clk>;
1056                         #clock-cells = <0>;
1057                 };
1058
1059                 /* Fixed factor clocks */
1060                 pll1_div2_clk: pll1_div2 {
1061                         compatible = "fixed-factor-clock";
1062                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1063                         #clock-cells = <0>;
1064                         clock-div = <2>;
1065                         clock-mult = <1>;
1066                 };
1067                 zg_clk: zg {
1068                         compatible = "fixed-factor-clock";
1069                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1070                         #clock-cells = <0>;
1071                         clock-div = <5>;
1072                         clock-mult = <1>;
1073                 };
1074                 zx_clk: zx {
1075                         compatible = "fixed-factor-clock";
1076                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1077                         #clock-cells = <0>;
1078                         clock-div = <3>;
1079                         clock-mult = <1>;
1080                 };
1081                 zs_clk: zs {
1082                         compatible = "fixed-factor-clock";
1083                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1084                         #clock-cells = <0>;
1085                         clock-div = <6>;
1086                         clock-mult = <1>;
1087                 };
1088                 hp_clk: hp {
1089                         compatible = "fixed-factor-clock";
1090                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1091                         #clock-cells = <0>;
1092                         clock-div = <12>;
1093                         clock-mult = <1>;
1094                 };
1095                 p_clk: p {
1096                         compatible = "fixed-factor-clock";
1097                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1098                         #clock-cells = <0>;
1099                         clock-div = <24>;
1100                         clock-mult = <1>;
1101                 };
1102                 m2_clk: m2 {
1103                         compatible = "fixed-factor-clock";
1104                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1105                         #clock-cells = <0>;
1106                         clock-div = <8>;
1107                         clock-mult = <1>;
1108                 };
1109                 rclk_clk: rclk {
1110                         compatible = "fixed-factor-clock";
1111                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1112                         #clock-cells = <0>;
1113                         clock-div = <(48 * 1024)>;
1114                         clock-mult = <1>;
1115                 };
1116                 mp_clk: mp {
1117                         compatible = "fixed-factor-clock";
1118                         clocks = <&pll1_div2_clk>;
1119                         #clock-cells = <0>;
1120                         clock-div = <15>;
1121                         clock-mult = <1>;
1122                 };
1123                 cp_clk: cp {
1124                         compatible = "fixed-factor-clock";
1125                         clocks = <&extal_clk>;
1126                         #clock-cells = <0>;
1127                         clock-div = <2>;
1128                         clock-mult = <1>;
1129                 };
1130
1131                 /* Gate clocks */
1132                 mstp1_clks: mstp1_clks@e6150134 {
1133                         compatible = "renesas,r8a7793-mstp-clocks",
1134                                      "renesas,cpg-mstp-clocks";
1135                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1136                         clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1137                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
1138                                  <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1139                                  <&zs_clk>, <&zs_clk>, <&zs_clk>;
1140                         #clock-cells = <1>;
1141                         clock-indices = <
1142                                 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
1143                                 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
1144                                 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
1145                                 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
1146                                 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
1147                                 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
1148                                 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
1149                                 R8A7793_CLK_VSP1_S
1150                         >;
1151                         clock-output-names =
1152                                 "vcp0", "vpc0", "ssp_dev", "tmu1",
1153                                 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
1154                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
1155                                 "vsp1-du0", "vsps";
1156                 };
1157                 mstp2_clks: mstp2_clks@e6150138 {
1158                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1159                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1160                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1161                                  <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
1162                         #clock-cells = <1>;
1163                         clock-indices = <
1164                                 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
1165                                 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
1166                                 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
1167                         >;
1168                         clock-output-names =
1169                                 "scifa2", "scifa1", "scifa0", "scifb0",
1170                                 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
1171                 };
1172                 mstp3_clks: mstp3_clks@e615013c {
1173                         compatible = "renesas,r8a7793-mstp-clocks",
1174                                      "renesas,cpg-mstp-clocks";
1175                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1176                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
1177                                  <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
1178                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
1179                                  <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1180                         #clock-cells = <1>;
1181                         clock-indices = <
1182                                 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
1183                                 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
1184                                 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
1185                                 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
1186                                 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
1187                                 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
1188                         >;
1189                         clock-output-names =
1190                                 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1191                                 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1192                                 "usbdmac0", "usbdmac1";
1193                 };
1194                 mstp4_clks: mstp4_clks@e6150140 {
1195                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1196                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1197                         clocks = <&cp_clk>, <&zs_clk>;
1198                         #clock-cells = <1>;
1199                         clock-indices = <
1200                                 R8A7793_CLK_IRQC R8A7793_CLK_INTC_SYS
1201                         >;
1202                         clock-output-names = "irqc", "intc-sys";
1203                 };
1204                 mstp5_clks: mstp5_clks@e6150144 {
1205                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1206                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1207                         clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
1208                         #clock-cells = <1>;
1209                         clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
1210                                          R8A7793_CLK_THERMAL>;
1211                         clock-output-names = "audmac0", "audmac1", "thermal";
1212                 };
1213                 mstp7_clks: mstp7_clks@e615014c {
1214                         compatible = "renesas,r8a7793-mstp-clocks",
1215                                      "renesas,cpg-mstp-clocks";
1216                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1217                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>,
1218                                  <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1219                                  <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
1220                                  <&zx_clk>, <&zx_clk>;
1221                         #clock-cells = <1>;
1222                         clock-indices = <
1223                                 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
1224                                 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
1225                                 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
1226                                 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
1227                                 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
1228                                 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
1229                                 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
1230                         >;
1231                         clock-output-names =
1232                                 "ehci", "hsusb", "hscif2", "scif5", "scif4",
1233                                 "hscif1", "hscif0", "scif3", "scif2",
1234                                 "scif1", "scif0", "du1", "du0", "lvds0";
1235                 };
1236                 mstp8_clks: mstp8_clks@e6150990 {
1237                         compatible = "renesas,r8a7793-mstp-clocks",
1238                                      "renesas,cpg-mstp-clocks";
1239                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1240                         clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1241                                  <&p_clk>, <&zs_clk>, <&zs_clk>;
1242                         #clock-cells = <1>;
1243                         clock-indices = <
1244                                 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
1245                                 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
1246                                 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
1247                                 R8A7793_CLK_SATA0
1248                         >;
1249                         clock-output-names =
1250                                 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
1251                                 "sata1", "sata0";
1252                 };
1253                 mstp9_clks: mstp9_clks@e6150994 {
1254                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1255                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1256                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1257                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1258                                  <&p_clk>, <&p_clk>,
1259                                  <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
1260                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1261                                  <&hp_clk>, <&hp_clk>;
1262                         #clock-cells = <1>;
1263                         clock-indices = <
1264                                 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
1265                                 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
1266                                 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
1267                                 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
1268                                 R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
1269                                 R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
1270                                 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
1271                                 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
1272                                 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
1273                         >;
1274                         clock-output-names =
1275                                 "gpio7", "gpio6", "gpio5", "gpio4",
1276                                 "gpio3", "gpio2", "gpio1", "gpio0",
1277                                 "rcan1", "rcan0", "qspi_mod", "i2c5",
1278                                 "i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
1279                                 "i2c0";
1280                 };
1281                 mstp10_clks: mstp10_clks@e6150998 {
1282                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1283                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1284                         clocks = <&p_clk>,
1285                                 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1286                                 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1287                                 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1288                                 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1289                                 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1290                                 <&p_clk>,
1291                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1292                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1293                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1294                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1295                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1296                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1297                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
1298
1299                         #clock-cells = <1>;
1300                         clock-indices = <
1301                                 R8A7793_CLK_SSI_ALL
1302                                 R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
1303                                 R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
1304                                 R8A7793_CLK_SCU_ALL
1305                                 R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
1306                                 R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
1307                                 R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
1308                                 R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
1309                         >;
1310                         clock-output-names =
1311                                 "ssi-all",
1312                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1313                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1314                                 "scu-all",
1315                                 "scu-dvc1", "scu-dvc0",
1316                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1317                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1318                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1319                 };
1320                 mstp11_clks: mstp11_clks@e615099c {
1321                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1322                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1323                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1324                         #clock-cells = <1>;
1325                         clock-indices = <
1326                                 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
1327                         >;
1328                         clock-output-names = "scifa3", "scifa4", "scifa5";
1329                 };
1330         };
1331
1332         rst: reset-controller@e6160000 {
1333                 compatible = "renesas,r8a7793-rst";
1334                 reg = <0 0xe6160000 0 0x0100>;
1335         };
1336
1337         prr: chipid@ff000044 {
1338                 compatible = "renesas,prr";
1339                 reg = <0 0xff000044 0 4>;
1340         };
1341
1342         sysc: system-controller@e6180000 {
1343                 compatible = "renesas,r8a7793-sysc";
1344                 reg = <0 0xe6180000 0 0x0200>;
1345                 #power-domain-cells = <1>;
1346         };
1347
1348         ipmmu_sy0: mmu@e6280000 {
1349                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1350                 reg = <0 0xe6280000 0 0x1000>;
1351                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1352                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1353                 #iommu-cells = <1>;
1354                 status = "disabled";
1355         };
1356
1357         ipmmu_sy1: mmu@e6290000 {
1358                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1359                 reg = <0 0xe6290000 0 0x1000>;
1360                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1361                 #iommu-cells = <1>;
1362                 status = "disabled";
1363         };
1364
1365         ipmmu_ds: mmu@e6740000 {
1366                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1367                 reg = <0 0xe6740000 0 0x1000>;
1368                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1369                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1370                 #iommu-cells = <1>;
1371                 status = "disabled";
1372         };
1373
1374         ipmmu_mp: mmu@ec680000 {
1375                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1376                 reg = <0 0xec680000 0 0x1000>;
1377                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1378                 #iommu-cells = <1>;
1379                 status = "disabled";
1380         };
1381
1382         ipmmu_mx: mmu@fe951000 {
1383                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1384                 reg = <0 0xfe951000 0 0x1000>;
1385                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1386                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1387                 #iommu-cells = <1>;
1388                 status = "disabled";
1389         };
1390
1391         ipmmu_rt: mmu@ffc80000 {
1392                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1393                 reg = <0 0xffc80000 0 0x1000>;
1394                 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1395                 #iommu-cells = <1>;
1396                 status = "disabled";
1397         };
1398
1399         ipmmu_gp: mmu@e62a0000 {
1400                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1401                 reg = <0 0xe62a0000 0 0x1000>;
1402                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1403                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1404                 #iommu-cells = <1>;
1405                 status = "disabled";
1406         };
1407
1408         rcar_sound: sound@ec500000 {
1409                 /*
1410                  * #sound-dai-cells is required
1411                  *
1412                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1413                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1414                  */
1415                 compatible =  "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
1416                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1417                         <0 0xec5a0000 0 0x100>,  /* ADG */
1418                         <0 0xec540000 0 0x1000>, /* SSIU */
1419                         <0 0xec541000 0 0x280>,  /* SSI */
1420                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1421                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1422
1423                 clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1424                         <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
1425                         <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
1426                         <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
1427                         <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
1428                         <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
1429                         <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
1430                         <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
1431                         <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
1432                         <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
1433                         <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
1434                         <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
1435                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1436                 clock-names = "ssi-all",
1437                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1438                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1439                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1440                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1441                                 "dvc.0", "dvc.1",
1442                                 "clk_a", "clk_b", "clk_c", "clk_i";
1443                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1444
1445                 status = "disabled";
1446
1447                 rcar_sound,dvc {
1448                         dvc0: dvc-0 {
1449                                 dmas = <&audma1 0xbc>;
1450                                 dma-names = "tx";
1451                         };
1452                         dvc1: dvc-1 {
1453                                 dmas = <&audma1 0xbe>;
1454                                 dma-names = "tx";
1455                         };
1456                 };
1457
1458                 rcar_sound,src {
1459                         src0: src-0 {
1460                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1461                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1462                                 dma-names = "rx", "tx";
1463                         };
1464                         src1: src-1 {
1465                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1466                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1467                                 dma-names = "rx", "tx";
1468                         };
1469                         src2: src-2 {
1470                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1471                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1472                                 dma-names = "rx", "tx";
1473                         };
1474                         src3: src-3 {
1475                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1476                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1477                                 dma-names = "rx", "tx";
1478                         };
1479                         src4: src-4 {
1480                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1481                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1482                                 dma-names = "rx", "tx";
1483                         };
1484                         src5: src-5 {
1485                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1486                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1487                                 dma-names = "rx", "tx";
1488                         };
1489                         src6: src-6 {
1490                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1491                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1492                                 dma-names = "rx", "tx";
1493                         };
1494                         src7: src-7 {
1495                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1496                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1497                                 dma-names = "rx", "tx";
1498                         };
1499                         src8: src-8 {
1500                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1501                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1502                                 dma-names = "rx", "tx";
1503                         };
1504                         src9: src-9 {
1505                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1506                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1507                                 dma-names = "rx", "tx";
1508                         };
1509                 };
1510
1511                 rcar_sound,ssi {
1512                         ssi0: ssi-0 {
1513                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1514                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1515                                 dma-names = "rx", "tx", "rxu", "txu";
1516                         };
1517                         ssi1: ssi-1 {
1518                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1519                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1520                                 dma-names = "rx", "tx", "rxu", "txu";
1521                         };
1522                         ssi2: ssi-2 {
1523                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1524                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1525                                 dma-names = "rx", "tx", "rxu", "txu";
1526                         };
1527                         ssi3: ssi-3 {
1528                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1529                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1530                                 dma-names = "rx", "tx", "rxu", "txu";
1531                         };
1532                         ssi4: ssi-4 {
1533                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1534                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1535                                 dma-names = "rx", "tx", "rxu", "txu";
1536                         };
1537                         ssi5: ssi-5 {
1538                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1539                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1540                                 dma-names = "rx", "tx", "rxu", "txu";
1541                         };
1542                         ssi6: ssi-6 {
1543                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1544                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1545                                 dma-names = "rx", "tx", "rxu", "txu";
1546                         };
1547                         ssi7: ssi-7 {
1548                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1549                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1550                                 dma-names = "rx", "tx", "rxu", "txu";
1551                         };
1552                         ssi8: ssi-8 {
1553                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1554                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1555                                 dma-names = "rx", "tx", "rxu", "txu";
1556                         };
1557                         ssi9: ssi-9 {
1558                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1559                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1560                                 dma-names = "rx", "tx", "rxu", "txu";
1561                         };
1562                 };
1563         };
1564 };