2 * Device Tree Source for the r8a7792 SoC
4 * Copyright (C) 2016 Cogent Embedded Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/r8a7792-sysc.h>
17 compatible = "renesas,r8a7792";
39 /* External CAN clock */
41 compatible = "fixed-clock";
43 /* This value must be overridden by the board. */
44 clock-frequency = <0>;
50 enable-method = "renesas,apmu";
54 compatible = "arm,cortex-a15";
56 clock-frequency = <1000000000>;
57 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
58 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
59 next-level-cache = <&L2_CA15>;
64 compatible = "arm,cortex-a15";
66 clock-frequency = <1000000000>;
67 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
68 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
69 next-level-cache = <&L2_CA15>;
72 L2_CA15: cache-controller-0 {
76 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
80 /* External root clock */
82 compatible = "fixed-clock";
84 /* This value must be overridden by the board. */
85 clock-frequency = <0>;
89 compatible = "arm,cortex-a15-pmu";
90 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
91 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
92 interrupt-affinity = <&cpu0>, <&cpu1>;
95 /* External SCIF clock */
97 compatible = "fixed-clock";
99 /* This value must be overridden by the board. */
100 clock-frequency = <0>;
104 compatible = "simple-bus";
105 interrupt-parent = <&gic>;
107 #address-cells = <2>;
111 rwdt: watchdog@e6020000 {
112 compatible = "renesas,r8a7792-wdt",
113 "renesas,rcar-gen2-wdt";
114 reg = <0 0xe6020000 0 0x0c>;
115 clocks = <&cpg CPG_MOD 402>;
116 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
121 gpio0: gpio@e6050000 {
122 compatible = "renesas,gpio-r8a7792",
123 "renesas,rcar-gen2-gpio";
124 reg = <0 0xe6050000 0 0x50>;
125 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
128 gpio-ranges = <&pfc 0 0 29>;
129 #interrupt-cells = <2>;
130 interrupt-controller;
131 clocks = <&cpg CPG_MOD 912>;
132 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
136 gpio1: gpio@e6051000 {
137 compatible = "renesas,gpio-r8a7792",
138 "renesas,rcar-gen2-gpio";
139 reg = <0 0xe6051000 0 0x50>;
140 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
143 gpio-ranges = <&pfc 0 32 23>;
144 #interrupt-cells = <2>;
145 interrupt-controller;
146 clocks = <&cpg CPG_MOD 911>;
147 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
151 gpio2: gpio@e6052000 {
152 compatible = "renesas,gpio-r8a7792",
153 "renesas,rcar-gen2-gpio";
154 reg = <0 0xe6052000 0 0x50>;
155 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
158 gpio-ranges = <&pfc 0 64 32>;
159 #interrupt-cells = <2>;
160 interrupt-controller;
161 clocks = <&cpg CPG_MOD 910>;
162 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
166 gpio3: gpio@e6053000 {
167 compatible = "renesas,gpio-r8a7792",
168 "renesas,rcar-gen2-gpio";
169 reg = <0 0xe6053000 0 0x50>;
170 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
173 gpio-ranges = <&pfc 0 96 28>;
174 #interrupt-cells = <2>;
175 interrupt-controller;
176 clocks = <&cpg CPG_MOD 909>;
177 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
181 gpio4: gpio@e6054000 {
182 compatible = "renesas,gpio-r8a7792",
183 "renesas,rcar-gen2-gpio";
184 reg = <0 0xe6054000 0 0x50>;
185 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
188 gpio-ranges = <&pfc 0 128 17>;
189 #interrupt-cells = <2>;
190 interrupt-controller;
191 clocks = <&cpg CPG_MOD 908>;
192 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
196 gpio5: gpio@e6055000 {
197 compatible = "renesas,gpio-r8a7792",
198 "renesas,rcar-gen2-gpio";
199 reg = <0 0xe6055000 0 0x50>;
200 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
203 gpio-ranges = <&pfc 0 160 17>;
204 #interrupt-cells = <2>;
205 interrupt-controller;
206 clocks = <&cpg CPG_MOD 907>;
207 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
211 gpio6: gpio@e6055100 {
212 compatible = "renesas,gpio-r8a7792",
213 "renesas,rcar-gen2-gpio";
214 reg = <0 0xe6055100 0 0x50>;
215 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
218 gpio-ranges = <&pfc 0 192 17>;
219 #interrupt-cells = <2>;
220 interrupt-controller;
221 clocks = <&cpg CPG_MOD 905>;
222 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
226 gpio7: gpio@e6055200 {
227 compatible = "renesas,gpio-r8a7792",
228 "renesas,rcar-gen2-gpio";
229 reg = <0 0xe6055200 0 0x50>;
230 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
233 gpio-ranges = <&pfc 0 224 17>;
234 #interrupt-cells = <2>;
235 interrupt-controller;
236 clocks = <&cpg CPG_MOD 904>;
237 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
241 gpio8: gpio@e6055300 {
242 compatible = "renesas,gpio-r8a7792",
243 "renesas,rcar-gen2-gpio";
244 reg = <0 0xe6055300 0 0x50>;
245 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
248 gpio-ranges = <&pfc 0 256 17>;
249 #interrupt-cells = <2>;
250 interrupt-controller;
251 clocks = <&cpg CPG_MOD 921>;
252 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
256 gpio9: gpio@e6055400 {
257 compatible = "renesas,gpio-r8a7792",
258 "renesas,rcar-gen2-gpio";
259 reg = <0 0xe6055400 0 0x50>;
260 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
263 gpio-ranges = <&pfc 0 288 17>;
264 #interrupt-cells = <2>;
265 interrupt-controller;
266 clocks = <&cpg CPG_MOD 919>;
267 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
271 gpio10: gpio@e6055500 {
272 compatible = "renesas,gpio-r8a7792",
273 "renesas,rcar-gen2-gpio";
274 reg = <0 0xe6055500 0 0x50>;
275 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
278 gpio-ranges = <&pfc 0 320 32>;
279 #interrupt-cells = <2>;
280 interrupt-controller;
281 clocks = <&cpg CPG_MOD 914>;
282 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
286 gpio11: gpio@e6055600 {
287 compatible = "renesas,gpio-r8a7792",
288 "renesas,rcar-gen2-gpio";
289 reg = <0 0xe6055600 0 0x50>;
290 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
293 gpio-ranges = <&pfc 0 352 30>;
294 #interrupt-cells = <2>;
295 interrupt-controller;
296 clocks = <&cpg CPG_MOD 913>;
297 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
301 pfc: pin-controller@e6060000 {
302 compatible = "renesas,pfc-r8a7792";
303 reg = <0 0xe6060000 0 0x144>;
306 cpg: clock-controller@e6150000 {
307 compatible = "renesas,r8a7792-cpg-mssr";
308 reg = <0 0xe6150000 0 0x1000>;
309 clocks = <&extal_clk>;
310 clock-names = "extal";
312 #power-domain-cells = <0>;
317 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
318 reg = <0 0xe6152000 0 0x188>;
319 cpus = <&cpu0 &cpu1>;
322 rst: reset-controller@e6160000 {
323 compatible = "renesas,r8a7792-rst";
324 reg = <0 0xe6160000 0 0x0100>;
327 sysc: system-controller@e6180000 {
328 compatible = "renesas,r8a7792-sysc";
329 reg = <0 0xe6180000 0 0x0200>;
330 #power-domain-cells = <1>;
333 irqc: interrupt-controller@e61c0000 {
334 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
335 #interrupt-cells = <2>;
336 interrupt-controller;
337 reg = <0 0xe61c0000 0 0x200>;
338 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&cpg CPG_MOD 407>;
343 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
347 icram0: sram@e63a0000 {
348 compatible = "mmio-sram";
349 reg = <0 0xe63a0000 0 0x12000>;
352 icram1: sram@e63c0000 {
353 compatible = "mmio-sram";
354 reg = <0 0xe63c0000 0 0x1000>;
355 #address-cells = <1>;
357 ranges = <0 0 0xe63c0000 0x1000>;
360 compatible = "renesas,smp-sram";
365 /* I2C doesn't need pinmux */
367 compatible = "renesas,i2c-r8a7792",
368 "renesas,rcar-gen2-i2c";
369 reg = <0 0xe6508000 0 0x40>;
370 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&cpg CPG_MOD 931>;
372 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
374 i2c-scl-internal-delay-ns = <6>;
375 #address-cells = <1>;
381 compatible = "renesas,i2c-r8a7792",
382 "renesas,rcar-gen2-i2c";
383 reg = <0 0xe6518000 0 0x40>;
384 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&cpg CPG_MOD 930>;
386 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
388 i2c-scl-internal-delay-ns = <6>;
389 #address-cells = <1>;
395 compatible = "renesas,i2c-r8a7792",
396 "renesas,rcar-gen2-i2c";
397 reg = <0 0xe6530000 0 0x40>;
398 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&cpg CPG_MOD 929>;
400 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
402 i2c-scl-internal-delay-ns = <6>;
403 #address-cells = <1>;
409 compatible = "renesas,i2c-r8a7792",
410 "renesas,rcar-gen2-i2c";
411 reg = <0 0xe6540000 0 0x40>;
412 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&cpg CPG_MOD 928>;
414 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
416 i2c-scl-internal-delay-ns = <6>;
417 #address-cells = <1>;
423 compatible = "renesas,i2c-r8a7792",
424 "renesas,rcar-gen2-i2c";
425 reg = <0 0xe6520000 0 0x40>;
426 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&cpg CPG_MOD 927>;
428 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
430 i2c-scl-internal-delay-ns = <6>;
431 #address-cells = <1>;
437 compatible = "renesas,i2c-r8a7792",
438 "renesas,rcar-gen2-i2c";
439 reg = <0 0xe6528000 0 0x40>;
440 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&cpg CPG_MOD 925>;
442 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
444 i2c-scl-internal-delay-ns = <110>;
445 #address-cells = <1>;
450 dmac0: dma-controller@e6700000 {
451 compatible = "renesas,dmac-r8a7792",
453 reg = <0 0xe6700000 0 0x20000>;
454 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
455 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
456 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
457 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
458 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
459 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
460 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
461 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
462 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
463 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
464 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
465 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
466 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
467 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
468 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
469 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
470 interrupt-names = "error",
471 "ch0", "ch1", "ch2", "ch3",
472 "ch4", "ch5", "ch6", "ch7",
473 "ch8", "ch9", "ch10", "ch11",
474 "ch12", "ch13", "ch14";
475 clocks = <&cpg CPG_MOD 219>;
477 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
483 dmac1: dma-controller@e6720000 {
484 compatible = "renesas,dmac-r8a7792",
486 reg = <0 0xe6720000 0 0x20000>;
487 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
488 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
489 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
490 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
491 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
492 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
493 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
494 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
495 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
496 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
497 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
498 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
499 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
500 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
501 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
502 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
503 interrupt-names = "error",
504 "ch0", "ch1", "ch2", "ch3",
505 "ch4", "ch5", "ch6", "ch7",
506 "ch8", "ch9", "ch10", "ch11",
507 "ch12", "ch13", "ch14";
508 clocks = <&cpg CPG_MOD 218>;
510 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
516 avb: ethernet@e6800000 {
517 compatible = "renesas,etheravb-r8a7792",
518 "renesas,etheravb-rcar-gen2";
519 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
520 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&cpg CPG_MOD 812>;
522 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
524 #address-cells = <1>;
530 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
531 reg = <0 0xe6b10000 0 0x2c>;
532 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cpg CPG_MOD 917>;
534 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
535 <&dmac1 0x17>, <&dmac1 0x18>;
536 dma-names = "tx", "rx", "tx", "rx";
537 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
540 #address-cells = <1>;
545 scif0: serial@e6e60000 {
546 compatible = "renesas,scif-r8a7792",
547 "renesas,rcar-gen2-scif", "renesas,scif";
548 reg = <0 0xe6e60000 0 64>;
549 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&cpg CPG_MOD 721>,
551 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
552 clock-names = "fck", "brg_int", "scif_clk";
553 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
554 <&dmac1 0x29>, <&dmac1 0x2a>;
555 dma-names = "tx", "rx", "tx", "rx";
556 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
561 scif1: serial@e6e68000 {
562 compatible = "renesas,scif-r8a7792",
563 "renesas,rcar-gen2-scif", "renesas,scif";
564 reg = <0 0xe6e68000 0 64>;
565 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&cpg CPG_MOD 720>,
567 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
568 clock-names = "fck", "brg_int", "scif_clk";
569 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
570 <&dmac1 0x2d>, <&dmac1 0x2e>;
571 dma-names = "tx", "rx", "tx", "rx";
572 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
577 scif2: serial@e6e58000 {
578 compatible = "renesas,scif-r8a7792",
579 "renesas,rcar-gen2-scif", "renesas,scif";
580 reg = <0 0xe6e58000 0 64>;
581 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&cpg CPG_MOD 719>,
583 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
584 clock-names = "fck", "brg_int", "scif_clk";
585 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
586 <&dmac1 0x2b>, <&dmac1 0x2c>;
587 dma-names = "tx", "rx", "tx", "rx";
588 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
593 scif3: serial@e6ea8000 {
594 compatible = "renesas,scif-r8a7792",
595 "renesas,rcar-gen2-scif", "renesas,scif";
596 reg = <0 0xe6ea8000 0 64>;
597 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&cpg CPG_MOD 718>,
599 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
600 clock-names = "fck", "brg_int", "scif_clk";
601 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
602 <&dmac1 0x2f>, <&dmac1 0x30>;
603 dma-names = "tx", "rx", "tx", "rx";
604 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
609 hscif0: serial@e62c0000 {
610 compatible = "renesas,hscif-r8a7792",
611 "renesas,rcar-gen2-hscif", "renesas,hscif";
612 reg = <0 0xe62c0000 0 96>;
613 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&cpg CPG_MOD 717>,
615 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
616 clock-names = "fck", "brg_int", "scif_clk";
617 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
618 <&dmac1 0x39>, <&dmac1 0x3a>;
619 dma-names = "tx", "rx", "tx", "rx";
620 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
625 hscif1: serial@e62c8000 {
626 compatible = "renesas,hscif-r8a7792",
627 "renesas,rcar-gen2-hscif", "renesas,hscif";
628 reg = <0 0xe62c8000 0 96>;
629 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cpg CPG_MOD 716>,
631 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
632 clock-names = "fck", "brg_int", "scif_clk";
633 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
634 <&dmac1 0x4d>, <&dmac1 0x4e>;
635 dma-names = "tx", "rx", "tx", "rx";
636 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
641 msiof0: spi@e6e20000 {
642 compatible = "renesas,msiof-r8a7792",
643 "renesas,rcar-gen2-msiof";
644 reg = <0 0xe6e20000 0 0x0064>;
645 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&cpg CPG_MOD 000>;
647 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
648 <&dmac1 0x51>, <&dmac1 0x52>;
649 dma-names = "tx", "rx", "tx", "rx";
650 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
652 #address-cells = <1>;
657 msiof1: spi@e6e10000 {
658 compatible = "renesas,msiof-r8a7792",
659 "renesas,rcar-gen2-msiof";
660 reg = <0 0xe6e10000 0 0x0064>;
661 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&cpg CPG_MOD 208>;
663 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
664 <&dmac1 0x55>, <&dmac1 0x56>;
665 dma-names = "tx", "rx", "tx", "rx";
666 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
668 #address-cells = <1>;
674 compatible = "renesas,can-r8a7792",
675 "renesas,rcar-gen2-can";
676 reg = <0 0xe6e80000 0 0x1000>;
677 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&cpg CPG_MOD 916>,
679 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
680 clock-names = "clkp1", "clkp2", "can_clk";
681 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
687 compatible = "renesas,can-r8a7792",
688 "renesas,rcar-gen2-can";
689 reg = <0 0xe6e88000 0 0x1000>;
690 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cpg CPG_MOD 915>,
692 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
693 clock-names = "clkp1", "clkp2", "can_clk";
694 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
699 vin0: video@e6ef0000 {
700 compatible = "renesas,vin-r8a7792",
701 "renesas,rcar-gen2-vin";
702 reg = <0 0xe6ef0000 0 0x1000>;
703 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&cpg CPG_MOD 811>;
705 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
710 vin1: video@e6ef1000 {
711 compatible = "renesas,vin-r8a7792",
712 "renesas,rcar-gen2-vin";
713 reg = <0 0xe6ef1000 0 0x1000>;
714 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&cpg CPG_MOD 810>;
716 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
721 vin2: video@e6ef2000 {
722 compatible = "renesas,vin-r8a7792",
723 "renesas,rcar-gen2-vin";
724 reg = <0 0xe6ef2000 0 0x1000>;
725 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&cpg CPG_MOD 809>;
727 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
732 vin3: video@e6ef3000 {
733 compatible = "renesas,vin-r8a7792",
734 "renesas,rcar-gen2-vin";
735 reg = <0 0xe6ef3000 0 0x1000>;
736 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 808>;
738 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
743 vin4: video@e6ef4000 {
744 compatible = "renesas,vin-r8a7792",
745 "renesas,rcar-gen2-vin";
746 reg = <0 0xe6ef4000 0 0x1000>;
747 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&cpg CPG_MOD 805>;
749 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
754 vin5: video@e6ef5000 {
755 compatible = "renesas,vin-r8a7792",
756 "renesas,rcar-gen2-vin";
757 reg = <0 0xe6ef5000 0 0x1000>;
758 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&cpg CPG_MOD 804>;
760 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
766 compatible = "renesas,sdhi-r8a7792",
767 "renesas,rcar-gen2-sdhi";
768 reg = <0 0xee100000 0 0x328>;
769 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
770 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
771 <&dmac1 0xcd>, <&dmac1 0xce>;
772 dma-names = "tx", "rx", "tx", "rx";
773 clocks = <&cpg CPG_MOD 314>;
774 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
779 gic: interrupt-controller@f1001000 {
780 compatible = "arm,gic-400";
781 #interrupt-cells = <3>;
782 interrupt-controller;
783 reg = <0 0xf1001000 0 0x1000>,
784 <0 0xf1002000 0 0x2000>,
785 <0 0xf1004000 0 0x2000>,
786 <0 0xf1006000 0 0x2000>;
787 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
788 IRQ_TYPE_LEVEL_HIGH)>;
789 clocks = <&cpg CPG_MOD 408>;
791 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
796 compatible = "renesas,vsp1";
797 reg = <0 0xfe928000 0 0x8000>;
798 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&cpg CPG_MOD 131>;
800 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
805 compatible = "renesas,vsp1";
806 reg = <0 0xfe930000 0 0x8000>;
807 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&cpg CPG_MOD 128>;
809 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
814 compatible = "renesas,vsp1";
815 reg = <0 0xfe938000 0 0x8000>;
816 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&cpg CPG_MOD 127>;
818 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
822 jpu: jpeg-codec@fe980000 {
823 compatible = "renesas,jpu-r8a7792",
824 "renesas,rcar-gen2-jpu";
825 reg = <0 0xfe980000 0 0x10300>;
826 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&cpg CPG_MOD 106>;
828 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
832 du: display@feb00000 {
833 compatible = "renesas,du-r8a7792";
834 reg = <0 0xfeb00000 0 0x40000>;
836 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&cpg CPG_MOD 724>,
840 clock-names = "du.0", "du.1";
844 #address-cells = <1>;
849 du_out_rgb0: endpoint {
854 du_out_rgb1: endpoint {
860 prr: chipid@ff000044 {
861 compatible = "renesas,prr";
862 reg = <0 0xff000044 0 4>;
867 compatible = "arm,armv7-timer";
868 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
869 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
870 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
871 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;