3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include "skeleton.dtsi"
10 model = "Qualcomm MSM8974";
11 compatible = "qcom,msm8974";
12 interrupt-parent = <&intc>;
20 reg = <0x08000000 0x5100000>;
25 reg = <0x0d100000 0x100000>;
30 reg = <0x0d200000 0xa00000>;
34 adsp_region: adsp@0dc00000 {
35 reg = <0x0dc00000 0x1900000>;
40 reg = <0x0f500000 0x500000>;
44 smem_region: smem@fa00000 {
45 reg = <0xfa00000 0x200000>;
50 reg = <0x0fc00000 0x160000>;
55 reg = <0x0fd60000 0x20000>;
60 reg = <0x0fd80000 0x180000>;
68 interrupts = <1 9 0xf04>;
71 compatible = "qcom,krait";
72 enable-method = "qcom,kpss-acc-v2";
75 next-level-cache = <&L2>;
78 cpu-idle-states = <&CPU_SPC>;
82 compatible = "qcom,krait";
83 enable-method = "qcom,kpss-acc-v2";
86 next-level-cache = <&L2>;
89 cpu-idle-states = <&CPU_SPC>;
93 compatible = "qcom,krait";
94 enable-method = "qcom,kpss-acc-v2";
97 next-level-cache = <&L2>;
100 cpu-idle-states = <&CPU_SPC>;
104 compatible = "qcom,krait";
105 enable-method = "qcom,kpss-acc-v2";
108 next-level-cache = <&L2>;
111 cpu-idle-states = <&CPU_SPC>;
115 compatible = "cache";
117 qcom,saw = <&saw_l2>;
122 compatible = "qcom,idle-state-spc",
124 entry-latency-us = <150>;
125 exit-latency-us = <200>;
126 min-residency-us = <2000>;
133 polling-delay-passive = <250>;
134 polling-delay = <1000>;
136 thermal-sensors = <&tsens 5>;
140 temperature = <75000>;
145 temperature = <110000>;
153 polling-delay-passive = <250>;
154 polling-delay = <1000>;
156 thermal-sensors = <&tsens 6>;
160 temperature = <75000>;
165 temperature = <110000>;
173 polling-delay-passive = <250>;
174 polling-delay = <1000>;
176 thermal-sensors = <&tsens 7>;
180 temperature = <75000>;
185 temperature = <110000>;
193 polling-delay-passive = <250>;
194 polling-delay = <1000>;
196 thermal-sensors = <&tsens 8>;
200 temperature = <75000>;
205 temperature = <110000>;
214 compatible = "qcom,krait-pmu";
215 interrupts = <1 7 0xf04>;
220 compatible = "fixed-clock";
222 clock-frequency = <19200000>;
225 sleep_clk: sleep_clk {
226 compatible = "fixed-clock";
228 clock-frequency = <32768>;
233 compatible = "arm,armv7-timer";
234 interrupts = <1 2 0xf08>,
238 clock-frequency = <19200000>;
242 compatible = "qcom,msm8974-adsp-pil";
244 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
245 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
246 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
247 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
248 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
249 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
251 cx-supply = <&pm8841_s2>;
253 clocks = <&xo_board>;
256 memory-region = <&adsp_region>;
258 qcom,smem-states = <&adsp_smp2p_out 0>;
259 qcom,smem-state-names = "stop";
263 compatible = "qcom,smem";
265 memory-region = <&smem_region>;
266 qcom,rpm-msg-ram = <&rpm_msg_ram>;
268 hwlocks = <&tcsr_mutex 3>;
272 compatible = "qcom,smp2p";
273 qcom,smem = <443>, <429>;
275 interrupt-parent = <&intc>;
276 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
278 qcom,ipc = <&apcs 8 10>;
280 qcom,local-pid = <0>;
281 qcom,remote-pid = <2>;
283 adsp_smp2p_out: master-kernel {
284 qcom,entry-name = "master-kernel";
285 #qcom,smem-state-cells = <1>;
288 adsp_smp2p_in: slave-kernel {
289 qcom,entry-name = "slave-kernel";
291 interrupt-controller;
292 #interrupt-cells = <2>;
297 compatible = "qcom,smp2p";
298 qcom,smem = <435>, <428>;
300 interrupt-parent = <&intc>;
301 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
303 qcom,ipc = <&apcs 8 14>;
305 qcom,local-pid = <0>;
306 qcom,remote-pid = <1>;
308 modem_smp2p_out: master-kernel {
309 qcom,entry-name = "master-kernel";
310 #qcom,smem-state-cells = <1>;
313 modem_smp2p_in: slave-kernel {
314 qcom,entry-name = "slave-kernel";
316 interrupt-controller;
317 #interrupt-cells = <2>;
322 compatible = "qcom,smp2p";
323 qcom,smem = <451>, <431>;
325 interrupt-parent = <&intc>;
326 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
328 qcom,ipc = <&apcs 8 18>;
330 qcom,local-pid = <0>;
331 qcom,remote-pid = <4>;
333 wcnss_smp2p_out: master-kernel {
334 qcom,entry-name = "master-kernel";
336 #qcom,smem-state-cells = <1>;
339 wcnss_smp2p_in: slave-kernel {
340 qcom,entry-name = "slave-kernel";
342 interrupt-controller;
343 #interrupt-cells = <2>;
348 compatible = "qcom,smsm";
350 #address-cells = <1>;
353 qcom,ipc-1 = <&apcs 8 13>;
354 qcom,ipc-2 = <&apcs 8 9>;
355 qcom,ipc-3 = <&apcs 8 19>;
360 #qcom,smem-state-cells = <1>;
363 modem_smsm: modem@1 {
365 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
373 interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
379 wcnss_smsm: wcnss@7 {
381 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
383 interrupt-controller;
384 #interrupt-cells = <2>;
390 compatible = "qcom,scm";
391 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
392 clock-names = "core", "bus", "iface";
397 #address-cells = <1>;
400 compatible = "simple-bus";
402 intc: interrupt-controller@f9000000 {
403 compatible = "qcom,msm-qgic2";
404 interrupt-controller;
405 #interrupt-cells = <3>;
406 reg = <0xf9000000 0x1000>,
410 apcs: syscon@f9011000 {
411 compatible = "syscon";
412 reg = <0xf9011000 0x1000>;
415 qfprom: qfprom@fc4bc000 {
416 #address-cells = <1>;
418 compatible = "qcom,qfprom";
419 reg = <0xfc4bc000 0x1000>;
420 tsens_calib: calib@d0 {
423 tsens_backup: backup@440 {
428 tsens: thermal-sensor@fc4a8000 {
429 compatible = "qcom,msm8974-tsens";
430 reg = <0xfc4a8000 0x2000>;
431 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
432 nvmem-cell-names = "calib", "calib_backup";
433 #thermal-sensor-cells = <1>;
437 #address-cells = <1>;
440 compatible = "arm,armv7-timer-mem";
441 reg = <0xf9020000 0x1000>;
442 clock-frequency = <19200000>;
446 interrupts = <0 8 0x4>,
448 reg = <0xf9021000 0x1000>,
454 interrupts = <0 9 0x4>;
455 reg = <0xf9023000 0x1000>;
461 interrupts = <0 10 0x4>;
462 reg = <0xf9024000 0x1000>;
468 interrupts = <0 11 0x4>;
469 reg = <0xf9025000 0x1000>;
475 interrupts = <0 12 0x4>;
476 reg = <0xf9026000 0x1000>;
482 interrupts = <0 13 0x4>;
483 reg = <0xf9027000 0x1000>;
489 interrupts = <0 14 0x4>;
490 reg = <0xf9028000 0x1000>;
495 saw0: power-controller@f9089000 {
496 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
497 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
500 saw1: power-controller@f9099000 {
501 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
502 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
505 saw2: power-controller@f90a9000 {
506 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
507 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
510 saw3: power-controller@f90b9000 {
511 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
512 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
515 saw_l2: power-controller@f9012000 {
516 compatible = "qcom,saw2";
517 reg = <0xf9012000 0x1000>;
521 acc0: clock-controller@f9088000 {
522 compatible = "qcom,kpss-acc-v2";
523 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
526 acc1: clock-controller@f9098000 {
527 compatible = "qcom,kpss-acc-v2";
528 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
531 acc2: clock-controller@f90a8000 {
532 compatible = "qcom,kpss-acc-v2";
533 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
536 acc3: clock-controller@f90b8000 {
537 compatible = "qcom,kpss-acc-v2";
538 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
542 compatible = "qcom,pshold";
543 reg = <0xfc4ab000 0x4>;
546 gcc: clock-controller@fc400000 {
547 compatible = "qcom,gcc-msm8974";
550 #power-domain-cells = <1>;
551 reg = <0xfc400000 0x4000>;
554 tcsr_mutex_block: syscon@fd484000 {
555 compatible = "syscon";
556 reg = <0xfd484000 0x2000>;
559 mmcc: clock-controller@fd8c0000 {
560 compatible = "qcom,mmcc-msm8974";
563 #power-domain-cells = <1>;
564 reg = <0xfd8c0000 0x6000>;
567 tcsr_mutex: tcsr-mutex {
568 compatible = "qcom,tcsr-mutex";
569 syscon = <&tcsr_mutex_block 0 0x80>;
574 rpm_msg_ram: memory@fc428000 {
575 compatible = "qcom,rpm-msg-ram";
576 reg = <0xfc428000 0x4000>;
579 blsp1_uart1: serial@f991d000 {
580 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
581 reg = <0xf991d000 0x1000>;
582 interrupts = <0 107 0x0>;
583 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
584 clock-names = "core", "iface";
588 blsp1_uart2: serial@f991e000 {
589 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
590 reg = <0xf991e000 0x1000>;
591 interrupts = <0 108 0x0>;
592 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
593 clock-names = "core", "iface";
598 compatible = "qcom,sdhci-msm-v4";
599 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
600 reg-names = "hc_mem", "core_mem";
601 interrupts = <0 123 0>, <0 138 0>;
602 interrupt-names = "hc_irq", "pwr_irq";
603 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
604 <&gcc GCC_SDCC1_AHB_CLK>,
606 clock-names = "core", "iface", "xo";
611 compatible = "qcom,sdhci-msm-v4";
612 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
613 reg-names = "hc_mem", "core_mem";
614 interrupts = <0 125 0>, <0 221 0>;
615 interrupt-names = "hc_irq", "pwr_irq";
616 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
617 <&gcc GCC_SDCC2_AHB_CLK>,
619 clock-names = "core", "iface", "xo";
624 compatible = "qcom,prng";
625 reg = <0xf9bff000 0x200>;
626 clocks = <&gcc GCC_PRNG_AHB_CLK>;
627 clock-names = "core";
630 msmgpio: pinctrl@fd510000 {
631 compatible = "qcom,msm8974-pinctrl";
632 reg = <0xfd510000 0x4000>;
635 interrupt-controller;
636 #interrupt-cells = <2>;
637 interrupts = <0 208 0>;
642 compatible = "qcom,i2c-qup-v2.1.1";
643 reg = <0xf9924000 0x1000>;
644 interrupts = <0 96 IRQ_TYPE_NONE>;
645 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
646 clock-names = "core", "iface";
647 #address-cells = <1>;
651 blsp_i2c8: i2c@f9964000 {
653 compatible = "qcom,i2c-qup-v2.1.1";
654 reg = <0xf9964000 0x1000>;
655 interrupts = <0 102 IRQ_TYPE_NONE>;
656 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
657 clock-names = "core", "iface";
658 #address-cells = <1>;
662 blsp_i2c11: i2c@f9967000 {
664 compatible = "qcom,i2c-qup-v2.1.1";
665 reg = <0xf9967000 0x1000>;
666 interrupts = <0 105 IRQ_TYPE_NONE>;
667 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
668 clock-names = "core", "iface";
669 #address-cells = <1>;
671 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
672 dma-names = "tx", "rx";
675 spmi_bus: spmi@fc4cf000 {
676 compatible = "qcom,spmi-pmic-arb";
677 reg-names = "core", "intr", "cnfg";
678 reg = <0xfc4cf000 0x1000>,
681 interrupt-names = "periph_irq";
682 interrupts = <0 190 0>;
685 #address-cells = <2>;
687 interrupt-controller;
688 #interrupt-cells = <4>;
691 blsp2_dma: dma-controller@f9944000 {
692 compatible = "qcom,bam-v1.4.0";
693 reg = <0xf9944000 0x19000>;
694 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
696 clock-names = "bam_clk";
702 compatible = "arm,coresight-tmc", "arm,primecell";
703 reg = <0xfc322000 0x1000>;
705 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
706 clock-names = "apb_pclk", "atclk";
711 remote-endpoint = <&replicator_out0>;
717 compatible = "arm,coresight-tpiu", "arm,primecell";
718 reg = <0xfc318000 0x1000>;
720 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
721 clock-names = "apb_pclk", "atclk";
726 remote-endpoint = <&replicator_out1>;
731 replicator@fc31c000 {
732 compatible = "qcom,coresight-replicator1x", "arm,primecell";
733 reg = <0xfc31c000 0x1000>;
735 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
736 clock-names = "apb_pclk", "atclk";
739 #address-cells = <1>;
744 replicator_out0: endpoint {
745 remote-endpoint = <&etr_in>;
750 replicator_out1: endpoint {
751 remote-endpoint = <&tpiu_in>;
756 replicator_in: endpoint {
758 remote-endpoint = <&etf_out>;
765 compatible = "arm,coresight-tmc", "arm,primecell";
766 reg = <0xfc307000 0x1000>;
768 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
769 clock-names = "apb_pclk", "atclk";
772 #address-cells = <1>;
778 remote-endpoint = <&replicator_in>;
785 remote-endpoint = <&merger_out>;
792 compatible = "arm,coresight-funnel", "arm,primecell";
793 reg = <0xfc31b000 0x1000>;
795 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
796 clock-names = "apb_pclk", "atclk";
799 #address-cells = <1>;
803 * Not described input ports:
804 * 0 - connected trought funnel to Audio, Modem and
805 * Resource and Power Manager CPU's
806 * 2...7 - not-connected
810 merger_in1: endpoint {
812 remote-endpoint = <&funnel1_out>;
817 merger_out: endpoint {
818 remote-endpoint = <&etf_in>;
825 compatible = "arm,coresight-funnel", "arm,primecell";
826 reg = <0xfc31a000 0x1000>;
828 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
829 clock-names = "apb_pclk", "atclk";
832 #address-cells = <1>;
836 * Not described input ports:
838 * 1 - connected trought funnel to Multimedia CPU
839 * 2 - connected to Wireless CPU
843 * 7 - connected to STM
847 funnel1_in5: endpoint {
849 remote-endpoint = <&kpss_out>;
854 funnel1_out: endpoint {
855 remote-endpoint = <&merger_in1>;
861 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
862 compatible = "arm,coresight-funnel", "arm,primecell";
863 reg = <0xfc345000 0x1000>;
865 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
866 clock-names = "apb_pclk", "atclk";
869 #address-cells = <1>;
876 remote-endpoint = <&etm0_out>;
883 remote-endpoint = <&etm1_out>;
890 remote-endpoint = <&etm2_out>;
897 remote-endpoint = <&etm3_out>;
903 remote-endpoint = <&funnel1_in5>;
910 compatible = "arm,coresight-etm4x", "arm,primecell";
911 reg = <0xfc33c000 0x1000>;
913 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
914 clock-names = "apb_pclk", "atclk";
920 remote-endpoint = <&kpss_in0>;
926 compatible = "arm,coresight-etm4x", "arm,primecell";
927 reg = <0xfc33d000 0x1000>;
929 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
930 clock-names = "apb_pclk", "atclk";
936 remote-endpoint = <&kpss_in1>;
942 compatible = "arm,coresight-etm4x", "arm,primecell";
943 reg = <0xfc33e000 0x1000>;
945 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
946 clock-names = "apb_pclk", "atclk";
952 remote-endpoint = <&kpss_in2>;
958 compatible = "arm,coresight-etm4x", "arm,primecell";
959 reg = <0xfc33f000 0x1000>;
961 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
962 clock-names = "apb_pclk", "atclk";
968 remote-endpoint = <&kpss_in3>;
975 compatible = "qcom,smd";
978 interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
980 qcom,ipc = <&apcs 8 8>;
985 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
987 qcom,ipc = <&apcs 8 12>;
992 interrupts = <0 168 1>;
993 qcom,ipc = <&apcs 8 0>;
994 qcom,smd-edge = <15>;
997 compatible = "qcom,rpm-msm8974";
998 qcom,smd-channels = "rpm_requests";
1000 rpmcc: clock-controller {
1001 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1006 compatible = "qcom,rpm-pm8841-regulators";
1019 compatible = "qcom,rpm-pm8941-regulators";
1051 pm8941_lvs1: lvs1 {};
1052 pm8941_lvs2: lvs2 {};
1053 pm8941_lvs3: lvs3 {};
1055 pm8941_5vs1: 5vs1 {};
1056 pm8941_5vs2: 5vs2 {};
1062 vreg_boost: vreg-boost {
1063 compatible = "regulator-fixed";
1065 regulator-name = "vreg-boost";
1066 regulator-min-microvolt = <3150000>;
1067 regulator-max-microvolt = <3150000>;
1069 regulator-always-on;
1072 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1075 pinctrl-names = "default";
1076 pinctrl-0 = <&boost_bypass_n_pin>;
1078 vreg_vph_pwr: vreg-vph-pwr {
1079 compatible = "regulator-fixed";
1080 regulator-name = "vph-pwr";
1082 regulator-min-microvolt = <3600000>;
1083 regulator-max-microvolt = <3600000>;
1085 regulator-always-on;