arch/arm/boot/dts/qcom-msm8660.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         model = "Qualcomm MSM8660";
  13         compatible = "qcom,msm8660";
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         compatible = "qcom,scorpion";
  22                         enable-method = "qcom,gcc-msm8660";
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         next-level-cache = <&L2>;
  26                 };
  27
  28                 cpu@1 {
  29                         compatible = "qcom,scorpion";
  30                         enable-method = "qcom,gcc-msm8660";
  31                         device_type = "cpu";
  32                         reg = <1>;
  33                         next-level-cache = <&L2>;
  34                 };
  35
  36                 L2: l2-cache {
  37                         compatible = "cache";
  38                         cache-level = <2>;
  39                 };
  40         };
  41
  42         memory {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0>;
  45         };
  46
  47         cpu-pmu {
  48                 compatible = "qcom,scorpion-mp-pmu";
  49                 interrupts = <1 9 0x304>;
  50         };
  51
  52         clocks {
  53                 cxo_board {
  54                         compatible = "fixed-clock";
  55                         #clock-cells = <0>;
  56                         clock-frequency = <19200000>;
  57                 };
  58
  59                 pxo_board {
  60                         compatible = "fixed-clock";
  61                         #clock-cells = <0>;
  62                         clock-frequency = <27000000>;
  63                 };
  64
  65                 sleep_clk {
  66                         compatible = "fixed-clock";
  67                         #clock-cells = <0>;
  68                         clock-frequency = <32768>;
  69                 };
  70         };
  71
  72         /*
  73          * These channels from the ADC are simply hardware monitors.
  74          * That is why the ADC is referred to as "HKADC" - HouseKeeping
  75          * ADC.
  76          */
  77         iio-hwmon {
  78                 compatible = "iio-hwmon";
  79                 io-channels = <&xoadc 0x00 0x01>, /* Battery */
  80                             <&xoadc 0x00 0x02>, /* DC in (charger) */
  81                             <&xoadc 0x00 0x04>, /* VPH the main system voltage */
  82                             <&xoadc 0x00 0x0b>, /* Die temperature */
  83                             <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
  84                             <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
  85                             <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
  86         };
  87
  88         soc: soc {
  89                 #address-cells = <1>;
  90                 #size-cells = <1>;
  91                 ranges;
  92                 compatible = "simple-bus";
  93
  94                 intc: interrupt-controller@2080000 {
  95                         compatible = "qcom,msm-8660-qgic";
  96                         interrupt-controller;
  97                         #interrupt-cells = <3>;
  98                         reg = < 0x02080000 0x1000 >,
  99                               < 0x02081000 0x1000 >;
 100                 };
 101
 102                 timer@2000000 {
 103                         compatible = "qcom,scss-timer", "qcom,msm-timer";
 104                         interrupts = <1 0 0x301>,
 105                                      <1 1 0x301>,
 106                                      <1 2 0x301>;
 107                         reg = <0x02000000 0x100>;
 108                         clock-frequency = <27000000>,
 109                                           <32768>;
 110                         cpu-offset = <0x40000>;
 111                 };
 112
 113                 tlmm: pinctrl@800000 {
 114                         compatible = "qcom,msm8660-pinctrl";
 115                         reg = <0x800000 0x4000>;
 116
 117                         gpio-controller;
 118                         #gpio-cells = <2>;
 119                         interrupts = <0 16 0x4>;
 120                         interrupt-controller;
 121                         #interrupt-cells = <2>;
 122
 123                 };
 124
 125                 gcc: clock-controller@900000 {
 126                         compatible = "qcom,gcc-msm8660";
 127                         #clock-cells = <1>;
 128                         #reset-cells = <1>;
 129                         reg = <0x900000 0x4000>;
 130                 };
 131
 132                 gsbi6: gsbi@16500000 {
 133                         compatible = "qcom,gsbi-v1.0.0";
 134                         cell-index = <12>;
 135                         reg = <0x16500000 0x100>;
 136                         clocks = <&gcc GSBI6_H_CLK>;
 137                         clock-names = "iface";
 138                         #address-cells = <1>;
 139                         #size-cells = <1>;
 140                         ranges;
 141
 142                         syscon-tcsr = <&tcsr>;
 143
 144                         gsbi6_serial: serial@16540000 {
 145                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 146                                 reg = <0x16540000 0x1000>,
 147                                       <0x16500000 0x1000>;
 148                                 interrupts = <GIC_SPI 156 IRQ_TYPE_NONE>;
 149                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 150                                 clock-names = "core", "iface";
 151                                 status = "disabled";
 152                         };
 153
 154                         gsbi6_i2c: i2c@16580000 {
 155                                 compatible = "qcom,i2c-qup-v1.1.1";
 156                                 reg = <0x16580000 0x1000>;
 157                                 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
 158                                 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
 159                                 clock-names = "core", "iface";
 160                                 #address-cells = <1>;
 161                                 #size-cells = <0>;
 162                                 status = "disabled";
 163                         };
 164                 };
 165
 166                 gsbi7: gsbi@16600000 {
 167                         compatible = "qcom,gsbi-v1.0.0";
 168                         cell-index = <12>;
 169                         reg = <0x16600000 0x100>;
 170                         clocks = <&gcc GSBI7_H_CLK>;
 171                         clock-names = "iface";
 172                         #address-cells = <1>;
 173                         #size-cells = <1>;
 174                         ranges;
 175
 176                         syscon-tcsr = <&tcsr>;
 177
 178                         gsbi7_serial: serial@16640000 {
 179                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 180                                 reg = <0x16640000 0x1000>,
 181                                       <0x16600000 0x1000>;
 182                                 interrupts = <GIC_SPI 158 IRQ_TYPE_NONE>;
 183                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 184                                 clock-names = "core", "iface";
 185                                 status = "disabled";
 186                         };
 187
 188                         gsbi7_i2c: i2c@16680000 {
 189                                 compatible = "qcom,i2c-qup-v1.1.1";
 190                                 reg = <0x16680000 0x1000>;
 191                                 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
 192                                 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
 193                                 clock-names = "core", "iface";
 194                                 #address-cells = <1>;
 195                                 #size-cells = <0>;
 196                                 status = "disabled";
 197                         };
 198                 };
 199
 200                 gsbi8: gsbi@19800000 {
 201                         compatible = "qcom,gsbi-v1.0.0";
 202                         cell-index = <12>;
 203                         reg = <0x19800000 0x100>;
 204                         clocks = <&gcc GSBI8_H_CLK>;
 205                         clock-names = "iface";
 206                         #address-cells = <1>;
 207                         #size-cells = <1>;
 208                         ranges;
 209
 210                         syscon-tcsr = <&tcsr>;
 211
 212                         gsbi8_i2c: i2c@19880000 {
 213                                 compatible = "qcom,i2c-qup-v1.1.1";
 214                                 reg = <0x19880000 0x1000>;
 215                                 interrupts = <GIC_SPI 161 IRQ_TYPE_NONE>;
 216                                 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
 217                                 clock-names = "core", "iface";
 218                                 #address-cells = <1>;
 219                                 #size-cells = <0>;
 220                                 status = "disabled";
 221                         };
 222                 };
 223
 224                 gsbi12: gsbi@19c00000 {
 225                         compatible = "qcom,gsbi-v1.0.0";
 226                         cell-index = <12>;
 227                         reg = <0x19c00000 0x100>;
 228                         clocks = <&gcc GSBI12_H_CLK>;
 229                         clock-names = "iface";
 230                         #address-cells = <1>;
 231                         #size-cells = <1>;
 232                         ranges;
 233
 234                         syscon-tcsr = <&tcsr>;
 235
 236                         gsbi12_serial: serial@19c40000 {
 237                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 238                                 reg = <0x19c40000 0x1000>,
 239                                       <0x19c00000 0x1000>;
 240                                 interrupts = <0 195 IRQ_TYPE_NONE>;
 241                                 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
 242                                 clock-names = "core", "iface";
 243                                 status = "disabled";
 244                         };
 245
 246                         gsbi12_i2c: i2c@19c80000 {
 247                                 compatible = "qcom,i2c-qup-v1.1.1";
 248                                 reg = <0x19c80000 0x1000>;
 249                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 250                                 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
 251                                 clock-names = "core", "iface";
 252                                 #address-cells = <1>;
 253                                 #size-cells = <0>;
 254                                 status = "disabled";
 255                         };
 256                 };
 257
 258                 external-bus@1a100000 {
 259                         compatible = "qcom,msm8660-ebi2";
 260                         #address-cells = <2>;
 261                         #size-cells = <1>;
 262                         ranges = <0 0x0 0x1a800000 0x00800000>,
 263                                  <1 0x0 0x1b000000 0x00800000>,
 264                                  <2 0x0 0x1b800000 0x00800000>,
 265                                  <3 0x0 0x1d000000 0x08000000>,
 266                                  <4 0x0 0x1c800000 0x00800000>,
 267                                  <5 0x0 0x1c000000 0x00800000>;
 268                         reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
 269                         reg-names = "ebi2", "xmem";
 270                         clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
 271                         clock-names = "ebi2x", "ebi2";
 272                         status = "disabled";
 273                 };
 274
 275                 qcom,ssbi@500000 {
 276                         compatible = "qcom,ssbi";
 277                         reg = <0x500000 0x1000>;
 278                         qcom,controller-type = "pmic-arbiter";
 279
 280                         pm8058: pmic@0 {
 281                                 compatible = "qcom,pm8058";
 282                                 interrupt-parent = <&tlmm>;
 283                                 interrupts = <88 8>;
 284                                 #interrupt-cells = <2>;
 285                                 interrupt-controller;
 286                                 #address-cells = <1>;
 287                                 #size-cells = <0>;
 288
 289                                 pm8058_gpio: gpio@150 {
 290                                         compatible = "qcom,pm8058-gpio",
 291                                                      "qcom,ssbi-gpio";
 292                                         reg = <0x150>;
 293                                         interrupt-parent = <&pm8058>;
 294                                         interrupts = <192 IRQ_TYPE_NONE>,
 295                                                      <193 IRQ_TYPE_NONE>,
 296                                                      <194 IRQ_TYPE_NONE>,
 297                                                      <195 IRQ_TYPE_NONE>,
 298                                                      <196 IRQ_TYPE_NONE>,
 299                                                      <197 IRQ_TYPE_NONE>,
 300                                                      <198 IRQ_TYPE_NONE>,
 301                                                      <199 IRQ_TYPE_NONE>,
 302                                                      <200 IRQ_TYPE_NONE>,
 303                                                      <201 IRQ_TYPE_NONE>,
 304                                                      <202 IRQ_TYPE_NONE>,
 305                                                      <203 IRQ_TYPE_NONE>,
 306                                                      <204 IRQ_TYPE_NONE>,
 307                                                      <205 IRQ_TYPE_NONE>,
 308                                                      <206 IRQ_TYPE_NONE>,
 309                                                      <207 IRQ_TYPE_NONE>,
 310                                                      <208 IRQ_TYPE_NONE>,
 311                                                      <209 IRQ_TYPE_NONE>,
 312                                                      <210 IRQ_TYPE_NONE>,
 313                                                      <211 IRQ_TYPE_NONE>,
 314                                                      <212 IRQ_TYPE_NONE>,
 315                                                      <213 IRQ_TYPE_NONE>,
 316                                                      <214 IRQ_TYPE_NONE>,
 317                                                      <215 IRQ_TYPE_NONE>,
 318                                                      <216 IRQ_TYPE_NONE>,
 319                                                      <217 IRQ_TYPE_NONE>,
 320                                                      <218 IRQ_TYPE_NONE>,
 321                                                      <219 IRQ_TYPE_NONE>,
 322                                                      <220 IRQ_TYPE_NONE>,
 323                                                      <221 IRQ_TYPE_NONE>,
 324                                                      <222 IRQ_TYPE_NONE>,
 325                                                      <223 IRQ_TYPE_NONE>,
 326                                                      <224 IRQ_TYPE_NONE>,
 327                                                      <225 IRQ_TYPE_NONE>,
 328                                                      <226 IRQ_TYPE_NONE>,
 329                                                      <227 IRQ_TYPE_NONE>,
 330                                                      <228 IRQ_TYPE_NONE>,
 331                                                      <229 IRQ_TYPE_NONE>,
 332                                                      <230 IRQ_TYPE_NONE>,
 333                                                      <231 IRQ_TYPE_NONE>,
 334                                                      <232 IRQ_TYPE_NONE>,
 335                                                      <233 IRQ_TYPE_NONE>,
 336                                                      <234 IRQ_TYPE_NONE>,
 337                                                      <235 IRQ_TYPE_NONE>;
 338                                         gpio-controller;
 339                                         #gpio-cells = <2>;
 340
 341                                 };
 342
 343                                 pm8058_mpps: mpps@50 {
 344                                         compatible = "qcom,pm8058-mpp",
 345                                                      "qcom,ssbi-mpp";
 346                                         reg = <0x50>;
 347                                         gpio-controller;
 348                                         #gpio-cells = <2>;
 349                                         interrupt-parent = <&pm8058>;
 350                                         interrupts =
 351                                         <128 IRQ_TYPE_NONE>,
 352                                         <129 IRQ_TYPE_NONE>,
 353                                         <130 IRQ_TYPE_NONE>,
 354                                         <131 IRQ_TYPE_NONE>,
 355                                         <132 IRQ_TYPE_NONE>,
 356                                         <133 IRQ_TYPE_NONE>,
 357                                         <134 IRQ_TYPE_NONE>,
 358                                         <135 IRQ_TYPE_NONE>,
 359                                         <136 IRQ_TYPE_NONE>,
 360                                         <137 IRQ_TYPE_NONE>,
 361                                         <138 IRQ_TYPE_NONE>,
 362                                         <139 IRQ_TYPE_NONE>;
 363                                 };
 364
 365                                 pwrkey@1c {
 366                                         compatible = "qcom,pm8058-pwrkey";
 367                                         reg = <0x1c>;
 368                                         interrupt-parent = <&pm8058>;
 369                                         interrupts = <50 1>, <51 1>;
 370                                         debounce = <15625>;
 371                                         pull-up;
 372                                 };
 373
 374                                 keypad@148 {
 375                                         compatible = "qcom,pm8058-keypad";
 376                                         reg = <0x148>;
 377                                         interrupt-parent = <&pm8058>;
 378                                         interrupts = <74 1>, <75 1>;
 379                                         debounce = <15>;
 380                                         scan-delay = <32>;
 381                                         row-hold = <91500>;
 382                                 };
 383
 384                                 xoadc: xoadc@197 {
 385                                         compatible = "qcom,pm8058-adc";
 386                                         reg = <0x197>;
 387                                         interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
 388                                         #address-cells = <2>;
 389                                         #size-cells = <0>;
 390                                         #io-channel-cells = <2>;
 391
 392                                         vcoin: adc-channel@0 {
 393                                                 reg = <0x00 0x00>;
 394                                         };
 395                                         vbat: adc-channel@1 {
 396                                                 reg = <0x00 0x01>;
 397                                         };
 398                                         dcin: adc-channel@2 {
 399                                                 reg = <0x00 0x02>;
 400                                         };
 401                                         ichg: adc-channel@3 {
 402                                                 reg = <0x00 0x03>;
 403                                         };
 404                                         vph_pwr: adc-channel@4 {
 405                                                 reg = <0x00 0x04>;
 406                                         };
 407                                         usb_vbus: adc-channel@a {
 408                                                 reg = <0x00 0x0a>;
 409                                         };
 410                                         die_temp: adc-channel@b {
 411                                                 reg = <0x00 0x0b>;
 412                                         };
 413                                         ref_625mv: adc-channel@c {
 414                                                 reg = <0x00 0x0c>;
 415                                         };
 416                                         ref_1250mv: adc-channel@d {
 417                                                 reg = <0x00 0x0d>;
 418                                         };
 419                                         ref_325mv: adc-channel@e {
 420                                                 reg = <0x00 0x0e>;
 421                                         };
 422                                         ref_muxoff: adc-channel@f {
 423                                                 reg = <0x00 0x0f>;
 424                                         };
 425                                 };
 426
 427                                 rtc@1e8 {
 428                                         compatible = "qcom,pm8058-rtc";
 429                                         reg = <0x1e8>;
 430                                         interrupt-parent = <&pm8058>;
 431                                         interrupts = <39 1>;
 432                                         allow-set-time;
 433                                 };
 434
 435                                 vibrator@4a {
 436                                         compatible = "qcom,pm8058-vib";
 437                                         reg = <0x4a>;
 438                                 };
 439                         };
 440                 };
 441
 442                 l2cc: clock-controller@2082000 {
 443                         compatible      = "syscon";
 444                         reg             = <0x02082000 0x1000>;
 445                 };
 446
 447                 rpm: rpm@104000 {
 448                         compatible      = "qcom,rpm-msm8660";
 449                         reg             = <0x00104000 0x1000>;
 450                         qcom,ipc        = <&l2cc 0x8 2>;
 451
 452                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 453                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 454                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 455                         interrupt-names = "ack", "err", "wakeup";
 456                         clocks = <&gcc RPM_MSG_RAM_H_CLK>;
 457                         clock-names = "ram";
 458
 459                         rpmcc: clock-controller {
 460                                 compatible      = "qcom,rpmcc-msm8660", "qcom,rpmcc";
 461                                 #clock-cells = <1>;
 462                         };
 463
 464                         pm8901-regulators {
 465                                 compatible = "qcom,rpm-pm8901-regulators";
 466
 467                                 pm8901_l0: l0 {};
 468                                 pm8901_l1: l1 {};
 469                                 pm8901_l2: l2 {};
 470                                 pm8901_l3: l3 {};
 471                                 pm8901_l4: l4 {};
 472                                 pm8901_l5: l5 {};
 473                                 pm8901_l6: l6 {};
 474
 475                                 /* S0 and S1 Handled as SAW regulators by SPM */
 476                                 pm8901_s2: s2 {};
 477                                 pm8901_s3: s3 {};
 478                                 pm8901_s4: s4 {};
 479
 480                                 pm8901_lvs0: lvs0 {};
 481                                 pm8901_lvs1: lvs1 {};
 482                                 pm8901_lvs2: lvs2 {};
 483                                 pm8901_lvs3: lvs3 {};
 484
 485                                 pm8901_mvs: mvs {};
 486                         };
 487
 488                         pm8058-regulators {
 489                                 compatible = "qcom,rpm-pm8058-regulators";
 490
 491                                 pm8058_l0: l0 {};
 492                                 pm8058_l1: l1 {};
 493                                 pm8058_l2: l2 {};
 494                                 pm8058_l3: l3 {};
 495                                 pm8058_l4: l4 {};
 496                                 pm8058_l5: l5 {};
 497                                 pm8058_l6: l6 {};
 498                                 pm8058_l7: l7 {};
 499                                 pm8058_l8: l8 {};
 500                                 pm8058_l9: l9 {};
 501                                 pm8058_l10: l10 {};
 502                                 pm8058_l11: l11 {};
 503                                 pm8058_l12: l12 {};
 504                                 pm8058_l13: l13 {};
 505                                 pm8058_l14: l14 {};
 506                                 pm8058_l15: l15 {};
 507                                 pm8058_l16: l16 {};
 508                                 pm8058_l17: l17 {};
 509                                 pm8058_l18: l18 {};
 510                                 pm8058_l19: l19 {};
 511                                 pm8058_l20: l20 {};
 512                                 pm8058_l21: l21 {};
 513                                 pm8058_l22: l22 {};
 514                                 pm8058_l23: l23 {};
 515                                 pm8058_l24: l24 {};
 516                                 pm8058_l25: l25 {};
 517
 518                                 pm8058_s0: s0 {};
 519                                 pm8058_s1: s1 {};
 520                                 pm8058_s2: s2 {};
 521                                 pm8058_s3: s3 {};
 522                                 pm8058_s4: s4 {};
 523
 524                                 pm8058_lvs0: lvs0 {};
 525                                 pm8058_lvs1: lvs1 {};
 526
 527                                 pm8058_ncp: ncp {};
 528                         };
 529                 };
 530
 531                 amba {
 532                         compatible = "simple-bus";
 533                         #address-cells = <1>;
 534                         #size-cells = <1>;
 535                         ranges;
 536                         sdcc1: sdcc@12400000 {
 537                                 status          = "disabled";
 538                                 compatible      = "arm,pl18x", "arm,primecell";
 539                                 arm,primecell-periphid = <0x00051180>;
 540                                 reg             = <0x12400000 0x8000>;
 541                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 542                                 interrupt-names = "cmd_irq";
 543                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 544                                 clock-names     = "mclk", "apb_pclk";
 545                                 bus-width       = <8>;
 546                                 max-frequency   = <48000000>;
 547                                 non-removable;
 548                                 cap-sd-highspeed;
 549                                 cap-mmc-highspeed;
 550                         };
 551
 552                         sdcc2: sdcc@12140000 {
 553                                 status          = "disabled";
 554                                 compatible      = "arm,pl18x", "arm,primecell";
 555                                 arm,primecell-periphid = <0x00051180>;
 556                                 reg             = <0x12140000 0x8000>;
 557                                 interrupts      = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 558                                 interrupt-names = "cmd_irq";
 559                                 clocks          = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
 560                                 clock-names     = "mclk", "apb_pclk";
 561                                 bus-width       = <8>;
 562                                 max-frequency   = <48000000>;
 563                                 cap-sd-highspeed;
 564                                 cap-mmc-highspeed;
 565                         };
 566
 567                         sdcc3: sdcc@12180000 {
 568                                 compatible      = "arm,pl18x", "arm,primecell";
 569                                 arm,primecell-periphid = <0x00051180>;
 570                                 status          = "disabled";
 571                                 reg             = <0x12180000 0x8000>;
 572                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 573                                 interrupt-names = "cmd_irq";
 574                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 575                                 clock-names     = "mclk", "apb_pclk";
 576                                 bus-width       = <4>;
 577                                 cap-sd-highspeed;
 578                                 cap-mmc-highspeed;
 579                                 max-frequency   = <48000000>;
 580                                 no-1-8-v;
 581                         };
 582
 583                         sdcc4: sdcc@121c0000 {
 584                                 compatible      = "arm,pl18x", "arm,primecell";
 585                                 arm,primecell-periphid = <0x00051180>;
 586                                 status          = "disabled";
 587                                 reg             = <0x121c0000 0x8000>;
 588                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 589                                 interrupt-names = "cmd_irq";
 590                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 591                                 clock-names     = "mclk", "apb_pclk";
 592                                 bus-width       = <4>;
 593                                 max-frequency   = <48000000>;
 594                                 cap-sd-highspeed;
 595                                 cap-mmc-highspeed;
 596                         };
 597
 598                         sdcc5: sdcc@12200000 {
 599                                 compatible      = "arm,pl18x", "arm,primecell";
 600                                 arm,primecell-periphid = <0x00051180>;
 601                                 status          = "disabled";
 602                                 reg             = <0x12200000 0x8000>;
 603                                 interrupts      = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 604                                 interrupt-names = "cmd_irq";
 605                                 clocks          = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
 606                                 clock-names     = "mclk", "apb_pclk";
 607                                 bus-width       = <4>;
 608                                 cap-sd-highspeed;
 609                                 cap-mmc-highspeed;
 610                                 max-frequency   = <48000000>;
 611                         };
 612                 };
 613
 614                 tcsr: syscon@1a400000 {
 615                         compatible = "qcom,tcsr-msm8660", "syscon";
 616                         reg = <0x1a400000 0x100>;
 617                 };
 618         };
 619
 620 };