arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13 #include <dt-bindings/clock/omap5.h>
  14
  15 / {
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         compatible = "ti,omap5";
  20         interrupt-parent = <&wakeupgen>;
  21         chosen { };
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 1000000 1060000
  49                                 1500000 1250000
  50                         >;
  51
  52                         clocks = <&dpll_mpu_ck>;
  53                         clock-names = "cpu";
  54
  55                         clock-latency = <300000>; /* From omap-cpufreq driver */
  56
  57                         /* cooling options */
  58                         #cooling-cells = <2>; /* min followed by max */
  59                 };
  60                 cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a15";
  63                         reg = <0x1>;
  64                 };
  65         };
  66
  67         thermal-zones {
  68                 #include "omap4-cpu-thermal.dtsi"
  69                 #include "omap5-gpu-thermal.dtsi"
  70                 #include "omap5-core-thermal.dtsi"
  71         };
  72
  73         timer {
  74                 compatible = "arm,armv7-timer";
  75                 /* PPI secure/nonsecure IRQ */
  76                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  77                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  78                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  79                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  80                 interrupt-parent = <&gic>;
  81         };
  82
  83         pmu {
  84                 compatible = "arm,cortex-a15-pmu";
  85                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  86                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  87         };
  88
  89         gic: interrupt-controller@48211000 {
  90                 compatible = "arm,cortex-a15-gic";
  91                 interrupt-controller;
  92                 #interrupt-cells = <3>;
  93                 reg = <0 0x48211000 0 0x1000>,
  94                       <0 0x48212000 0 0x2000>,
  95                       <0 0x48214000 0 0x2000>,
  96                       <0 0x48216000 0 0x2000>;
  97                 interrupt-parent = <&gic>;
  98         };
  99
 100         wakeupgen: interrupt-controller@48281000 {
 101                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 102                 interrupt-controller;
 103                 #interrupt-cells = <3>;
 104                 reg = <0 0x48281000 0 0x1000>;
 105                 interrupt-parent = <&gic>;
 106         };
 107
 108         /*
 109          * The soc node represents the soc top level view. It is used for IPs
 110          * that are not memory mapped in the MPU view or for the MPU itself.
 111          */
 112         soc {
 113                 compatible = "ti,omap-infra";
 114                 mpu {
 115                         compatible = "ti,omap4-mpu";
 116                         ti,hwmods = "mpu";
 117                         sram = <&ocmcram>;
 118                 };
 119         };
 120
 121         /*
 122          * XXX: Use a flat representation of the OMAP3 interconnect.
 123          * The real OMAP interconnect network is quite complex.
 124          * Since it will not bring real advantage to represent that in DT for
 125          * the moment, just use a fake OCP bus entry to represent the whole bus
 126          * hierarchy.
 127          */
 128         ocp {
 129                 compatible = "ti,omap5-l3-noc", "simple-bus";
 130                 #address-cells = <1>;
 131                 #size-cells = <1>;
 132                 ranges = <0 0 0 0xc0000000>;
 133                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 134                 reg = <0 0x44000000 0 0x2000>,
 135                       <0 0x44800000 0 0x3000>,
 136                       <0 0x45000000 0 0x4000>;
 137                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 138                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 139
 140                 l4_cfg: l4@4a000000 {
 141                         compatible = "ti,omap5-l4-cfg", "simple-bus";
 142                         #address-cells = <1>;
 143                         #size-cells = <1>;
 144                         ranges = <0 0x4a000000 0x22a000>;
 145
 146                         scm_core: scm@2000 {
 147                                 compatible = "ti,omap5-scm-core", "simple-bus";
 148                                 reg = <0x2000 0x1000>;
 149                                 #address-cells = <1>;
 150                                 #size-cells = <1>;
 151                                 ranges = <0 0x2000 0x800>;
 152
 153                                 scm_conf: scm_conf@0 {
 154                                         compatible = "syscon";
 155                                         reg = <0x0 0x800>;
 156                                         #address-cells = <1>;
 157                                         #size-cells = <1>;
 158                                 };
 159                         };
 160
 161                         scm_padconf_core: scm@2800 {
 162                                 compatible = "ti,omap5-scm-padconf-core",
 163                                              "simple-bus";
 164                                 #address-cells = <1>;
 165                                 #size-cells = <1>;
 166                                 ranges = <0 0x2800 0x800>;
 167
 168                                 omap5_pmx_core: pinmux@40 {
 169                                         compatible = "ti,omap5-padconf",
 170                                                      "pinctrl-single";
 171                                         reg = <0x40 0x01b6>;
 172                                         #address-cells = <1>;
 173                                         #size-cells = <0>;
 174                                         #pinctrl-cells = <1>;
 175                                         #interrupt-cells = <1>;
 176                                         interrupt-controller;
 177                                         pinctrl-single,register-width = <16>;
 178                                         pinctrl-single,function-mask = <0x7fff>;
 179                                 };
 180
 181                                 omap5_padconf_global: omap5_padconf_global@5a0 {
 182                                         compatible = "syscon",
 183                                                      "simple-bus";
 184                                         reg = <0x5a0 0xec>;
 185                                         #address-cells = <1>;
 186                                         #size-cells = <1>;
 187                                         ranges = <0 0x5a0 0xec>;
 188
 189                                         pbias_regulator: pbias_regulator@60 {
 190                                                 compatible = "ti,pbias-omap5", "ti,pbias-omap";
 191                                                 reg = <0x60 0x4>;
 192                                                 syscon = <&omap5_padconf_global>;
 193                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 194                                                         regulator-name = "pbias_mmc_omap5";
 195                                                         regulator-min-microvolt = <1800000>;
 196                                                         regulator-max-microvolt = <3300000>;
 197                                                 };
 198                                         };
 199                                 };
 200                         };
 201
 202                         cm_core_aon: cm_core_aon@4000 {
 203                                 compatible = "ti,omap5-cm-core-aon",
 204                                              "simple-bus";
 205                                 reg = <0x4000 0x2000>;
 206                                 #address-cells = <1>;
 207                                 #size-cells = <1>;
 208                                 ranges = <0 0x4000 0x2000>;
 209
 210                                 cm_core_aon_clocks: clocks {
 211                                         #address-cells = <1>;
 212                                         #size-cells = <0>;
 213                                 };
 214
 215                                 cm_core_aon_clockdomains: clockdomains {
 216                                 };
 217                         };
 218
 219                         cm_core: cm_core@8000 {
 220                                 compatible = "ti,omap5-cm-core", "simple-bus";
 221                                 reg = <0x8000 0x3000>;
 222                                 #address-cells = <1>;
 223                                 #size-cells = <1>;
 224                                 ranges = <0 0x8000 0x3000>;
 225
 226                                 cm_core_clocks: clocks {
 227                                         #address-cells = <1>;
 228                                         #size-cells = <0>;
 229                                 };
 230
 231                                 cm_core_clockdomains: clockdomains {
 232                                 };
 233                         };
 234                 };
 235
 236                 l4_wkup: l4@4ae00000 {
 237                         compatible = "ti,omap5-l4-wkup", "simple-bus";
 238                         #address-cells = <1>;
 239                         #size-cells = <1>;
 240                         ranges = <0 0x4ae00000 0x2b000>;
 241
 242                         counter32k: counter@4000 {
 243                                 compatible = "ti,omap-counter32k";
 244                                 reg = <0x4000 0x40>;
 245                                 ti,hwmods = "counter_32k";
 246                         };
 247
 248                         prm: prm@6000 {
 249                                 compatible = "ti,omap5-prm", "simple-bus";
 250                                 reg = <0x6000 0x3000>;
 251                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 252                                 #address-cells = <1>;
 253                                 #size-cells = <1>;
 254                                 ranges = <0 0x6000 0x3000>;
 255
 256                                 prm_clocks: clocks {
 257                                         #address-cells = <1>;
 258                                         #size-cells = <0>;
 259                                 };
 260
 261                                 prm_clockdomains: clockdomains {
 262                                 };
 263                         };
 264
 265                         scrm: scrm@a000 {
 266                                 compatible = "ti,omap5-scrm";
 267                                 reg = <0xa000 0x2000>;
 268
 269                                 scrm_clocks: clocks {
 270                                         #address-cells = <1>;
 271                                         #size-cells = <0>;
 272                                 };
 273
 274                                 scrm_clockdomains: clockdomains {
 275                                 };
 276                         };
 277
 278                         omap5_pmx_wkup: pinmux@c840 {
 279                                 compatible = "ti,omap5-padconf",
 280                                              "pinctrl-single";
 281                                 reg = <0xc840 0x003c>;
 282                                 #address-cells = <1>;
 283                                 #size-cells = <0>;
 284                                 #pinctrl-cells = <1>;
 285                                 #interrupt-cells = <1>;
 286                                 interrupt-controller;
 287                                 pinctrl-single,register-width = <16>;
 288                                 pinctrl-single,function-mask = <0x7fff>;
 289                         };
 290                 };
 291
 292                 ocmcram: ocmcram@40300000 {
 293                         compatible = "mmio-sram";
 294                         reg = <0x40300000 0x20000>; /* 128k */
 295                 };
 296
 297                 sdma: dma-controller@4a056000 {
 298                         compatible = "ti,omap4430-sdma";
 299                         reg = <0x4a056000 0x1000>;
 300                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 301                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 302                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 303                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 304                         #dma-cells = <1>;
 305                         dma-channels = <32>;
 306                         dma-requests = <127>;
 307                         ti,hwmods = "dma_system";
 308                 };
 309
 310                 gpio1: gpio@4ae10000 {
 311                         compatible = "ti,omap4-gpio";
 312                         reg = <0x4ae10000 0x200>;
 313                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 314                         ti,hwmods = "gpio1";
 315                         ti,gpio-always-on;
 316                         gpio-controller;
 317                         #gpio-cells = <2>;
 318                         interrupt-controller;
 319                         #interrupt-cells = <2>;
 320                 };
 321
 322                 gpio2: gpio@48055000 {
 323                         compatible = "ti,omap4-gpio";
 324                         reg = <0x48055000 0x200>;
 325                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 326                         ti,hwmods = "gpio2";
 327                         gpio-controller;
 328                         #gpio-cells = <2>;
 329                         interrupt-controller;
 330                         #interrupt-cells = <2>;
 331                 };
 332
 333                 gpio3: gpio@48057000 {
 334                         compatible = "ti,omap4-gpio";
 335                         reg = <0x48057000 0x200>;
 336                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 337                         ti,hwmods = "gpio3";
 338                         gpio-controller;
 339                         #gpio-cells = <2>;
 340                         interrupt-controller;
 341                         #interrupt-cells = <2>;
 342                 };
 343
 344                 gpio4: gpio@48059000 {
 345                         compatible = "ti,omap4-gpio";
 346                         reg = <0x48059000 0x200>;
 347                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 348                         ti,hwmods = "gpio4";
 349                         gpio-controller;
 350                         #gpio-cells = <2>;
 351                         interrupt-controller;
 352                         #interrupt-cells = <2>;
 353                 };
 354
 355                 gpio5: gpio@4805b000 {
 356                         compatible = "ti,omap4-gpio";
 357                         reg = <0x4805b000 0x200>;
 358                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 359                         ti,hwmods = "gpio5";
 360                         gpio-controller;
 361                         #gpio-cells = <2>;
 362                         interrupt-controller;
 363                         #interrupt-cells = <2>;
 364                 };
 365
 366                 gpio6: gpio@4805d000 {
 367                         compatible = "ti,omap4-gpio";
 368                         reg = <0x4805d000 0x200>;
 369                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 370                         ti,hwmods = "gpio6";
 371                         gpio-controller;
 372                         #gpio-cells = <2>;
 373                         interrupt-controller;
 374                         #interrupt-cells = <2>;
 375                 };
 376
 377                 gpio7: gpio@48051000 {
 378                         compatible = "ti,omap4-gpio";
 379                         reg = <0x48051000 0x200>;
 380                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 381                         ti,hwmods = "gpio7";
 382                         gpio-controller;
 383                         #gpio-cells = <2>;
 384                         interrupt-controller;
 385                         #interrupt-cells = <2>;
 386                 };
 387
 388                 gpio8: gpio@48053000 {
 389                         compatible = "ti,omap4-gpio";
 390                         reg = <0x48053000 0x200>;
 391                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 392                         ti,hwmods = "gpio8";
 393                         gpio-controller;
 394                         #gpio-cells = <2>;
 395                         interrupt-controller;
 396                         #interrupt-cells = <2>;
 397                 };
 398
 399                 gpmc: gpmc@50000000 {
 400                         compatible = "ti,omap4430-gpmc";
 401                         reg = <0x50000000 0x1000>;
 402                         #address-cells = <2>;
 403                         #size-cells = <1>;
 404                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 405                         dmas = <&sdma 4>;
 406                         dma-names = "rxtx";
 407                         gpmc,num-cs = <8>;
 408                         gpmc,num-waitpins = <4>;
 409                         ti,hwmods = "gpmc";
 410                         clocks = <&l3_iclk_div>;
 411                         clock-names = "fck";
 412                         interrupt-controller;
 413                         #interrupt-cells = <2>;
 414                         gpio-controller;
 415                         #gpio-cells = <2>;
 416                 };
 417
 418                 i2c1: i2c@48070000 {
 419                         compatible = "ti,omap4-i2c";
 420                         reg = <0x48070000 0x100>;
 421                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         ti,hwmods = "i2c1";
 425                 };
 426
 427                 i2c2: i2c@48072000 {
 428                         compatible = "ti,omap4-i2c";
 429                         reg = <0x48072000 0x100>;
 430                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         ti,hwmods = "i2c2";
 434                 };
 435
 436                 i2c3: i2c@48060000 {
 437                         compatible = "ti,omap4-i2c";
 438                         reg = <0x48060000 0x100>;
 439                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                         ti,hwmods = "i2c3";
 443                 };
 444
 445                 i2c4: i2c@4807a000 {
 446                         compatible = "ti,omap4-i2c";
 447                         reg = <0x4807a000 0x100>;
 448                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 449                         #address-cells = <1>;
 450                         #size-cells = <0>;
 451                         ti,hwmods = "i2c4";
 452                 };
 453
 454                 i2c5: i2c@4807c000 {
 455                         compatible = "ti,omap4-i2c";
 456                         reg = <0x4807c000 0x100>;
 457                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                         ti,hwmods = "i2c5";
 461                 };
 462
 463                 hwspinlock: spinlock@4a0f6000 {
 464                         compatible = "ti,omap4-hwspinlock";
 465                         reg = <0x4a0f6000 0x1000>;
 466                         ti,hwmods = "spinlock";
 467                         #hwlock-cells = <1>;
 468                 };
 469
 470                 mcspi1: spi@48098000 {
 471                         compatible = "ti,omap4-mcspi";
 472                         reg = <0x48098000 0x200>;
 473                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                         ti,hwmods = "mcspi1";
 477                         ti,spi-num-cs = <4>;
 478                         dmas = <&sdma 35>,
 479                                <&sdma 36>,
 480                                <&sdma 37>,
 481                                <&sdma 38>,
 482                                <&sdma 39>,
 483                                <&sdma 40>,
 484                                <&sdma 41>,
 485                                <&sdma 42>;
 486                         dma-names = "tx0", "rx0", "tx1", "rx1",
 487                                     "tx2", "rx2", "tx3", "rx3";
 488                 };
 489
 490                 mcspi2: spi@4809a000 {
 491                         compatible = "ti,omap4-mcspi";
 492                         reg = <0x4809a000 0x200>;
 493                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 494                         #address-cells = <1>;
 495                         #size-cells = <0>;
 496                         ti,hwmods = "mcspi2";
 497                         ti,spi-num-cs = <2>;
 498                         dmas = <&sdma 43>,
 499                                <&sdma 44>,
 500                                <&sdma 45>,
 501                                <&sdma 46>;
 502                         dma-names = "tx0", "rx0", "tx1", "rx1";
 503                 };
 504
 505                 mcspi3: spi@480b8000 {
 506                         compatible = "ti,omap4-mcspi";
 507                         reg = <0x480b8000 0x200>;
 508                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511                         ti,hwmods = "mcspi3";
 512                         ti,spi-num-cs = <2>;
 513                         dmas = <&sdma 15>, <&sdma 16>;
 514                         dma-names = "tx0", "rx0";
 515                 };
 516
 517                 mcspi4: spi@480ba000 {
 518                         compatible = "ti,omap4-mcspi";
 519                         reg = <0x480ba000 0x200>;
 520                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                         ti,hwmods = "mcspi4";
 524                         ti,spi-num-cs = <1>;
 525                         dmas = <&sdma 70>, <&sdma 71>;
 526                         dma-names = "tx0", "rx0";
 527                 };
 528
 529                 uart1: serial@4806a000 {
 530                         compatible = "ti,omap4-uart";
 531                         reg = <0x4806a000 0x100>;
 532                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 533                         ti,hwmods = "uart1";
 534                         clock-frequency = <48000000>;
 535                 };
 536
 537                 uart2: serial@4806c000 {
 538                         compatible = "ti,omap4-uart";
 539                         reg = <0x4806c000 0x100>;
 540                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 541                         ti,hwmods = "uart2";
 542                         clock-frequency = <48000000>;
 543                 };
 544
 545                 uart3: serial@48020000 {
 546                         compatible = "ti,omap4-uart";
 547                         reg = <0x48020000 0x100>;
 548                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 549                         ti,hwmods = "uart3";
 550                         clock-frequency = <48000000>;
 551                 };
 552
 553                 uart4: serial@4806e000 {
 554                         compatible = "ti,omap4-uart";
 555                         reg = <0x4806e000 0x100>;
 556                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 557                         ti,hwmods = "uart4";
 558                         clock-frequency = <48000000>;
 559                 };
 560
 561                 uart5: serial@48066000 {
 562                         compatible = "ti,omap4-uart";
 563                         reg = <0x48066000 0x100>;
 564                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 565                         ti,hwmods = "uart5";
 566                         clock-frequency = <48000000>;
 567                 };
 568
 569                 uart6: serial@48068000 {
 570                         compatible = "ti,omap4-uart";
 571                         reg = <0x48068000 0x100>;
 572                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 573                         ti,hwmods = "uart6";
 574                         clock-frequency = <48000000>;
 575                 };
 576
 577                 mmc1: mmc@4809c000 {
 578                         compatible = "ti,omap4-hsmmc";
 579                         reg = <0x4809c000 0x400>;
 580                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 581                         ti,hwmods = "mmc1";
 582                         ti,dual-volt;
 583                         ti,needs-special-reset;
 584                         dmas = <&sdma 61>, <&sdma 62>;
 585                         dma-names = "tx", "rx";
 586                         pbias-supply = <&pbias_mmc_reg>;
 587                 };
 588
 589                 mmc2: mmc@480b4000 {
 590                         compatible = "ti,omap4-hsmmc";
 591                         reg = <0x480b4000 0x400>;
 592                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 593                         ti,hwmods = "mmc2";
 594                         ti,needs-special-reset;
 595                         dmas = <&sdma 47>, <&sdma 48>;
 596                         dma-names = "tx", "rx";
 597                 };
 598
 599                 mmc3: mmc@480ad000 {
 600                         compatible = "ti,omap4-hsmmc";
 601                         reg = <0x480ad000 0x400>;
 602                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 603                         ti,hwmods = "mmc3";
 604                         ti,needs-special-reset;
 605                         dmas = <&sdma 77>, <&sdma 78>;
 606                         dma-names = "tx", "rx";
 607                 };
 608
 609                 mmc4: mmc@480d1000 {
 610                         compatible = "ti,omap4-hsmmc";
 611                         reg = <0x480d1000 0x400>;
 612                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 613                         ti,hwmods = "mmc4";
 614                         ti,needs-special-reset;
 615                         dmas = <&sdma 57>, <&sdma 58>;
 616                         dma-names = "tx", "rx";
 617                 };
 618
 619                 mmc5: mmc@480d5000 {
 620                         compatible = "ti,omap4-hsmmc";
 621                         reg = <0x480d5000 0x400>;
 622                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 623                         ti,hwmods = "mmc5";
 624                         ti,needs-special-reset;
 625                         dmas = <&sdma 59>, <&sdma 60>;
 626                         dma-names = "tx", "rx";
 627                 };
 628
 629                 mmu_dsp: mmu@4a066000 {
 630                         compatible = "ti,omap4-iommu";
 631                         reg = <0x4a066000 0x100>;
 632                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 633                         ti,hwmods = "mmu_dsp";
 634                         #iommu-cells = <0>;
 635                 };
 636
 637                 mmu_ipu: mmu@55082000 {
 638                         compatible = "ti,omap4-iommu";
 639                         reg = <0x55082000 0x100>;
 640                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 641                         ti,hwmods = "mmu_ipu";
 642                         #iommu-cells = <0>;
 643                         ti,iommu-bus-err-back;
 644                 };
 645
 646                 keypad: keypad@4ae1c000 {
 647                         compatible = "ti,omap4-keypad";
 648                         reg = <0x4ae1c000 0x400>;
 649                         ti,hwmods = "kbd";
 650                 };
 651
 652                 mcpdm: mcpdm@40132000 {
 653                         compatible = "ti,omap4-mcpdm";
 654                         reg = <0x40132000 0x7f>, /* MPU private access */
 655                               <0x49032000 0x7f>; /* L3 Interconnect */
 656                         reg-names = "mpu", "dma";
 657                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 658                         ti,hwmods = "mcpdm";
 659                         dmas = <&sdma 65>,
 660                                <&sdma 66>;
 661                         dma-names = "up_link", "dn_link";
 662                         status = "disabled";
 663                 };
 664
 665                 dmic: dmic@4012e000 {
 666                         compatible = "ti,omap4-dmic";
 667                         reg = <0x4012e000 0x7f>, /* MPU private access */
 668                               <0x4902e000 0x7f>; /* L3 Interconnect */
 669                         reg-names = "mpu", "dma";
 670                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 671                         ti,hwmods = "dmic";
 672                         dmas = <&sdma 67>;
 673                         dma-names = "up_link";
 674                         status = "disabled";
 675                 };
 676
 677                 mcbsp1: mcbsp@40122000 {
 678                         compatible = "ti,omap4-mcbsp";
 679                         reg = <0x40122000 0xff>, /* MPU private access */
 680                               <0x49022000 0xff>; /* L3 Interconnect */
 681                         reg-names = "mpu", "dma";
 682                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 683                         interrupt-names = "common";
 684                         ti,buffer-size = <128>;
 685                         ti,hwmods = "mcbsp1";
 686                         dmas = <&sdma 33>,
 687                                <&sdma 34>;
 688                         dma-names = "tx", "rx";
 689                         status = "disabled";
 690                 };
 691
 692                 mcbsp2: mcbsp@40124000 {
 693                         compatible = "ti,omap4-mcbsp";
 694                         reg = <0x40124000 0xff>, /* MPU private access */
 695                               <0x49024000 0xff>; /* L3 Interconnect */
 696                         reg-names = "mpu", "dma";
 697                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 698                         interrupt-names = "common";
 699                         ti,buffer-size = <128>;
 700                         ti,hwmods = "mcbsp2";
 701                         dmas = <&sdma 17>,
 702                                <&sdma 18>;
 703                         dma-names = "tx", "rx";
 704                         status = "disabled";
 705                 };
 706
 707                 mcbsp3: mcbsp@40126000 {
 708                         compatible = "ti,omap4-mcbsp";
 709                         reg = <0x40126000 0xff>, /* MPU private access */
 710                               <0x49026000 0xff>; /* L3 Interconnect */
 711                         reg-names = "mpu", "dma";
 712                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 713                         interrupt-names = "common";
 714                         ti,buffer-size = <128>;
 715                         ti,hwmods = "mcbsp3";
 716                         dmas = <&sdma 19>,
 717                                <&sdma 20>;
 718                         dma-names = "tx", "rx";
 719                         status = "disabled";
 720                 };
 721
 722                 mailbox: mailbox@4a0f4000 {
 723                         compatible = "ti,omap4-mailbox";
 724                         reg = <0x4a0f4000 0x200>;
 725                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 726                         ti,hwmods = "mailbox";
 727                         #mbox-cells = <1>;
 728                         ti,mbox-num-users = <3>;
 729                         ti,mbox-num-fifos = <8>;
 730                         mbox_ipu: mbox_ipu {
 731                                 ti,mbox-tx = <0 0 0>;
 732                                 ti,mbox-rx = <1 0 0>;
 733                         };
 734                         mbox_dsp: mbox_dsp {
 735                                 ti,mbox-tx = <3 0 0>;
 736                                 ti,mbox-rx = <2 0 0>;
 737                         };
 738                 };
 739
 740                 timer1: timer@4ae18000 {
 741                         compatible = "ti,omap5430-timer";
 742                         reg = <0x4ae18000 0x80>;
 743                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 744                         ti,hwmods = "timer1";
 745                         ti,timer-alwon;
 746                         clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
 747                         clock-names = "fck";
 748                 };
 749
 750                 timer2: timer@48032000 {
 751                         compatible = "ti,omap5430-timer";
 752                         reg = <0x48032000 0x80>;
 753                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 754                         ti,hwmods = "timer2";
 755                 };
 756
 757                 timer3: timer@48034000 {
 758                         compatible = "ti,omap5430-timer";
 759                         reg = <0x48034000 0x80>;
 760                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 761                         ti,hwmods = "timer3";
 762                 };
 763
 764                 timer4: timer@48036000 {
 765                         compatible = "ti,omap5430-timer";
 766                         reg = <0x48036000 0x80>;
 767                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 768                         ti,hwmods = "timer4";
 769                 };
 770
 771                 timer5: timer@40138000 {
 772                         compatible = "ti,omap5430-timer";
 773                         reg = <0x40138000 0x80>,
 774                               <0x49038000 0x80>;
 775                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 776                         ti,hwmods = "timer5";
 777                         ti,timer-dsp;
 778                         ti,timer-pwm;
 779                 };
 780
 781                 timer6: timer@4013a000 {
 782                         compatible = "ti,omap5430-timer";
 783                         reg = <0x4013a000 0x80>,
 784                               <0x4903a000 0x80>;
 785                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 786                         ti,hwmods = "timer6";
 787                         ti,timer-dsp;
 788                         ti,timer-pwm;
 789                 };
 790
 791                 timer7: timer@4013c000 {
 792                         compatible = "ti,omap5430-timer";
 793                         reg = <0x4013c000 0x80>,
 794                               <0x4903c000 0x80>;
 795                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 796                         ti,hwmods = "timer7";
 797                         ti,timer-dsp;
 798                 };
 799
 800                 timer8: timer@4013e000 {
 801                         compatible = "ti,omap5430-timer";
 802                         reg = <0x4013e000 0x80>,
 803                               <0x4903e000 0x80>;
 804                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 805                         ti,hwmods = "timer8";
 806                         ti,timer-dsp;
 807                         ti,timer-pwm;
 808                 };
 809
 810                 timer9: timer@4803e000 {
 811                         compatible = "ti,omap5430-timer";
 812                         reg = <0x4803e000 0x80>;
 813                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 814                         ti,hwmods = "timer9";
 815                         ti,timer-pwm;
 816                 };
 817
 818                 timer10: timer@48086000 {
 819                         compatible = "ti,omap5430-timer";
 820                         reg = <0x48086000 0x80>;
 821                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 822                         ti,hwmods = "timer10";
 823                         ti,timer-pwm;
 824                 };
 825
 826                 timer11: timer@48088000 {
 827                         compatible = "ti,omap5430-timer";
 828                         reg = <0x48088000 0x80>;
 829                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 830                         ti,hwmods = "timer11";
 831                         ti,timer-pwm;
 832                 };
 833
 834                 wdt2: wdt@4ae14000 {
 835                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 836                         reg = <0x4ae14000 0x80>;
 837                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 838                         ti,hwmods = "wd_timer2";
 839                 };
 840
 841                 dmm@4e000000 {
 842                         compatible = "ti,omap5-dmm";
 843                         reg = <0x4e000000 0x800>;
 844                         interrupts = <0 113 0x4>;
 845                         ti,hwmods = "dmm";
 846                 };
 847
 848                 emif1: emif@4c000000 {
 849                         compatible      = "ti,emif-4d5";
 850                         ti,hwmods       = "emif1";
 851                         ti,no-idle-on-init;
 852                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 853                         reg = <0x4c000000 0x400>;
 854                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 855                         hw-caps-read-idle-ctrl;
 856                         hw-caps-ll-interface;
 857                         hw-caps-temp-alert;
 858                 };
 859
 860                 emif2: emif@4d000000 {
 861                         compatible      = "ti,emif-4d5";
 862                         ti,hwmods       = "emif2";
 863                         ti,no-idle-on-init;
 864                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 865                         reg = <0x4d000000 0x400>;
 866                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 867                         hw-caps-read-idle-ctrl;
 868                         hw-caps-ll-interface;
 869                         hw-caps-temp-alert;
 870                 };
 871
 872                 usb3: omap_dwc3@4a020000 {
 873                         compatible = "ti,dwc3";
 874                         ti,hwmods = "usb_otg_ss";
 875                         reg = <0x4a020000 0x10000>;
 876                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 877                         #address-cells = <1>;
 878                         #size-cells = <1>;
 879                         utmi-mode = <2>;
 880                         ranges;
 881                         dwc3: dwc3@4a030000 {
 882                                 compatible = "snps,dwc3";
 883                                 reg = <0x4a030000 0x10000>;
 884                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 885                                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 886                                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 887                                 interrupt-names = "peripheral",
 888                                                   "host",
 889                                                   "otg";
 890                                 phys = <&usb2_phy>, <&usb3_phy>;
 891                                 phy-names = "usb2-phy", "usb3-phy";
 892                                 dr_mode = "peripheral";
 893                         };
 894                 };
 895
 896                 ocp2scp@4a080000 {
 897                         compatible = "ti,omap-ocp2scp";
 898                         #address-cells = <1>;
 899                         #size-cells = <1>;
 900                         reg = <0x4a080000 0x20>;
 901                         ranges;
 902                         ti,hwmods = "ocp2scp1";
 903                         usb2_phy: usb2phy@4a084000 {
 904                                 compatible = "ti,omap-usb2";
 905                                 reg = <0x4a084000 0x7c>;
 906                                 syscon-phy-power = <&scm_conf 0x300>;
 907                                 clocks = <&usb_phy_cm_clk32k>,
 908                                          <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
 909                                 clock-names = "wkupclk", "refclk";
 910                                 #phy-cells = <0>;
 911                         };
 912
 913                         usb3_phy: usb3phy@4a084400 {
 914                                 compatible = "ti,omap-usb3";
 915                                 reg = <0x4a084400 0x80>,
 916                                       <0x4a084800 0x64>,
 917                                       <0x4a084c00 0x40>;
 918                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 919                                 syscon-phy-power = <&scm_conf 0x370>;
 920                                 clocks = <&usb_phy_cm_clk32k>,
 921                                          <&sys_clkin>,
 922                                          <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
 923                                 clock-names =   "wkupclk",
 924                                                 "sysclk",
 925                                                 "refclk";
 926                                 #phy-cells = <0>;
 927                         };
 928                 };
 929
 930                 usbhstll: usbhstll@4a062000 {
 931                         compatible = "ti,usbhs-tll";
 932                         reg = <0x4a062000 0x1000>;
 933                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 934                         ti,hwmods = "usb_tll_hs";
 935                 };
 936
 937                 usbhshost: usbhshost@4a064000 {
 938                         compatible = "ti,usbhs-host";
 939                         reg = <0x4a064000 0x800>;
 940                         ti,hwmods = "usb_host_hs";
 941                         #address-cells = <1>;
 942                         #size-cells = <1>;
 943                         ranges;
 944                         clocks = <&l3init_60m_fclk>,
 945                                  <&xclk60mhsp1_ck>,
 946                                  <&xclk60mhsp2_ck>;
 947                         clock-names = "refclk_60m_int",
 948                                       "refclk_60m_ext_p1",
 949                                       "refclk_60m_ext_p2";
 950
 951                         usbhsohci: ohci@4a064800 {
 952                                 compatible = "ti,ohci-omap3";
 953                                 reg = <0x4a064800 0x400>;
 954                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 955                                 remote-wakeup-connected;
 956                         };
 957
 958                         usbhsehci: ehci@4a064c00 {
 959                                 compatible = "ti,ehci-omap";
 960                                 reg = <0x4a064c00 0x400>;
 961                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 962                         };
 963                 };
 964
 965                 bandgap: bandgap@4a0021e0 {
 966                         reg = <0x4a0021e0 0xc
 967                                0x4a00232c 0xc
 968                                0x4a002380 0x2c
 969                                0x4a0023C0 0x3c>;
 970                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 971                         compatible = "ti,omap5430-bandgap";
 972
 973                         #thermal-sensor-cells = <1>;
 974                 };
 975
 976                 /* OCP2SCP3 */
 977                 ocp2scp@4a090000 {
 978                         compatible = "ti,omap-ocp2scp";
 979                         #address-cells = <1>;
 980                         #size-cells = <1>;
 981                         reg = <0x4a090000 0x20>;
 982                         ranges;
 983                         ti,hwmods = "ocp2scp3";
 984                         sata_phy: phy@4a096000 {
 985                                 compatible = "ti,phy-pipe3-sata";
 986                                 reg = <0x4A096000 0x80>, /* phy_rx */
 987                                       <0x4A096400 0x64>, /* phy_tx */
 988                                       <0x4A096800 0x40>; /* pll_ctrl */
 989                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 990                                 syscon-phy-power = <&scm_conf 0x374>;
 991                                 clocks = <&sys_clkin>,
 992                                          <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
 993                                 clock-names = "sysclk", "refclk";
 994                                 #phy-cells = <0>;
 995                         };
 996                 };
 997
 998                 sata: sata@4a141100 {
 999                         compatible = "snps,dwc-ahci";
1000                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1001                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1002                         phys = <&sata_phy>;
1003                         phy-names = "sata-phy";
1004                         clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
1005                         ti,hwmods = "sata";
1006                         ports-implemented = <0x1>;
1007                 };
1008
1009                 dss: dss@58000000 {
1010                         compatible = "ti,omap5-dss";
1011                         reg = <0x58000000 0x80>;
1012                         status = "disabled";
1013                         ti,hwmods = "dss_core";
1014                         clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1015                         clock-names = "fck";
1016                         #address-cells = <1>;
1017                         #size-cells = <1>;
1018                         ranges;
1019
1020                         dispc@58001000 {
1021                                 compatible = "ti,omap5-dispc";
1022                                 reg = <0x58001000 0x1000>;
1023                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1024                                 ti,hwmods = "dss_dispc";
1025                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1026                                 clock-names = "fck";
1027                         };
1028
1029                         rfbi: encoder@58002000  {
1030                                 compatible = "ti,omap5-rfbi";
1031                                 reg = <0x58002000 0x100>;
1032                                 status = "disabled";
1033                                 ti,hwmods = "dss_rfbi";
1034                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
1035                                 clock-names = "fck", "ick";
1036                         };
1037
1038                         dsi1: encoder@58004000 {
1039                                 compatible = "ti,omap5-dsi";
1040                                 reg = <0x58004000 0x200>,
1041                                       <0x58004200 0x40>,
1042                                       <0x58004300 0x40>;
1043                                 reg-names = "proto", "phy", "pll";
1044                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1045                                 status = "disabled";
1046                                 ti,hwmods = "dss_dsi1";
1047                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1048                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1049                                 clock-names = "fck", "sys_clk";
1050                         };
1051
1052                         dsi2: encoder@58005000 {
1053                                 compatible = "ti,omap5-dsi";
1054                                 reg = <0x58009000 0x200>,
1055                                       <0x58009200 0x40>,
1056                                       <0x58009300 0x40>;
1057                                 reg-names = "proto", "phy", "pll";
1058                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1059                                 status = "disabled";
1060                                 ti,hwmods = "dss_dsi2";
1061                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1062                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1063                                 clock-names = "fck", "sys_clk";
1064                         };
1065
1066                         hdmi: encoder@58060000 {
1067                                 compatible = "ti,omap5-hdmi";
1068                                 reg = <0x58040000 0x200>,
1069                                       <0x58040200 0x80>,
1070                                       <0x58040300 0x80>,
1071                                       <0x58060000 0x19000>;
1072                                 reg-names = "wp", "pll", "phy", "core";
1073                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1074                                 status = "disabled";
1075                                 ti,hwmods = "dss_hdmi";
1076                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
1077                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1078                                 clock-names = "fck", "sys_clk";
1079                                 dmas = <&sdma 76>;
1080                                 dma-names = "audio_tx";
1081                         };
1082                 };
1083
1084                 abb_mpu: regulator-abb-mpu {
1085                         compatible = "ti,abb-v2";
1086                         regulator-name = "abb_mpu";
1087                         #address-cells = <0>;
1088                         #size-cells = <0>;
1089                         clocks = <&sys_clkin>;
1090                         ti,settling-time = <50>;
1091                         ti,clock-cycles = <16>;
1092
1093                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1094                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1095                         reg-names = "base-address", "int-address",
1096                                     "efuse-address", "ldo-address";
1097                         ti,tranxdone-status-mask = <0x80>;
1098                         /* LDOVBBMPU_MUX_CTRL */
1099                         ti,ldovbb-override-mask = <0x400>;
1100                         /* LDOVBBMPU_VSET_OUT */
1101                         ti,ldovbb-vset-mask = <0x1F>;
1102
1103                         /*
1104                          * NOTE: only FBB mode used but actual vset will
1105                          * determine final biasing
1106                          */
1107                         ti,abb_info = <
1108                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1109                         1060000         0       0x0     0 0x02000000 0x01F00000
1110                         1250000         0       0x4     0 0x02000000 0x01F00000
1111                         >;
1112                 };
1113
1114                 abb_mm: regulator-abb-mm {
1115                         compatible = "ti,abb-v2";
1116                         regulator-name = "abb_mm";
1117                         #address-cells = <0>;
1118                         #size-cells = <0>;
1119                         clocks = <&sys_clkin>;
1120                         ti,settling-time = <50>;
1121                         ti,clock-cycles = <16>;
1122
1123                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1124                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1125                         reg-names = "base-address", "int-address",
1126                                     "efuse-address", "ldo-address";
1127                         ti,tranxdone-status-mask = <0x80000000>;
1128                         /* LDOVBBMM_MUX_CTRL */
1129                         ti,ldovbb-override-mask = <0x400>;
1130                         /* LDOVBBMM_VSET_OUT */
1131                         ti,ldovbb-vset-mask = <0x1F>;
1132
1133                         /*
1134                          * NOTE: only FBB mode used but actual vset will
1135                          * determine final biasing
1136                          */
1137                         ti,abb_info = <
1138                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1139                         1025000         0       0x0     0 0x02000000 0x01F00000
1140                         1120000         0       0x4     0 0x02000000 0x01F00000
1141                         >;
1142                 };
1143         };
1144 };
1145
1146 &cpu_thermal {
1147         polling-delay = <500>; /* milliseconds */
1148         coefficients = <65 (-1791)>;
1149 };
1150
1151 #include "omap54xx-clocks.dtsi"
1152
1153 &gpu_thermal {
1154         coefficients = <117 (-2992)>;
1155 };
1156
1157 &core_thermal {
1158         coefficients = <0 2000>;
1159 };