arch/arm/boot/dts/omap3-igep.dtsi

   1 /*
   2  * Common device tree for IGEP boards based on AM/DM37x
   3  *
   4  * Copyright (C) 2012 Javier Martinez Canillas <javier@osg.samsung.com>
   5  * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 /dts-v1/;
  12
  13 #include "omap36xx.dtsi"
  14
  15 / {
  16         memory@80000000 {
  17                 device_type = "memory";
  18                 reg = <0x80000000 0x20000000>; /* 512 MB */
  19         };
  20
  21         chosen {
  22                 stdout-path = &uart3;
  23         };
  24
  25         sound {
  26                 compatible = "ti,omap-twl4030";
  27                 ti,model = "igep2";
  28                 ti,mcbsp = <&mcbsp2>;
  29         };
  30
  31         vdd33: regulator-vdd33 {
  32                 compatible = "regulator-fixed";
  33                 regulator-name = "vdd33";
  34                 regulator-always-on;
  35         };
  36
  37 };
  38
  39 &omap3_pmx_core {
  40         uart1_pins: pinmux_uart1_pins {
  41                 pinctrl-single,pins = <
  42                         OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0)        /* uart1_rx.uart1_rx */
  43                         OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0)       /* uart1_tx.uart1_tx */
  44                 >;
  45         };
  46
  47         uart3_pins: pinmux_uart3_pins {
  48                 pinctrl-single,pins = <
  49                         OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0)        /* uart3_rx.uart3_rx */
  50                         OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)       /* uart3_tx.uart3_tx */
  51                 >;
  52         };
  53
  54         mcbsp2_pins: pinmux_mcbsp2_pins {
  55                 pinctrl-single,pins = <
  56                         OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx.mcbsp2_fsx */
  57                         OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_clkx.mcbsp2_clkx */
  58                         OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr.mcbsp2.dr */
  59                         OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dx.mcbsp2_dx */
  60                 >;
  61         };
  62
  63         mmc1_pins: pinmux_mmc1_pins {
  64                 pinctrl-single,pins = <
  65                         OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
  66                         OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
  67                         OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
  68                         OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
  69                         OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
  70                         OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
  71                 >;
  72         };
  73
  74         mmc2_pins: pinmux_mmc2_pins {
  75                 pinctrl-single,pins = <
  76                         OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
  77                         OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
  78                         OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
  79                         OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
  80                         OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
  81                         OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
  82                 >;
  83         };
  84
  85         i2c1_pins: pinmux_i2c1_pins {
  86                 pinctrl-single,pins = <
  87                         OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)        /* i2c1_scl.i2c1_scl */
  88                         OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)        /* i2c1_sda.i2c1_sda */
  89                 >;
  90         };
  91
  92         i2c3_pins: pinmux_i2c3_pins {
  93                 pinctrl-single,pins = <
  94                         OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)        /* i2c3_scl.i2c3_scl */
  95                         OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)        /* i2c3_sda.i2c3_sda */
  96                 >;
  97         };
  98 };
  99
 100 &gpmc {
 101         nand@0,0 {
 102                 compatible = "ti,omap2-nand";
 103                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 104                 interrupt-parent = <&gpmc>;
 105                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 106                              <1 IRQ_TYPE_NONE>; /* termcount */
 107                 linux,mtd-name= "micron,mt29c4g96maz";
 108                 nand-bus-width = <16>;
 109                 gpmc,device-width = <2>;
 110                 ti,nand-ecc-opt = "bch8";
 111
 112                 gpmc,sync-clk-ps = <0>;
 113                 gpmc,cs-on-ns = <0>;
 114                 gpmc,cs-rd-off-ns = <44>;
 115                 gpmc,cs-wr-off-ns = <44>;
 116                 gpmc,adv-on-ns = <6>;
 117                 gpmc,adv-rd-off-ns = <34>;
 118                 gpmc,adv-wr-off-ns = <44>;
 119                 gpmc,we-off-ns = <40>;
 120                 gpmc,oe-off-ns = <54>;
 121                 gpmc,access-ns = <64>;
 122                 gpmc,rd-cycle-ns = <82>;
 123                 gpmc,wr-cycle-ns = <82>;
 124                 gpmc,wr-access-ns = <40>;
 125                 gpmc,wr-data-mux-bus-ns = <0>;
 126
 127                 #address-cells = <1>;
 128                 #size-cells = <1>;
 129         };
 130 };
 131
 132 &i2c1 {
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&i2c1_pins>;
 135         clock-frequency = <2600000>;
 136
 137         twl: twl@48 {
 138                 reg = <0x48>;
 139                 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
 140                 interrupt-parent = <&intc>;
 141
 142                 twl_audio: audio {
 143                         compatible = "ti,twl4030-audio";
 144                         codec {
 145                         };
 146                 };
 147         };
 148 };
 149
 150 #include "twl4030.dtsi"
 151 #include "twl4030_omap3.dtsi"
 152
 153 &i2c3 {
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&i2c3_pins>;
 156 };
 157
 158 &mcbsp2 {
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&mcbsp2_pins>;
 161         status = "okay";
 162 };
 163
 164 &mmc1 {
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&mmc1_pins>;
 167         vmmc-supply = <&vmmc1>;
 168         vmmc_aux-supply = <&vsim>;
 169         bus-width = <4>;
 170         cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
 171 };
 172
 173 &mmc3 {
 174         status = "disabled";
 175 };
 176
 177 &uart1 {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&uart1_pins>;
 180 };
 181
 182 &uart3 {
 183         pinctrl-names = "default";
 184         pinctrl-0 = <&uart3_pins>;
 185 };
 186
 187 &twl_gpio {
 188         ti,use-leds;
 189 };
 190
 191 &usb_otg_hs {
 192         interface-type = <0>;
 193         usb-phy = <&usb2_phy>;
 194         phys = <&usb2_phy>;
 195         phy-names = "usb2-phy";
 196         mode = <3>;
 197         power = <50>;
 198 };