1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018 Nuvoton Technology corporation.
3 // Copyright 2018 Google, Inc.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 interrupt-parent = <&gic>;
15 enable-method = "nuvoton,npcm750-smp";
19 compatible = "arm,cortex-a9";
21 clock-names = "clk_cpu";
23 next-level-cache = <&l2>;
28 compatible = "arm,cortex-a9";
30 clock-names = "clk_cpu";
32 next-level-cache = <&l2>;
36 /* external clock signal rg1refck, supplied by the phy */
38 compatible = "fixed-clock";
40 clock-frequency = <125000000>;
43 /* external clock signal rg2refck, supplied by the phy */
45 compatible = "fixed-clock";
47 clock-frequency = <125000000>;
51 compatible = "fixed-clock";
53 clock-frequency = <50000000>;
59 compatible = "simple-bus";
60 interrupt-parent = <&gic>;
61 ranges = <0x0 0xf0000000 0x00900000>;
64 compatible = "nuvoton,npcm750-gcr", "syscon",
66 reg = <0x800000 0x1000>;
70 compatible = "arm,cortex-a9-scu";
71 reg = <0x3fe000 0x1000>;
74 l2: cache-controller@3fc000 {
75 compatible = "arm,pl310-cache";
76 reg = <0x3fc000 0x1000>;
77 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
84 gic: interrupt-controller@3ff000 {
85 compatible = "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
88 reg = <0x3ff000 0x1000>,
93 compatible = "arm,cortex-a9-twd-timer";
94 reg = <0x3fe600 0x20>;
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
96 IRQ_TYPE_LEVEL_HIGH)>;
102 #address-cells = <1>;
104 compatible = "simple-bus";
105 interrupt-parent = <&gic>;
108 clk: clock-controller@f0801000 {
109 compatible = "nuvoton,npcm750-clk";
111 reg = <0xf0801000 0x1000>;
115 #address-cells = <1>;
117 compatible = "simple-bus";
118 interrupt-parent = <&gic>;
119 ranges = <0x0 0xf0000000 0x00300000>;
122 compatible = "nuvoton,npcm750-timer";
123 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
124 reg = <0x8000 0x1000>;
128 serial0: serial@1000 {
129 compatible = "ns16550a";
130 reg = <0x1000 0x1000>;
132 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
137 serial1: serial@2000 {
138 compatible = "ns16550a";
139 reg = <0x2000 0x1000>;
141 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
146 serial2: serial@3000 {
147 compatible = "ns16550a";
148 reg = <0x3000 0x1000>;
150 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
155 serial3: serial@4000 {
156 compatible = "ns16550a";
157 reg = <0x4000 0x1000>;
159 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;