arch/arm/boot/dts/nuvoton-npcm750.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2018 Nuvoton Technology corporation.
   3 // Copyright 2018 Google, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6
   7 / {
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10         interrupt-parent = <&gic>;
  11
  12         cpus {
  13                 #address-cells = <1>;
  14                 #size-cells = <0>;
  15                 enable-method = "nuvoton,npcm750-smp";
  16
  17                 cpu@0 {
  18                         device_type = "cpu";
  19                         compatible = "arm,cortex-a9";
  20                         clocks = <&clk 10>;
  21                         clock-names = "clk_cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&l2>;
  24                 };
  25
  26                 cpu@1 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a9";
  29                         clocks = <&clk 10>;
  30                         clock-names = "clk_cpu";
  31                         reg = <1>;
  32                         next-level-cache = <&l2>;
  33                 };
  34         };
  35
  36         /* external clock signal rg1refck, supplied by the phy */
  37         clk-rg1refck {
  38                 compatible = "fixed-clock";
  39                 #clock-cells = <0>;
  40                 clock-frequency = <125000000>;
  41         };
  42
  43         /* external clock signal rg2refck, supplied by the phy */
  44         clk-rg2refck {
  45                 compatible = "fixed-clock";
  46                 #clock-cells = <0>;
  47                 clock-frequency = <125000000>;
  48         };
  49
  50         clk-xin {
  51                 compatible = "fixed-clock";
  52                 #clock-cells = <0>;
  53                 clock-frequency = <50000000>;
  54         };
  55
  56         soc {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 compatible = "simple-bus";
  60                 interrupt-parent = <&gic>;
  61                 ranges = <0x0 0xf0000000 0x00900000>;
  62
  63                 gcr: gcr@800000 {
  64                         compatible = "nuvoton,npcm750-gcr", "syscon",
  65                                 "simple-mfd";
  66                         reg = <0x800000 0x1000>;
  67                 };
  68
  69                 scu: scu@3fe000 {
  70                         compatible = "arm,cortex-a9-scu";
  71                         reg = <0x3fe000 0x1000>;
  72                 };
  73
  74                 l2: cache-controller@3fc000 {
  75                         compatible = "arm,pl310-cache";
  76                         reg = <0x3fc000 0x1000>;
  77                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  78                         cache-unified;
  79                         cache-level = <2>;
  80                         clocks = <&clk 22>;
  81                         arm,shared-override;
  82                 };
  83
  84                 gic: interrupt-controller@3ff000 {
  85                         compatible = "arm,cortex-a9-gic";
  86                         interrupt-controller;
  87                         #interrupt-cells = <3>;
  88                         reg = <0x3ff000 0x1000>,
  89                             <0x3fe100 0x100>;
  90                 };
  91
  92                 timer@3fe600 {
  93                         compatible = "arm,cortex-a9-twd-timer";
  94                         reg = <0x3fe600 0x20>;
  95                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  96                                                   IRQ_TYPE_LEVEL_HIGH)>;
  97                         clocks = <&clk 15>;
  98                 };
  99         };
 100
 101         ahb {
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 compatible = "simple-bus";
 105                 interrupt-parent = <&gic>;
 106                 ranges;
 107
 108                 clk: clock-controller@f0801000 {
 109                         compatible = "nuvoton,npcm750-clk";
 110                         #clock-cells = <1>;
 111                         reg = <0xf0801000 0x1000>;
 112                 };
 113
 114                 apb {
 115                         #address-cells = <1>;
 116                         #size-cells = <1>;
 117                         compatible = "simple-bus";
 118                         interrupt-parent = <&gic>;
 119                         ranges = <0x0 0xf0000000 0x00300000>;
 120
 121                         timer0: timer@8000 {
 122                                 compatible = "nuvoton,npcm750-timer";
 123                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 124                                 reg = <0x8000 0x1000>;
 125                                 clocks = <&clk 15>;
 126                         };
 127
 128                         serial0: serial@1000 {
 129                                 compatible = "ns16550a";
 130                                 reg = <0x1000 0x1000>;
 131                                 clocks = <&clk 14>;
 132                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 133                                 reg-shift = <2>;
 134                                 status = "disabled";
 135                         };
 136
 137                         serial1: serial@2000 {
 138                                 compatible = "ns16550a";
 139                                 reg = <0x2000 0x1000>;
 140                                 clocks = <&clk 14>;
 141                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 142                                 reg-shift = <2>;
 143                                 status = "disabled";
 144                         };
 145
 146                         serial2: serial@3000 {
 147                                 compatible = "ns16550a";
 148                                 reg = <0x3000 0x1000>;
 149                                 clocks = <&clk 14>;
 150                                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 151                                 reg-shift = <2>;
 152                                 status = "disabled";
 153                         };
 154
 155                         serial3: serial@4000 {
 156                                 compatible = "ns16550a";
 157                                 reg = <0x4000 0x1000>;
 158                                 clocks = <&clk 14>;
 159                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 160                                 reg-shift = <2>;
 161                                 status = "disabled";
 162                         };
 163                 };
 164         };
 165 };