arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 #include "armada-385-clearfog-gtr.dtsi"
   4
   5 / {
   6         model = "SolidRun Clearfog GTR S4";
   7 };
   8
   9 &sfp0 {
  10         tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
  11 };
  12
  13 &mdio {
  14         switch0: ethernet-switch@4 {
  15                 compatible = "marvell,mv88e6085";
  16                 reg = <4>;
  17                 pinctrl-names = "default";
  18                 pinctrl-0 = <&cf_gtr_switch_reset_pins>;
  19                 reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
  20
  21                 ethernet-ports {
  22                         #address-cells = <1>;
  23                         #size-cells = <0>;
  24
  25                         ethernet-port@1 {
  26                                 reg = <1>;
  27                                 label = "lan2";
  28                                 phy-handle = <&switch0phy0>;
  29                         };
  30
  31                         ethernet-port@2 {
  32                                 reg = <2>;
  33                                 label = "lan1";
  34                                 phy-handle = <&switch0phy1>;
  35                         };
  36
  37                         ethernet-port@3 {
  38                                 reg = <3>;
  39                                 label = "lan4";
  40                                 phy-handle = <&switch0phy2>;
  41                         };
  42
  43                         ethernet-port@4 {
  44                                 reg = <4>;
  45                                 label = "lan3";
  46                                 phy-handle = <&switch0phy3>;
  47                         };
  48
  49                         ethernet-port@5 {
  50                                 reg = <5>;
  51                                 phy-mode = "2500base-x";
  52                                 ethernet = <&eth1>;
  53
  54                                 fixed-link {
  55                                         speed = <2500>;
  56                                         full-duplex;
  57                                 };
  58                         };
  59
  60                 };
  61
  62                 mdio {
  63                         #address-cells = <1>;
  64                         #size-cells = <0>;
  65
  66                         switch0phy0: ethernet-phy@11 {
  67                                 reg = <0x11>;
  68                         };
  69
  70                         switch0phy1: ethernet-phy@12 {
  71                                 reg = <0x12>;
  72                         };
  73
  74                         switch0phy2: ethernet-phy@13 {
  75                                 reg = <0x13>;
  76                         };
  77
  78                         switch0phy3: ethernet-phy@14 {
  79                                 reg = <0x14>;
  80                         };
  81                 };
  82
  83         };
  84 };