Merge tag 'csky-for-linus-4.20-fixup-dtb' of https://github.com/c-sky/csky-linux
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx7s.dtsi
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG
5
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx7d-pinfunc.h"
12
13 / {
14         #address-cells = <1>;
15         #size-cells = <1>;
16         /*
17          * The decompressor and also some bootloaders rely on a
18          * pre-existing /chosen node to be available to insert the
19          * command line and merge other ATAGS info.
20          * Also for U-Boot there must be a pre-existing /memory node.
21          */
22         chosen {};
23         memory { device_type = "memory"; };
24
25         aliases {
26                 gpio0 = &gpio1;
27                 gpio1 = &gpio2;
28                 gpio2 = &gpio3;
29                 gpio3 = &gpio4;
30                 gpio4 = &gpio5;
31                 gpio5 = &gpio6;
32                 gpio6 = &gpio7;
33                 i2c0 = &i2c1;
34                 i2c1 = &i2c2;
35                 i2c2 = &i2c3;
36                 i2c3 = &i2c4;
37                 mmc0 = &usdhc1;
38                 mmc1 = &usdhc2;
39                 mmc2 = &usdhc3;
40                 serial0 = &uart1;
41                 serial1 = &uart2;
42                 serial2 = &uart3;
43                 serial3 = &uart4;
44                 serial4 = &uart5;
45                 serial5 = &uart6;
46                 serial6 = &uart7;
47                 spi0 = &ecspi1;
48                 spi1 = &ecspi2;
49                 spi2 = &ecspi3;
50                 spi3 = &ecspi4;
51         };
52
53         cpus {
54                 #address-cells = <1>;
55                 #size-cells = <0>;
56
57                 idle-states {
58                         entry-method = "psci";
59
60                         cpu_sleep_wait: cpu-sleep-wait {
61                                 compatible = "arm,idle-state";
62                                 arm,psci-suspend-param = <0x0010000>;
63                                 local-timer-stop;
64                                 entry-latency-us = <100>;
65                                 exit-latency-us = <50>;
66                                 min-residency-us = <1000>;
67                         };
68                 };
69
70                 cpu0: cpu@0 {
71                         compatible = "arm,cortex-a7";
72                         device_type = "cpu";
73                         reg = <0>;
74                         clock-frequency = <792000000>;
75                         clock-latency = <61036>; /* two CLK32 periods */
76                         clocks = <&clks IMX7D_CLK_ARM>;
77                         cpu-idle-states = <&cpu_sleep_wait>;
78                 };
79         };
80
81         ckil: clock-cki {
82                 compatible = "fixed-clock";
83                 #clock-cells = <0>;
84                 clock-frequency = <32768>;
85                 clock-output-names = "ckil";
86         };
87
88         osc: clock-osc {
89                 compatible = "fixed-clock";
90                 #clock-cells = <0>;
91                 clock-frequency = <24000000>;
92                 clock-output-names = "osc";
93         };
94
95         usbphynop1: usbphynop1 {
96                 compatible = "usb-nop-xceiv";
97                 clocks = <&clks IMX7D_USB_PHY1_CLK>;
98                 clock-names = "main_clk";
99                 #phy-cells = <0>;
100         };
101
102         usbphynop3: usbphynop3 {
103                 compatible = "usb-nop-xceiv";
104                 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
105                 clock-names = "main_clk";
106                 #phy-cells = <0>;
107         };
108
109         pmu {
110                 compatible = "arm,cortex-a7-pmu";
111                 interrupt-parent = <&gpc>;
112                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
113                 interrupt-affinity = <&cpu0>;
114         };
115
116         replicator {
117                 /*
118                  * non-configurable replicators don't show up on the
119                  * AMBA bus.  As such no need to add "arm,primecell"
120                  */
121                 compatible = "arm,coresight-replicator";
122
123                 out-ports {
124                         #address-cells = <1>;
125                         #size-cells = <0>;
126                                 /* replicator output ports */
127                         port@0 {
128                                 reg = <0>;
129                                 replicator_out_port0: endpoint {
130                                         remote-endpoint = <&tpiu_in_port>;
131                                 };
132                         };
133
134                         port@1 {
135                                 reg = <1>;
136                                 replicator_out_port1: endpoint {
137                                         remote-endpoint = <&etr_in_port>;
138                                 };
139                         };
140                 };
141
142                 in-ports {
143                         port {
144                                 replicator_in_port0: endpoint {
145                                         remote-endpoint = <&etf_out_port>;
146                                 };
147                         };
148                 };
149         };
150
151         tempmon: tempmon {
152                 compatible = "fsl,imx7d-tempmon";
153                 interrupt-parent = <&gpc>;
154                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
155                 fsl,tempmon =<&anatop>;
156                 nvmem-cells = <&tempmon_calib>,
157                         <&tempmon_temp_grade>;
158                 nvmem-cell-names = "calib", "temp_grade";
159                 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
160         };
161
162         timer {
163                 compatible = "arm,armv7-timer";
164                 interrupt-parent = <&intc>;
165                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
166                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
169         };
170
171         soc {
172                 #address-cells = <1>;
173                 #size-cells = <1>;
174                 compatible = "simple-bus";
175                 interrupt-parent = <&gpc>;
176                 ranges;
177
178                 funnel@30041000 {
179                         compatible = "arm,coresight-funnel", "arm,primecell";
180                         reg = <0x30041000 0x1000>;
181                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
182                         clock-names = "apb_pclk";
183
184                         ca_funnel_in_ports: in-ports {
185                                 port {
186                                         ca_funnel_in_port0: endpoint {
187                                                 remote-endpoint = <&etm0_out_port>;
188                                         };
189                                 };
190
191                                 /* the other input ports are not connect to anything */
192                         };
193
194                         out-ports {
195                                 port {
196                                         ca_funnel_out_port0: endpoint {
197                                                 remote-endpoint = <&hugo_funnel_in_port0>;
198                                         };
199                                 };
200
201                         };
202                 };
203
204                 etm@3007c000 {
205                         compatible = "arm,coresight-etm3x", "arm,primecell";
206                         reg = <0x3007c000 0x1000>;
207                         cpu = <&cpu0>;
208                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
209                         clock-names = "apb_pclk";
210
211                         out-ports {
212                                 port {
213                                         etm0_out_port: endpoint {
214                                                 remote-endpoint = <&ca_funnel_in_port0>;
215                                         };
216                                 };
217                         };
218                 };
219
220                 funnel@30083000 {
221                         compatible = "arm,coresight-funnel", "arm,primecell";
222                         reg = <0x30083000 0x1000>;
223                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
224                         clock-names = "apb_pclk";
225
226                         in-ports {
227                                 #address-cells = <1>;
228                                 #size-cells = <0>;
229
230                                 port@0 {
231                                         reg = <0>;
232                                         hugo_funnel_in_port0: endpoint {
233                                                 remote-endpoint = <&ca_funnel_out_port0>;
234                                         };
235                                 };
236
237                                 port@1 {
238                                         reg = <1>;
239                                         hugo_funnel_in_port1: endpoint {
240                                                 /* M4 input */
241                                         };
242                                 };
243                                 /* the other input ports are not connect to anything */
244                         };
245
246                         out-ports {
247                                 port {
248                                         hugo_funnel_out_port0: endpoint {
249                                                 remote-endpoint = <&etf_in_port>;
250                                         };
251                                 };
252                         };
253                 };
254
255                 etf@30084000 {
256                         compatible = "arm,coresight-tmc", "arm,primecell";
257                         reg = <0x30084000 0x1000>;
258                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
259                         clock-names = "apb_pclk";
260
261                         in-ports {
262                                 port {
263                                         etf_in_port: endpoint {
264                                                 remote-endpoint = <&hugo_funnel_out_port0>;
265                                         };
266                                 };
267                         };
268
269                         out-ports {
270                                 port {
271                                         etf_out_port: endpoint {
272                                                 remote-endpoint = <&replicator_in_port0>;
273                                         };
274                                 };
275                         };
276                 };
277
278                 etr@30086000 {
279                         compatible = "arm,coresight-tmc", "arm,primecell";
280                         reg = <0x30086000 0x1000>;
281                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
282                         clock-names = "apb_pclk";
283
284                         in-ports {
285                                 port {
286                                         etr_in_port: endpoint {
287                                                 remote-endpoint = <&replicator_out_port1>;
288                                         };
289                                 };
290                         };
291                 };
292
293                 tpiu@30087000 {
294                         compatible = "arm,coresight-tpiu", "arm,primecell";
295                         reg = <0x30087000 0x1000>;
296                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
297                         clock-names = "apb_pclk";
298
299                         in-ports {
300                                 port {
301                                         tpiu_in_port: endpoint {
302                                                 remote-endpoint = <&replicator_out_port0>;
303                                         };
304                                 };
305                         };
306                 };
307
308                 intc: interrupt-controller@31001000 {
309                         compatible = "arm,cortex-a7-gic";
310                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
311                         #interrupt-cells = <3>;
312                         interrupt-controller;
313                         interrupt-parent = <&intc>;
314                         reg = <0x31001000 0x1000>,
315                               <0x31002000 0x2000>,
316                               <0x31004000 0x2000>,
317                               <0x31006000 0x2000>;
318                 };
319
320                 aips1: aips-bus@30000000 {
321                         compatible = "fsl,aips-bus", "simple-bus";
322                         #address-cells = <1>;
323                         #size-cells = <1>;
324                         reg = <0x30000000 0x400000>;
325                         ranges;
326
327                         gpio1: gpio@30200000 {
328                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
329                                 reg = <0x30200000 0x10000>;
330                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
331                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
332                                 gpio-controller;
333                                 #gpio-cells = <2>;
334                                 interrupt-controller;
335                                 #interrupt-cells = <2>;
336                                 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
337                         };
338
339                         gpio2: gpio@30210000 {
340                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
341                                 reg = <0x30210000 0x10000>;
342                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
343                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
344                                 gpio-controller;
345                                 #gpio-cells = <2>;
346                                 interrupt-controller;
347                                 #interrupt-cells = <2>;
348                                 gpio-ranges = <&iomuxc 0 13 32>;
349                         };
350
351                         gpio3: gpio@30220000 {
352                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
353                                 reg = <0x30220000 0x10000>;
354                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
355                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
356                                 gpio-controller;
357                                 #gpio-cells = <2>;
358                                 interrupt-controller;
359                                 #interrupt-cells = <2>;
360                                 gpio-ranges = <&iomuxc 0 45 29>;
361                         };
362
363                         gpio4: gpio@30230000 {
364                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
365                                 reg = <0x30230000 0x10000>;
366                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
367                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
368                                 gpio-controller;
369                                 #gpio-cells = <2>;
370                                 interrupt-controller;
371                                 #interrupt-cells = <2>;
372                                 gpio-ranges = <&iomuxc 0 74 24>;
373                         };
374
375                         gpio5: gpio@30240000 {
376                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
377                                 reg = <0x30240000 0x10000>;
378                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
379                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
380                                 gpio-controller;
381                                 #gpio-cells = <2>;
382                                 interrupt-controller;
383                                 #interrupt-cells = <2>;
384                                 gpio-ranges = <&iomuxc 0 98 18>;
385                         };
386
387                         gpio6: gpio@30250000 {
388                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
389                                 reg = <0x30250000 0x10000>;
390                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
391                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
392                                 gpio-controller;
393                                 #gpio-cells = <2>;
394                                 interrupt-controller;
395                                 #interrupt-cells = <2>;
396                                 gpio-ranges = <&iomuxc 0 116 23>;
397                         };
398
399                         gpio7: gpio@30260000 {
400                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
401                                 reg = <0x30260000 0x10000>;
402                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
403                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
404                                 gpio-controller;
405                                 #gpio-cells = <2>;
406                                 interrupt-controller;
407                                 #interrupt-cells = <2>;
408                                 gpio-ranges = <&iomuxc 0 139 16>;
409                         };
410
411                         wdog1: wdog@30280000 {
412                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
413                                 reg = <0x30280000 0x10000>;
414                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
415                                 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
416                         };
417
418                         wdog2: wdog@30290000 {
419                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
420                                 reg = <0x30290000 0x10000>;
421                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
422                                 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
423                                 status = "disabled";
424                         };
425
426                         wdog3: wdog@302a0000 {
427                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
428                                 reg = <0x302a0000 0x10000>;
429                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
430                                 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
431                                 status = "disabled";
432                         };
433
434                         wdog4: wdog@302b0000 {
435                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
436                                 reg = <0x302b0000 0x10000>;
437                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
438                                 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
439                                 status = "disabled";
440                         };
441
442                         iomuxc_lpsr: iomuxc-lpsr@302c0000 {
443                                 compatible = "fsl,imx7d-iomuxc-lpsr";
444                                 reg = <0x302c0000 0x10000>;
445                                 fsl,input-sel = <&iomuxc>;
446                         };
447
448                         gpt1: gpt@302d0000 {
449                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
450                                 reg = <0x302d0000 0x10000>;
451                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
452                                 clocks = <&clks IMX7D_CLK_DUMMY>,
453                                          <&clks IMX7D_GPT1_ROOT_CLK>;
454                                 clock-names = "ipg", "per";
455                         };
456
457                         gpt2: gpt@302e0000 {
458                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
459                                 reg = <0x302e0000 0x10000>;
460                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
461                                 clocks = <&clks IMX7D_CLK_DUMMY>,
462                                          <&clks IMX7D_GPT2_ROOT_CLK>;
463                                 clock-names = "ipg", "per";
464                                 status = "disabled";
465                         };
466
467                         gpt3: gpt@302f0000 {
468                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
469                                 reg = <0x302f0000 0x10000>;
470                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
471                                 clocks = <&clks IMX7D_CLK_DUMMY>,
472                                          <&clks IMX7D_GPT3_ROOT_CLK>;
473                                 clock-names = "ipg", "per";
474                                 status = "disabled";
475                         };
476
477                         gpt4: gpt@30300000 {
478                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
479                                 reg = <0x30300000 0x10000>;
480                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
481                                 clocks = <&clks IMX7D_CLK_DUMMY>,
482                                          <&clks IMX7D_GPT4_ROOT_CLK>;
483                                 clock-names = "ipg", "per";
484                                 status = "disabled";
485                         };
486
487                         kpp: kpp@30320000 {
488                                 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
489                                 reg = <0x30320000 0x10000>;
490                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
491                                 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
492                                 status = "disabled";
493                         };
494
495                         iomuxc: iomuxc@30330000 {
496                                 compatible = "fsl,imx7d-iomuxc";
497                                 reg = <0x30330000 0x10000>;
498                         };
499
500                         gpr: iomuxc-gpr@30340000 {
501                                 compatible = "fsl,imx7d-iomuxc-gpr",
502                                         "fsl,imx6q-iomuxc-gpr", "syscon";
503                                 reg = <0x30340000 0x10000>;
504                         };
505
506                         ocotp: ocotp-ctrl@30350000 {
507                                 #address-cells = <1>;
508                                 #size-cells = <1>;
509                                 compatible = "fsl,imx7d-ocotp", "syscon";
510                                 reg = <0x30350000 0x10000>;
511                                 clocks = <&clks IMX7D_OCOTP_CLK>;
512
513                                 tempmon_calib: calib@3c {
514                                         reg = <0x3c 0x4>;
515                                 };
516
517                                 tempmon_temp_grade: temp-grade@10 {
518                                         reg = <0x10 0x4>;
519                                 };
520                         };
521
522                         anatop: anatop@30360000 {
523                                 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
524                                         "syscon", "simple-bus";
525                                 reg = <0x30360000 0x10000>;
526                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
527                                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
528
529                                 reg_1p0d: regulator-vdd1p0d {
530                                         compatible = "fsl,anatop-regulator";
531                                         regulator-name = "vdd1p0d";
532                                         regulator-min-microvolt = <800000>;
533                                         regulator-max-microvolt = <1200000>;
534                                         anatop-reg-offset = <0x210>;
535                                         anatop-vol-bit-shift = <8>;
536                                         anatop-vol-bit-width = <5>;
537                                         anatop-min-bit-val = <8>;
538                                         anatop-min-voltage = <800000>;
539                                         anatop-max-voltage = <1200000>;
540                                         anatop-enable-bit = <0>;
541                                 };
542
543                                 reg_1p2: regulator-vdd1p2 {
544                                         compatible = "fsl,anatop-regulator";
545                                         regulator-name = "vdd1p2";
546                                         regulator-min-microvolt = <1100000>;
547                                         regulator-max-microvolt = <1300000>;
548                                         anatop-reg-offset = <0x220>;
549                                         anatop-vol-bit-shift = <8>;
550                                         anatop-vol-bit-width = <5>;
551                                         anatop-min-bit-val = <0x14>;
552                                         anatop-min-voltage = <1100000>;
553                                         anatop-max-voltage = <1300000>;
554                                         anatop-enable-bit = <0>;
555                                 };
556                         };
557
558                         snvs: snvs@30370000 {
559                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
560                                 reg = <0x30370000 0x10000>;
561
562                                 snvs_rtc: snvs-rtc-lp {
563                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
564                                         regmap = <&snvs>;
565                                         offset = <0x34>;
566                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
567                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
568                                         clocks = <&clks IMX7D_SNVS_CLK>;
569                                         clock-names = "snvs-rtc";
570                                 };
571
572                                 snvs_pwrkey: snvs-powerkey {
573                                         compatible = "fsl,sec-v4.0-pwrkey";
574                                         regmap = <&snvs>;
575                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
576                                         linux,keycode = <KEY_POWER>;
577                                         wakeup-source;
578                                 };
579                         };
580
581                         clks: ccm@30380000 {
582                                 compatible = "fsl,imx7d-ccm";
583                                 reg = <0x30380000 0x10000>;
584                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
585                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
586                                 #clock-cells = <1>;
587                                 clocks = <&ckil>, <&osc>;
588                                 clock-names = "ckil", "osc";
589                         };
590
591                         src: src@30390000 {
592                                 compatible = "fsl,imx7d-src", "syscon";
593                                 reg = <0x30390000 0x10000>;
594                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
595                                 #reset-cells = <1>;
596                         };
597
598                         gpc: gpc@303a0000 {
599                                 compatible = "fsl,imx7d-gpc";
600                                 reg = <0x303a0000 0x10000>;
601                                 interrupt-controller;
602                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
603                                 #interrupt-cells = <3>;
604                                 interrupt-parent = <&intc>;
605                                 #power-domain-cells = <1>;
606
607                                 pgc {
608                                         #address-cells = <1>;
609                                         #size-cells = <0>;
610
611                                         pgc_pcie_phy: pgc-power-domain@1 {
612                                                 #power-domain-cells = <0>;
613                                                 reg = <1>;
614                                                 power-supply = <&reg_1p0d>;
615                                         };
616                                 };
617                         };
618                 };
619
620                 aips2: aips-bus@30400000 {
621                         compatible = "fsl,aips-bus", "simple-bus";
622                         #address-cells = <1>;
623                         #size-cells = <1>;
624                         reg = <0x30400000 0x400000>;
625                         ranges;
626
627                         adc1: adc@30610000 {
628                                 compatible = "fsl,imx7d-adc";
629                                 reg = <0x30610000 0x10000>;
630                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
631                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
632                                 clock-names = "adc";
633                                 status = "disabled";
634                         };
635
636                         adc2: adc@30620000 {
637                                 compatible = "fsl,imx7d-adc";
638                                 reg = <0x30620000 0x10000>;
639                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
640                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
641                                 clock-names = "adc";
642                                 status = "disabled";
643                         };
644
645                         ecspi4: spi@30630000 {
646                                 #address-cells = <1>;
647                                 #size-cells = <0>;
648                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
649                                 reg = <0x30630000 0x10000>;
650                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
651                                 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
652                                         <&clks IMX7D_ECSPI4_ROOT_CLK>;
653                                 clock-names = "ipg", "per";
654                                 status = "disabled";
655                         };
656
657                         pwm1: pwm@30660000 {
658                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
659                                 reg = <0x30660000 0x10000>;
660                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
661                                 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
662                                          <&clks IMX7D_PWM1_ROOT_CLK>;
663                                 clock-names = "ipg", "per";
664                                 #pwm-cells = <3>;
665                                 status = "disabled";
666                         };
667
668                         pwm2: pwm@30670000 {
669                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
670                                 reg = <0x30670000 0x10000>;
671                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
672                                 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
673                                          <&clks IMX7D_PWM2_ROOT_CLK>;
674                                 clock-names = "ipg", "per";
675                                 #pwm-cells = <3>;
676                                 status = "disabled";
677                         };
678
679                         pwm3: pwm@30680000 {
680                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
681                                 reg = <0x30680000 0x10000>;
682                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
683                                 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
684                                          <&clks IMX7D_PWM3_ROOT_CLK>;
685                                 clock-names = "ipg", "per";
686                                 #pwm-cells = <3>;
687                                 status = "disabled";
688                         };
689
690                         pwm4: pwm@30690000 {
691                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
692                                 reg = <0x30690000 0x10000>;
693                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
694                                 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
695                                          <&clks IMX7D_PWM4_ROOT_CLK>;
696                                 clock-names = "ipg", "per";
697                                 #pwm-cells = <3>;
698                                 status = "disabled";
699                         };
700
701                         lcdif: lcdif@30730000 {
702                                 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
703                                 reg = <0x30730000 0x10000>;
704                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
705                                 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
706                                         <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
707                                 clock-names = "pix", "axi";
708                                 status = "disabled";
709                         };
710                 };
711
712                 aips3: aips-bus@30800000 {
713                         compatible = "fsl,aips-bus", "simple-bus";
714                         #address-cells = <1>;
715                         #size-cells = <1>;
716                         reg = <0x30800000 0x400000>;
717                         ranges;
718
719                         spba-bus@30800000 {
720                                 compatible = "fsl,spba-bus", "simple-bus";
721                                 #address-cells = <1>;
722                                 #size-cells = <1>;
723                                 reg = <0x30800000 0x100000>;
724                                 ranges;
725
726                                 ecspi1: spi@30820000 {
727                                         #address-cells = <1>;
728                                         #size-cells = <0>;
729                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
730                                         reg = <0x30820000 0x10000>;
731                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
732                                         clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
733                                                 <&clks IMX7D_ECSPI1_ROOT_CLK>;
734                                         clock-names = "ipg", "per";
735                                         status = "disabled";
736                                 };
737
738                                 ecspi2: spi@30830000 {
739                                         #address-cells = <1>;
740                                         #size-cells = <0>;
741                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
742                                         reg = <0x30830000 0x10000>;
743                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
744                                         clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
745                                                 <&clks IMX7D_ECSPI2_ROOT_CLK>;
746                                         clock-names = "ipg", "per";
747                                         status = "disabled";
748                                 };
749
750                                 ecspi3: spi@30840000 {
751                                         #address-cells = <1>;
752                                         #size-cells = <0>;
753                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
754                                         reg = <0x30840000 0x10000>;
755                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
756                                         clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
757                                                 <&clks IMX7D_ECSPI3_ROOT_CLK>;
758                                         clock-names = "ipg", "per";
759                                         status = "disabled";
760                                 };
761
762                                 uart1: serial@30860000 {
763                                         compatible = "fsl,imx7d-uart",
764                                                      "fsl,imx6q-uart";
765                                         reg = <0x30860000 0x10000>;
766                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
767                                         clocks = <&clks IMX7D_UART1_ROOT_CLK>,
768                                                 <&clks IMX7D_UART1_ROOT_CLK>;
769                                         clock-names = "ipg", "per";
770                                         status = "disabled";
771                                 };
772
773                                 uart2: serial@30890000 {
774                                         compatible = "fsl,imx7d-uart",
775                                                      "fsl,imx6q-uart";
776                                         reg = <0x30890000 0x10000>;
777                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
778                                         clocks = <&clks IMX7D_UART2_ROOT_CLK>,
779                                                 <&clks IMX7D_UART2_ROOT_CLK>;
780                                         clock-names = "ipg", "per";
781                                         status = "disabled";
782                                 };
783
784                                 uart3: serial@30880000 {
785                                         compatible = "fsl,imx7d-uart",
786                                                      "fsl,imx6q-uart";
787                                         reg = <0x30880000 0x10000>;
788                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
789                                         clocks = <&clks IMX7D_UART3_ROOT_CLK>,
790                                                 <&clks IMX7D_UART3_ROOT_CLK>;
791                                         clock-names = "ipg", "per";
792                                         status = "disabled";
793                                 };
794
795                                 sai1: sai@308a0000 {
796                                         #sound-dai-cells = <0>;
797                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
798                                         reg = <0x308a0000 0x10000>;
799                                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
800                                         clocks = <&clks IMX7D_SAI1_IPG_CLK>,
801                                                  <&clks IMX7D_SAI1_ROOT_CLK>,
802                                                  <&clks IMX7D_CLK_DUMMY>,
803                                                  <&clks IMX7D_CLK_DUMMY>;
804                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
805                                         dma-names = "rx", "tx";
806                                         dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
807                                         status = "disabled";
808                                 };
809
810                                 sai2: sai@308b0000 {
811                                         #sound-dai-cells = <0>;
812                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
813                                         reg = <0x308b0000 0x10000>;
814                                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
815                                         clocks = <&clks IMX7D_SAI2_IPG_CLK>,
816                                                  <&clks IMX7D_SAI2_ROOT_CLK>,
817                                                  <&clks IMX7D_CLK_DUMMY>,
818                                                  <&clks IMX7D_CLK_DUMMY>;
819                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
820                                         dma-names = "rx", "tx";
821                                         dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
822                                         status = "disabled";
823                                 };
824
825                                 sai3: sai@308c0000 {
826                                         #sound-dai-cells = <0>;
827                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
828                                         reg = <0x308c0000 0x10000>;
829                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
830                                         clocks = <&clks IMX7D_SAI3_IPG_CLK>,
831                                                  <&clks IMX7D_SAI3_ROOT_CLK>,
832                                                  <&clks IMX7D_CLK_DUMMY>,
833                                                  <&clks IMX7D_CLK_DUMMY>;
834                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
835                                         dma-names = "rx", "tx";
836                                         dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
837                                         status = "disabled";
838                                 };
839                         };
840
841                         crypto: caam@30900000 {
842                                 compatible = "fsl,sec-v4.0";
843                                 #address-cells = <1>;
844                                 #size-cells = <1>;
845                                 reg = <0x30900000 0x40000>;
846                                 ranges = <0 0x30900000 0x40000>;
847                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
848                                 clocks = <&clks IMX7D_CAAM_CLK>,
849                                          <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
850                                 clock-names = "ipg", "aclk";
851
852                                 sec_jr0: jr0@1000 {
853                                         compatible = "fsl,sec-v4.0-job-ring";
854                                         reg = <0x1000 0x1000>;
855                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
856                                 };
857
858                                 sec_jr1: jr1@2000 {
859                                         compatible = "fsl,sec-v4.0-job-ring";
860                                         reg = <0x2000 0x1000>;
861                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
862                                 };
863
864                                 sec_jr2: jr1@3000 {
865                                         compatible = "fsl,sec-v4.0-job-ring";
866                                         reg = <0x3000 0x1000>;
867                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
868                                 };
869                         };
870
871                         flexcan1: can@30a00000 {
872                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
873                                 reg = <0x30a00000 0x10000>;
874                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
875                                 clocks = <&clks IMX7D_CLK_DUMMY>,
876                                         <&clks IMX7D_CAN1_ROOT_CLK>;
877                                 clock-names = "ipg", "per";
878                                 status = "disabled";
879                         };
880
881                         flexcan2: can@30a10000 {
882                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
883                                 reg = <0x30a10000 0x10000>;
884                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
885                                 clocks = <&clks IMX7D_CLK_DUMMY>,
886                                         <&clks IMX7D_CAN2_ROOT_CLK>;
887                                 clock-names = "ipg", "per";
888                                 status = "disabled";
889                         };
890
891                         i2c1: i2c@30a20000 {
892                                 #address-cells = <1>;
893                                 #size-cells = <0>;
894                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
895                                 reg = <0x30a20000 0x10000>;
896                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
897                                 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
898                                 status = "disabled";
899                         };
900
901                         i2c2: i2c@30a30000 {
902                                 #address-cells = <1>;
903                                 #size-cells = <0>;
904                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
905                                 reg = <0x30a30000 0x10000>;
906                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
907                                 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
908                                 status = "disabled";
909                         };
910
911                         i2c3: i2c@30a40000 {
912                                 #address-cells = <1>;
913                                 #size-cells = <0>;
914                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
915                                 reg = <0x30a40000 0x10000>;
916                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
917                                 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
918                                 status = "disabled";
919                         };
920
921                         i2c4: i2c@30a50000 {
922                                 #address-cells = <1>;
923                                 #size-cells = <0>;
924                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
925                                 reg = <0x30a50000 0x10000>;
926                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
927                                 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
928                                 status = "disabled";
929                         };
930
931                         uart4: serial@30a60000 {
932                                 compatible = "fsl,imx7d-uart",
933                                              "fsl,imx6q-uart";
934                                 reg = <0x30a60000 0x10000>;
935                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
936                                 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
937                                         <&clks IMX7D_UART4_ROOT_CLK>;
938                                 clock-names = "ipg", "per";
939                                 status = "disabled";
940                         };
941
942                         uart5: serial@30a70000 {
943                                 compatible = "fsl,imx7d-uart",
944                                              "fsl,imx6q-uart";
945                                 reg = <0x30a70000 0x10000>;
946                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
947                                 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
948                                         <&clks IMX7D_UART5_ROOT_CLK>;
949                                 clock-names = "ipg", "per";
950                                 status = "disabled";
951                         };
952
953                         uart6: serial@30a80000 {
954                                 compatible = "fsl,imx7d-uart",
955                                              "fsl,imx6q-uart";
956                                 reg = <0x30a80000 0x10000>;
957                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
958                                 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
959                                         <&clks IMX7D_UART6_ROOT_CLK>;
960                                 clock-names = "ipg", "per";
961                                 status = "disabled";
962                         };
963
964                         uart7: serial@30a90000 {
965                                 compatible = "fsl,imx7d-uart",
966                                              "fsl,imx6q-uart";
967                                 reg = <0x30a90000 0x10000>;
968                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
969                                 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
970                                         <&clks IMX7D_UART7_ROOT_CLK>;
971                                 clock-names = "ipg", "per";
972                                 status = "disabled";
973                         };
974
975                         mu0a: mailbox@30aa0000 {
976                                 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
977                                 reg = <0x30aa0000 0x10000>;
978                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
979                                 clocks = <&clks IMX7D_MU_ROOT_CLK>;
980                                 #mbox-cells = <2>;
981                                 status = "disabled";
982                         };
983
984                         mu0b: mailbox@30ab0000 {
985                                 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
986                                 reg = <0x30ab0000 0x10000>;
987                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
988                                 clocks = <&clks IMX7D_MU_ROOT_CLK>;
989                                 #mbox-cells = <2>;
990                                 fsl,mu-side-b;
991                                 status = "disabled";
992                         };
993
994                         usbotg1: usb@30b10000 {
995                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
996                                 reg = <0x30b10000 0x200>;
997                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
998                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
999                                 fsl,usbphy = <&usbphynop1>;
1000                                 fsl,usbmisc = <&usbmisc1 0>;
1001                                 phy-clkgate-delay-us = <400>;
1002                                 status = "disabled";
1003                         };
1004
1005                         usbh: usb@30b30000 {
1006                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1007                                 reg = <0x30b30000 0x200>;
1008                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1009                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1010                                 fsl,usbphy = <&usbphynop3>;
1011                                 fsl,usbmisc = <&usbmisc3 0>;
1012                                 phy_type = "hsic";
1013                                 dr_mode = "host";
1014                                 phy-clkgate-delay-us = <400>;
1015                                 status = "disabled";
1016                         };
1017
1018                         usbmisc1: usbmisc@30b10200 {
1019                                 #index-cells = <1>;
1020                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1021                                 reg = <0x30b10200 0x200>;
1022                         };
1023
1024                         usbmisc3: usbmisc@30b30200 {
1025                                 #index-cells = <1>;
1026                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1027                                 reg = <0x30b30200 0x200>;
1028                         };
1029
1030                         usdhc1: usdhc@30b40000 {
1031                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1032                                 reg = <0x30b40000 0x10000>;
1033                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1034                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1035                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1036                                         <&clks IMX7D_USDHC1_ROOT_CLK>;
1037                                 clock-names = "ipg", "ahb", "per";
1038                                 bus-width = <4>;
1039                                 status = "disabled";
1040                         };
1041
1042                         usdhc2: usdhc@30b50000 {
1043                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1044                                 reg = <0x30b50000 0x10000>;
1045                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1046                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1047                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1048                                         <&clks IMX7D_USDHC2_ROOT_CLK>;
1049                                 clock-names = "ipg", "ahb", "per";
1050                                 bus-width = <4>;
1051                                 status = "disabled";
1052                         };
1053
1054                         usdhc3: usdhc@30b60000 {
1055                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1056                                 reg = <0x30b60000 0x10000>;
1057                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1058                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1059                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1060                                         <&clks IMX7D_USDHC3_ROOT_CLK>;
1061                                 clock-names = "ipg", "ahb", "per";
1062                                 bus-width = <4>;
1063                                 status = "disabled";
1064                         };
1065
1066                         sdma: sdma@30bd0000 {
1067                                 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1068                                 reg = <0x30bd0000 0x10000>;
1069                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1070                                 clocks = <&clks IMX7D_SDMA_CORE_CLK>,
1071                                          <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1072                                 clock-names = "ipg", "ahb";
1073                                 #dma-cells = <3>;
1074                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1075                         };
1076
1077                         fec1: ethernet@30be0000 {
1078                                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1079                                 reg = <0x30be0000 0x10000>;
1080                                 interrupt-names = "int0", "int1", "int2", "pps";
1081                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1082                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1083                                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1084                                         <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1085                                 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1086                                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1087                                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1088                                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1089                                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1090                                 clock-names = "ipg", "ahb", "ptp",
1091                                         "enet_clk_ref", "enet_out";
1092                                 fsl,num-tx-queues=<3>;
1093                                 fsl,num-rx-queues=<3>;
1094                                 status = "disabled";
1095                         };
1096                 };
1097
1098                 dma_apbh: dma-apbh@33000000 {
1099                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1100                         reg = <0x33000000 0x2000>;
1101                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1102                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1103                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1104                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1105                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1106                         #dma-cells = <1>;
1107                         dma-channels = <4>;
1108                         clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1109                 };
1110
1111                 gpmi: gpmi-nand@33002000{
1112                         compatible = "fsl,imx7d-gpmi-nand";
1113                         #address-cells = <1>;
1114                         #size-cells = <1>;
1115                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1116                         reg-names = "gpmi-nand", "bch";
1117                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1118                         interrupt-names = "bch";
1119                         clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1120                                 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1121                         clock-names = "gpmi_io", "gpmi_bch_apb";
1122                         dmas = <&dma_apbh 0>;
1123                         dma-names = "rx-tx";
1124                         status = "disabled";
1125                         assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1126                         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1127                 };
1128         };
1129 };