arch/arm/boot/dts/imx7s.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright 2015 Freescale Semiconductor, Inc.
   4 // Copyright 2016 Toradex AG
   5
   6 #include <dt-bindings/clock/imx7d-clock.h>
   7 #include <dt-bindings/power/imx7-power.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/reset/imx7-reset.h>
  12 #include "imx7d-pinfunc.h"
  13
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17         /*
  18          * The decompressor and also some bootloaders rely on a
  19          * pre-existing /chosen node to be available to insert the
  20          * command line and merge other ATAGS info.
  21          */
  22         chosen {};
  23
  24         aliases {
  25                 gpio0 = &gpio1;
  26                 gpio1 = &gpio2;
  27                 gpio2 = &gpio3;
  28                 gpio3 = &gpio4;
  29                 gpio4 = &gpio5;
  30                 gpio5 = &gpio6;
  31                 gpio6 = &gpio7;
  32                 i2c0 = &i2c1;
  33                 i2c1 = &i2c2;
  34                 i2c2 = &i2c3;
  35                 i2c3 = &i2c4;
  36                 mmc0 = &usdhc1;
  37                 mmc1 = &usdhc2;
  38                 mmc2 = &usdhc3;
  39                 serial0 = &uart1;
  40                 serial1 = &uart2;
  41                 serial2 = &uart3;
  42                 serial3 = &uart4;
  43                 serial4 = &uart5;
  44                 serial5 = &uart6;
  45                 serial6 = &uart7;
  46                 spi0 = &ecspi1;
  47                 spi1 = &ecspi2;
  48                 spi2 = &ecspi3;
  49                 spi3 = &ecspi4;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55
  56                 idle-states {
  57                         entry-method = "psci";
  58
  59                         cpu_sleep_wait: cpu-sleep-wait {
  60                                 compatible = "arm,idle-state";
  61                                 arm,psci-suspend-param = <0x0010000>;
  62                                 local-timer-stop;
  63                                 entry-latency-us = <100>;
  64                                 exit-latency-us = <50>;
  65                                 min-residency-us = <1000>;
  66                         };
  67                 };
  68
  69                 cpu0: cpu@0 {
  70                         compatible = "arm,cortex-a7";
  71                         device_type = "cpu";
  72                         reg = <0>;
  73                         clock-frequency = <792000000>;
  74                         clock-latency = <61036>; /* two CLK32 periods */
  75                         clocks = <&clks IMX7D_CLK_ARM>;
  76                         cpu-idle-states = <&cpu_sleep_wait>;
  77                 };
  78         };
  79
  80         ckil: clock-cki {
  81                 compatible = "fixed-clock";
  82                 #clock-cells = <0>;
  83                 clock-frequency = <32768>;
  84                 clock-output-names = "ckil";
  85         };
  86
  87         osc: clock-osc {
  88                 compatible = "fixed-clock";
  89                 #clock-cells = <0>;
  90                 clock-frequency = <24000000>;
  91                 clock-output-names = "osc";
  92         };
  93
  94         usbphynop1: usbphynop1 {
  95                 compatible = "usb-nop-xceiv";
  96                 clocks = <&clks IMX7D_USB_PHY1_CLK>;
  97                 clock-names = "main_clk";
  98                 #phy-cells = <0>;
  99         };
 100
 101         usbphynop3: usbphynop3 {
 102                 compatible = "usb-nop-xceiv";
 103                 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
 104                 clock-names = "main_clk";
 105                 #phy-cells = <0>;
 106         };
 107
 108         pmu {
 109                 compatible = "arm,cortex-a7-pmu";
 110                 interrupt-parent = <&gpc>;
 111                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 112                 interrupt-affinity = <&cpu0>;
 113         };
 114
 115         replicator {
 116                 /*
 117                  * non-configurable replicators don't show up on the
 118                  * AMBA bus.  As such no need to add "arm,primecell"
 119                  */
 120                 compatible = "arm,coresight-replicator";
 121
 122                 out-ports {
 123                         #address-cells = <1>;
 124                         #size-cells = <0>;
 125                                 /* replicator output ports */
 126                         port@0 {
 127                                 reg = <0>;
 128                                 replicator_out_port0: endpoint {
 129                                         remote-endpoint = <&tpiu_in_port>;
 130                                 };
 131                         };
 132
 133                         port@1 {
 134                                 reg = <1>;
 135                                 replicator_out_port1: endpoint {
 136                                         remote-endpoint = <&etr_in_port>;
 137                                 };
 138                         };
 139                 };
 140
 141                 in-ports {
 142                         port {
 143                                 replicator_in_port0: endpoint {
 144                                         remote-endpoint = <&etf_out_port>;
 145                                 };
 146                         };
 147                 };
 148         };
 149
 150         tempmon: tempmon {
 151                 compatible = "fsl,imx7d-tempmon";
 152                 interrupt-parent = <&gpc>;
 153                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 154                 fsl,tempmon =<&anatop>;
 155                 nvmem-cells = <&tempmon_calib>,
 156                         <&tempmon_temp_grade>;
 157                 nvmem-cell-names = "calib", "temp_grade";
 158                 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
 159         };
 160
 161         timer {
 162                 compatible = "arm,armv7-timer";
 163                 interrupt-parent = <&intc>;
 164                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 165                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 166                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 168         };
 169
 170         soc {
 171                 #address-cells = <1>;
 172                 #size-cells = <1>;
 173                 compatible = "simple-bus";
 174                 interrupt-parent = <&gpc>;
 175                 ranges;
 176
 177                 funnel@30041000 {
 178                         compatible = "arm,coresight-funnel", "arm,primecell";
 179                         reg = <0x30041000 0x1000>;
 180                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 181                         clock-names = "apb_pclk";
 182
 183                         ca_funnel_in_ports: in-ports {
 184                                 port {
 185                                         ca_funnel_in_port0: endpoint {
 186                                                 remote-endpoint = <&etm0_out_port>;
 187                                         };
 188                                 };
 189
 190                                 /* the other input ports are not connect to anything */
 191                         };
 192
 193                         out-ports {
 194                                 port {
 195                                         ca_funnel_out_port0: endpoint {
 196                                                 remote-endpoint = <&hugo_funnel_in_port0>;
 197                                         };
 198                                 };
 199
 200                         };
 201                 };
 202
 203                 etm@3007c000 {
 204                         compatible = "arm,coresight-etm3x", "arm,primecell";
 205                         reg = <0x3007c000 0x1000>;
 206                         cpu = <&cpu0>;
 207                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 208                         clock-names = "apb_pclk";
 209
 210                         out-ports {
 211                                 port {
 212                                         etm0_out_port: endpoint {
 213                                                 remote-endpoint = <&ca_funnel_in_port0>;
 214                                         };
 215                                 };
 216                         };
 217                 };
 218
 219                 funnel@30083000 {
 220                         compatible = "arm,coresight-funnel", "arm,primecell";
 221                         reg = <0x30083000 0x1000>;
 222                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 223                         clock-names = "apb_pclk";
 224
 225                         in-ports {
 226                                 #address-cells = <1>;
 227                                 #size-cells = <0>;
 228
 229                                 port@0 {
 230                                         reg = <0>;
 231                                         hugo_funnel_in_port0: endpoint {
 232                                                 remote-endpoint = <&ca_funnel_out_port0>;
 233                                         };
 234                                 };
 235
 236                                 port@1 {
 237                                         reg = <1>;
 238                                         hugo_funnel_in_port1: endpoint {
 239                                                 /* M4 input */
 240                                         };
 241                                 };
 242                                 /* the other input ports are not connect to anything */
 243                         };
 244
 245                         out-ports {
 246                                 port {
 247                                         hugo_funnel_out_port0: endpoint {
 248                                                 remote-endpoint = <&etf_in_port>;
 249                                         };
 250                                 };
 251                         };
 252                 };
 253
 254                 etf@30084000 {
 255                         compatible = "arm,coresight-tmc", "arm,primecell";
 256                         reg = <0x30084000 0x1000>;
 257                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 258                         clock-names = "apb_pclk";
 259
 260                         in-ports {
 261                                 port {
 262                                         etf_in_port: endpoint {
 263                                                 remote-endpoint = <&hugo_funnel_out_port0>;
 264                                         };
 265                                 };
 266                         };
 267
 268                         out-ports {
 269                                 port {
 270                                         etf_out_port: endpoint {
 271                                                 remote-endpoint = <&replicator_in_port0>;
 272                                         };
 273                                 };
 274                         };
 275                 };
 276
 277                 etr@30086000 {
 278                         compatible = "arm,coresight-tmc", "arm,primecell";
 279                         reg = <0x30086000 0x1000>;
 280                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 281                         clock-names = "apb_pclk";
 282
 283                         in-ports {
 284                                 port {
 285                                         etr_in_port: endpoint {
 286                                                 remote-endpoint = <&replicator_out_port1>;
 287                                         };
 288                                 };
 289                         };
 290                 };
 291
 292                 tpiu@30087000 {
 293                         compatible = "arm,coresight-tpiu", "arm,primecell";
 294                         reg = <0x30087000 0x1000>;
 295                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 296                         clock-names = "apb_pclk";
 297
 298                         in-ports {
 299                                 port {
 300                                         tpiu_in_port: endpoint {
 301                                                 remote-endpoint = <&replicator_out_port0>;
 302                                         };
 303                                 };
 304                         };
 305                 };
 306
 307                 intc: interrupt-controller@31001000 {
 308                         compatible = "arm,cortex-a7-gic";
 309                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 310                         #interrupt-cells = <3>;
 311                         interrupt-controller;
 312                         interrupt-parent = <&intc>;
 313                         reg = <0x31001000 0x1000>,
 314                               <0x31002000 0x2000>,
 315                               <0x31004000 0x2000>,
 316                               <0x31006000 0x2000>;
 317                 };
 318
 319                 aips1: aips-bus@30000000 {
 320                         compatible = "fsl,aips-bus", "simple-bus";
 321                         #address-cells = <1>;
 322                         #size-cells = <1>;
 323                         reg = <0x30000000 0x400000>;
 324                         ranges;
 325
 326                         gpio1: gpio@30200000 {
 327                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 328                                 reg = <0x30200000 0x10000>;
 329                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
 330                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
 331                                 gpio-controller;
 332                                 #gpio-cells = <2>;
 333                                 interrupt-controller;
 334                                 #interrupt-cells = <2>;
 335                                 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
 336                         };
 337
 338                         gpio2: gpio@30210000 {
 339                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 340                                 reg = <0x30210000 0x10000>;
 341                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 342                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 343                                 gpio-controller;
 344                                 #gpio-cells = <2>;
 345                                 interrupt-controller;
 346                                 #interrupt-cells = <2>;
 347                                 gpio-ranges = <&iomuxc 0 13 32>;
 348                         };
 349
 350                         gpio3: gpio@30220000 {
 351                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 352                                 reg = <0x30220000 0x10000>;
 353                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 354                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 355                                 gpio-controller;
 356                                 #gpio-cells = <2>;
 357                                 interrupt-controller;
 358                                 #interrupt-cells = <2>;
 359                                 gpio-ranges = <&iomuxc 0 45 29>;
 360                         };
 361
 362                         gpio4: gpio@30230000 {
 363                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 364                                 reg = <0x30230000 0x10000>;
 365                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 366                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 367                                 gpio-controller;
 368                                 #gpio-cells = <2>;
 369                                 interrupt-controller;
 370                                 #interrupt-cells = <2>;
 371                                 gpio-ranges = <&iomuxc 0 74 24>;
 372                         };
 373
 374                         gpio5: gpio@30240000 {
 375                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 376                                 reg = <0x30240000 0x10000>;
 377                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 378                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 379                                 gpio-controller;
 380                                 #gpio-cells = <2>;
 381                                 interrupt-controller;
 382                                 #interrupt-cells = <2>;
 383                                 gpio-ranges = <&iomuxc 0 98 18>;
 384                         };
 385
 386                         gpio6: gpio@30250000 {
 387                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 388                                 reg = <0x30250000 0x10000>;
 389                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 390                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 391                                 gpio-controller;
 392                                 #gpio-cells = <2>;
 393                                 interrupt-controller;
 394                                 #interrupt-cells = <2>;
 395                                 gpio-ranges = <&iomuxc 0 116 23>;
 396                         };
 397
 398                         gpio7: gpio@30260000 {
 399                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 400                                 reg = <0x30260000 0x10000>;
 401                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 402                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 403                                 gpio-controller;
 404                                 #gpio-cells = <2>;
 405                                 interrupt-controller;
 406                                 #interrupt-cells = <2>;
 407                                 gpio-ranges = <&iomuxc 0 139 16>;
 408                         };
 409
 410                         wdog1: wdog@30280000 {
 411                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 412                                 reg = <0x30280000 0x10000>;
 413                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 414                                 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
 415                         };
 416
 417                         wdog2: wdog@30290000 {
 418                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 419                                 reg = <0x30290000 0x10000>;
 420                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 421                                 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
 422                                 status = "disabled";
 423                         };
 424
 425                         wdog3: wdog@302a0000 {
 426                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 427                                 reg = <0x302a0000 0x10000>;
 428                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 429                                 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
 430                                 status = "disabled";
 431                         };
 432
 433                         wdog4: wdog@302b0000 {
 434                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 435                                 reg = <0x302b0000 0x10000>;
 436                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 437                                 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
 438                                 status = "disabled";
 439                         };
 440
 441                         iomuxc_lpsr: iomuxc-lpsr@302c0000 {
 442                                 compatible = "fsl,imx7d-iomuxc-lpsr";
 443                                 reg = <0x302c0000 0x10000>;
 444                                 fsl,input-sel = <&iomuxc>;
 445                         };
 446
 447                         gpt1: gpt@302d0000 {
 448                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 449                                 reg = <0x302d0000 0x10000>;
 450                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 451                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 452                                          <&clks IMX7D_GPT1_ROOT_CLK>;
 453                                 clock-names = "ipg", "per";
 454                         };
 455
 456                         gpt2: gpt@302e0000 {
 457                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 458                                 reg = <0x302e0000 0x10000>;
 459                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 460                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 461                                          <&clks IMX7D_GPT2_ROOT_CLK>;
 462                                 clock-names = "ipg", "per";
 463                                 status = "disabled";
 464                         };
 465
 466                         gpt3: gpt@302f0000 {
 467                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 468                                 reg = <0x302f0000 0x10000>;
 469                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 470                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 471                                          <&clks IMX7D_GPT3_ROOT_CLK>;
 472                                 clock-names = "ipg", "per";
 473                                 status = "disabled";
 474                         };
 475
 476                         gpt4: gpt@30300000 {
 477                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 478                                 reg = <0x30300000 0x10000>;
 479                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 480                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 481                                          <&clks IMX7D_GPT4_ROOT_CLK>;
 482                                 clock-names = "ipg", "per";
 483                                 status = "disabled";
 484                         };
 485
 486                         kpp: kpp@30320000 {
 487                                 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
 488                                 reg = <0x30320000 0x10000>;
 489                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 490                                 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
 491                                 status = "disabled";
 492                         };
 493
 494                         iomuxc: iomuxc@30330000 {
 495                                 compatible = "fsl,imx7d-iomuxc";
 496                                 reg = <0x30330000 0x10000>;
 497                         };
 498
 499                         gpr: iomuxc-gpr@30340000 {
 500                                 compatible = "fsl,imx7d-iomuxc-gpr",
 501                                         "fsl,imx6q-iomuxc-gpr", "syscon",
 502                                         "simple-mfd";
 503                                 reg = <0x30340000 0x10000>;
 504
 505                                 mux: mux-controller {
 506                                         compatible = "mmio-mux";
 507                                         #mux-control-cells = <0>;
 508                                         mux-reg-masks = <0x14 0x00000010>;
 509                                 };
 510
 511                                 video_mux: csi-mux {
 512                                         compatible = "video-mux";
 513                                         mux-controls = <&mux 0>;
 514                                         #address-cells = <1>;
 515                                         #size-cells = <0>;
 516                                         status = "disabled";
 517
 518                                         port@0 {
 519                                                 reg = <0>;
 520                                         };
 521
 522                                         port@1 {
 523                                                 reg = <1>;
 524
 525                                                 csi_mux_from_mipi_vc0: endpoint {
 526                                                         remote-endpoint = <&mipi_vc0_to_csi_mux>;
 527                                                 };
 528                                         };
 529
 530                                         port@2 {
 531                                                 reg = <2>;
 532
 533                                                 csi_mux_to_csi: endpoint {
 534                                                         remote-endpoint = <&csi_from_csi_mux>;
 535                                                 };
 536                                         };
 537                                 };
 538                         };
 539
 540                         ocotp: ocotp-ctrl@30350000 {
 541                                 #address-cells = <1>;
 542                                 #size-cells = <1>;
 543                                 compatible = "fsl,imx7d-ocotp", "syscon";
 544                                 reg = <0x30350000 0x10000>;
 545                                 clocks = <&clks IMX7D_OCOTP_CLK>;
 546
 547                                 tempmon_calib: calib@3c {
 548                                         reg = <0x3c 0x4>;
 549                                 };
 550
 551                                 tempmon_temp_grade: temp-grade@10 {
 552                                         reg = <0x10 0x4>;
 553                                 };
 554                         };
 555
 556                         anatop: anatop@30360000 {
 557                                 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
 558                                         "syscon", "simple-bus";
 559                                 reg = <0x30360000 0x10000>;
 560                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 561                                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 562
 563                                 reg_1p0d: regulator-vdd1p0d {
 564                                         compatible = "fsl,anatop-regulator";
 565                                         regulator-name = "vdd1p0d";
 566                                         regulator-min-microvolt = <800000>;
 567                                         regulator-max-microvolt = <1200000>;
 568                                         anatop-reg-offset = <0x210>;
 569                                         anatop-vol-bit-shift = <8>;
 570                                         anatop-vol-bit-width = <5>;
 571                                         anatop-min-bit-val = <8>;
 572                                         anatop-min-voltage = <800000>;
 573                                         anatop-max-voltage = <1200000>;
 574                                         anatop-enable-bit = <0>;
 575                                 };
 576
 577                                 reg_1p2: regulator-vdd1p2 {
 578                                         compatible = "fsl,anatop-regulator";
 579                                         regulator-name = "vdd1p2";
 580                                         regulator-min-microvolt = <1100000>;
 581                                         regulator-max-microvolt = <1300000>;
 582                                         anatop-reg-offset = <0x220>;
 583                                         anatop-vol-bit-shift = <8>;
 584                                         anatop-vol-bit-width = <5>;
 585                                         anatop-min-bit-val = <0x14>;
 586                                         anatop-min-voltage = <1100000>;
 587                                         anatop-max-voltage = <1300000>;
 588                                         anatop-enable-bit = <0>;
 589                                 };
 590                         };
 591
 592                         snvs: snvs@30370000 {
 593                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 594                                 reg = <0x30370000 0x10000>;
 595
 596                                 snvs_rtc: snvs-rtc-lp {
 597                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 598                                         regmap = <&snvs>;
 599                                         offset = <0x34>;
 600                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 601                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 602                                         clocks = <&clks IMX7D_SNVS_CLK>;
 603                                         clock-names = "snvs-rtc";
 604                                 };
 605
 606                                 snvs_pwrkey: snvs-powerkey {
 607                                         compatible = "fsl,sec-v4.0-pwrkey";
 608                                         regmap = <&snvs>;
 609                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 610                                         linux,keycode = <KEY_POWER>;
 611                                         wakeup-source;
 612                                 };
 613                         };
 614
 615                         clks: ccm@30380000 {
 616                                 compatible = "fsl,imx7d-ccm";
 617                                 reg = <0x30380000 0x10000>;
 618                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 619                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 620                                 #clock-cells = <1>;
 621                                 clocks = <&ckil>, <&osc>;
 622                                 clock-names = "ckil", "osc";
 623                         };
 624
 625                         src: src@30390000 {
 626                                 compatible = "fsl,imx7d-src", "syscon";
 627                                 reg = <0x30390000 0x10000>;
 628                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 629                                 #reset-cells = <1>;
 630                         };
 631
 632                         gpc: gpc@303a0000 {
 633                                 compatible = "fsl,imx7d-gpc";
 634                                 reg = <0x303a0000 0x10000>;
 635                                 interrupt-controller;
 636                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 637                                 #interrupt-cells = <3>;
 638                                 interrupt-parent = <&intc>;
 639                                 #power-domain-cells = <1>;
 640
 641                                 pgc {
 642                                         #address-cells = <1>;
 643                                         #size-cells = <0>;
 644
 645                                         pgc_mipi_phy: power-domain@0 {
 646                                                 #power-domain-cells = <0>;
 647                                                 reg = <0>;
 648                                                 power-supply = <&reg_1p0d>;
 649                                         };
 650
 651                                         pgc_pcie_phy: power-domain@1 {
 652                                                 #power-domain-cells = <0>;
 653                                                 reg = <1>;
 654                                                 power-supply = <&reg_1p0d>;
 655                                         };
 656                                 };
 657                         };
 658                 };
 659
 660                 aips2: aips-bus@30400000 {
 661                         compatible = "fsl,aips-bus", "simple-bus";
 662                         #address-cells = <1>;
 663                         #size-cells = <1>;
 664                         reg = <0x30400000 0x400000>;
 665                         ranges;
 666
 667                         adc1: adc@30610000 {
 668                                 compatible = "fsl,imx7d-adc";
 669                                 reg = <0x30610000 0x10000>;
 670                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 671                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 672                                 clock-names = "adc";
 673                                 #io-channel-cells = <1>;
 674                                 status = "disabled";
 675                         };
 676
 677                         adc2: adc@30620000 {
 678                                 compatible = "fsl,imx7d-adc";
 679                                 reg = <0x30620000 0x10000>;
 680                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 681                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 682                                 clock-names = "adc";
 683                                 #io-channel-cells = <1>;
 684                                 status = "disabled";
 685                         };
 686
 687                         ecspi4: spi@30630000 {
 688                                 #address-cells = <1>;
 689                                 #size-cells = <0>;
 690                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 691                                 reg = <0x30630000 0x10000>;
 692                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 693                                 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
 694                                         <&clks IMX7D_ECSPI4_ROOT_CLK>;
 695                                 clock-names = "ipg", "per";
 696                                 status = "disabled";
 697                         };
 698
 699                         pwm1: pwm@30660000 {
 700                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 701                                 reg = <0x30660000 0x10000>;
 702                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 703                                 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
 704                                          <&clks IMX7D_PWM1_ROOT_CLK>;
 705                                 clock-names = "ipg", "per";
 706                                 #pwm-cells = <3>;
 707                                 status = "disabled";
 708                         };
 709
 710                         pwm2: pwm@30670000 {
 711                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 712                                 reg = <0x30670000 0x10000>;
 713                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 714                                 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
 715                                          <&clks IMX7D_PWM2_ROOT_CLK>;
 716                                 clock-names = "ipg", "per";
 717                                 #pwm-cells = <3>;
 718                                 status = "disabled";
 719                         };
 720
 721                         pwm3: pwm@30680000 {
 722                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 723                                 reg = <0x30680000 0x10000>;
 724                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 725                                 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
 726                                          <&clks IMX7D_PWM3_ROOT_CLK>;
 727                                 clock-names = "ipg", "per";
 728                                 #pwm-cells = <3>;
 729                                 status = "disabled";
 730                         };
 731
 732                         pwm4: pwm@30690000 {
 733                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 734                                 reg = <0x30690000 0x10000>;
 735                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 736                                 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
 737                                          <&clks IMX7D_PWM4_ROOT_CLK>;
 738                                 clock-names = "ipg", "per";
 739                                 #pwm-cells = <3>;
 740                                 status = "disabled";
 741                         };
 742
 743                         csi: csi@30710000 {
 744                                 compatible = "fsl,imx7-csi";
 745                                 reg = <0x30710000 0x10000>;
 746                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 747                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 748                                          <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
 749                                          <&clks IMX7D_CLK_DUMMY>;
 750                                 clock-names = "axi", "mclk", "dcic";
 751                                 status = "disabled";
 752
 753                                 port {
 754                                         csi_from_csi_mux: endpoint {
 755                                                 remote-endpoint = <&csi_mux_to_csi>;
 756                                         };
 757                                 };
 758                         };
 759
 760                         lcdif: lcdif@30730000 {
 761                                 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
 762                                 reg = <0x30730000 0x10000>;
 763                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 764                                 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
 765                                         <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
 766                                 clock-names = "pix", "axi";
 767                                 status = "disabled";
 768                         };
 769
 770                         mipi_csi: mipi-csi@30750000 {
 771                                 compatible = "fsl,imx7-mipi-csi2";
 772                                 reg = <0x30750000 0x10000>;
 773                                 #address-cells = <1>;
 774                                 #size-cells = <0>;
 775                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 776                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
 777                                          <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
 778                                          <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
 779                                 clock-names = "pclk", "wrap", "phy";
 780                                 power-domains = <&pgc_mipi_phy>;
 781                                 phy-supply = <&reg_1p0d>;
 782                                 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
 783                                 reset-names = "mrst";
 784                                 status = "disabled";
 785
 786                                 port@0 {
 787                                         reg = <0>;
 788                                 };
 789
 790                                 port@1 {
 791                                         reg = <1>;
 792
 793                                         mipi_vc0_to_csi_mux: endpoint {
 794                                                 remote-endpoint = <&csi_mux_from_mipi_vc0>;
 795                                         };
 796                                 };
 797                         };
 798                 };
 799
 800                 aips3: aips-bus@30800000 {
 801                         compatible = "fsl,aips-bus", "simple-bus";
 802                         #address-cells = <1>;
 803                         #size-cells = <1>;
 804                         reg = <0x30800000 0x400000>;
 805                         ranges;
 806
 807                         spba-bus@30800000 {
 808                                 compatible = "fsl,spba-bus", "simple-bus";
 809                                 #address-cells = <1>;
 810                                 #size-cells = <1>;
 811                                 reg = <0x30800000 0x100000>;
 812                                 ranges;
 813
 814                                 ecspi1: spi@30820000 {
 815                                         #address-cells = <1>;
 816                                         #size-cells = <0>;
 817                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 818                                         reg = <0x30820000 0x10000>;
 819                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 820                                         clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
 821                                                 <&clks IMX7D_ECSPI1_ROOT_CLK>;
 822                                         clock-names = "ipg", "per";
 823                                         status = "disabled";
 824                                 };
 825
 826                                 ecspi2: spi@30830000 {
 827                                         #address-cells = <1>;
 828                                         #size-cells = <0>;
 829                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 830                                         reg = <0x30830000 0x10000>;
 831                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 832                                         clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
 833                                                 <&clks IMX7D_ECSPI2_ROOT_CLK>;
 834                                         clock-names = "ipg", "per";
 835                                         status = "disabled";
 836                                 };
 837
 838                                 ecspi3: spi@30840000 {
 839                                         #address-cells = <1>;
 840                                         #size-cells = <0>;
 841                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 842                                         reg = <0x30840000 0x10000>;
 843                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 844                                         clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
 845                                                 <&clks IMX7D_ECSPI3_ROOT_CLK>;
 846                                         clock-names = "ipg", "per";
 847                                         status = "disabled";
 848                                 };
 849
 850                                 uart1: serial@30860000 {
 851                                         compatible = "fsl,imx7d-uart",
 852                                                      "fsl,imx6q-uart";
 853                                         reg = <0x30860000 0x10000>;
 854                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 855                                         clocks = <&clks IMX7D_UART1_ROOT_CLK>,
 856                                                 <&clks IMX7D_UART1_ROOT_CLK>;
 857                                         clock-names = "ipg", "per";
 858                                         status = "disabled";
 859                                 };
 860
 861                                 uart2: serial@30890000 {
 862                                         compatible = "fsl,imx7d-uart",
 863                                                      "fsl,imx6q-uart";
 864                                         reg = <0x30890000 0x10000>;
 865                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 866                                         clocks = <&clks IMX7D_UART2_ROOT_CLK>,
 867                                                 <&clks IMX7D_UART2_ROOT_CLK>;
 868                                         clock-names = "ipg", "per";
 869                                         status = "disabled";
 870                                 };
 871
 872                                 uart3: serial@30880000 {
 873                                         compatible = "fsl,imx7d-uart",
 874                                                      "fsl,imx6q-uart";
 875                                         reg = <0x30880000 0x10000>;
 876                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 877                                         clocks = <&clks IMX7D_UART3_ROOT_CLK>,
 878                                                 <&clks IMX7D_UART3_ROOT_CLK>;
 879                                         clock-names = "ipg", "per";
 880                                         status = "disabled";
 881                                 };
 882
 883                                 sai1: sai@308a0000 {
 884                                         #sound-dai-cells = <0>;
 885                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 886                                         reg = <0x308a0000 0x10000>;
 887                                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 888                                         clocks = <&clks IMX7D_SAI1_IPG_CLK>,
 889                                                  <&clks IMX7D_SAI1_ROOT_CLK>,
 890                                                  <&clks IMX7D_CLK_DUMMY>,
 891                                                  <&clks IMX7D_CLK_DUMMY>;
 892                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 893                                         dma-names = "rx", "tx";
 894                                         dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
 895                                         status = "disabled";
 896                                 };
 897
 898                                 sai2: sai@308b0000 {
 899                                         #sound-dai-cells = <0>;
 900                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 901                                         reg = <0x308b0000 0x10000>;
 902                                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 903                                         clocks = <&clks IMX7D_SAI2_IPG_CLK>,
 904                                                  <&clks IMX7D_SAI2_ROOT_CLK>,
 905                                                  <&clks IMX7D_CLK_DUMMY>,
 906                                                  <&clks IMX7D_CLK_DUMMY>;
 907                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 908                                         dma-names = "rx", "tx";
 909                                         dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
 910                                         status = "disabled";
 911                                 };
 912
 913                                 sai3: sai@308c0000 {
 914                                         #sound-dai-cells = <0>;
 915                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 916                                         reg = <0x308c0000 0x10000>;
 917                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 918                                         clocks = <&clks IMX7D_SAI3_IPG_CLK>,
 919                                                  <&clks IMX7D_SAI3_ROOT_CLK>,
 920                                                  <&clks IMX7D_CLK_DUMMY>,
 921                                                  <&clks IMX7D_CLK_DUMMY>;
 922                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 923                                         dma-names = "rx", "tx";
 924                                         dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
 925                                         status = "disabled";
 926                                 };
 927                         };
 928
 929                         crypto: caam@30900000 {
 930                                 compatible = "fsl,sec-v4.0";
 931                                 #address-cells = <1>;
 932                                 #size-cells = <1>;
 933                                 reg = <0x30900000 0x40000>;
 934                                 ranges = <0 0x30900000 0x40000>;
 935                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 936                                 clocks = <&clks IMX7D_CAAM_CLK>,
 937                                          <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
 938                                 clock-names = "ipg", "aclk";
 939
 940                                 sec_jr0: jr0@1000 {
 941                                         compatible = "fsl,sec-v4.0-job-ring";
 942                                         reg = <0x1000 0x1000>;
 943                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 944                                 };
 945
 946                                 sec_jr1: jr1@2000 {
 947                                         compatible = "fsl,sec-v4.0-job-ring";
 948                                         reg = <0x2000 0x1000>;
 949                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 950                                 };
 951
 952                                 sec_jr2: jr1@3000 {
 953                                         compatible = "fsl,sec-v4.0-job-ring";
 954                                         reg = <0x3000 0x1000>;
 955                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 956                                 };
 957                         };
 958
 959                         flexcan1: can@30a00000 {
 960                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
 961                                 reg = <0x30a00000 0x10000>;
 962                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 963                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 964                                         <&clks IMX7D_CAN1_ROOT_CLK>;
 965                                 clock-names = "ipg", "per";
 966                                 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
 967                                 status = "disabled";
 968                         };
 969
 970                         flexcan2: can@30a10000 {
 971                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
 972                                 reg = <0x30a10000 0x10000>;
 973                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 974                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 975                                         <&clks IMX7D_CAN2_ROOT_CLK>;
 976                                 clock-names = "ipg", "per";
 977                                 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
 978                                 status = "disabled";
 979                         };
 980
 981                         i2c1: i2c@30a20000 {
 982                                 #address-cells = <1>;
 983                                 #size-cells = <0>;
 984                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 985                                 reg = <0x30a20000 0x10000>;
 986                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 987                                 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
 988                                 status = "disabled";
 989                         };
 990
 991                         i2c2: i2c@30a30000 {
 992                                 #address-cells = <1>;
 993                                 #size-cells = <0>;
 994                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 995                                 reg = <0x30a30000 0x10000>;
 996                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 997                                 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
 998                                 status = "disabled";
 999                         };
1000
1001                         i2c3: i2c@30a40000 {
1002                                 #address-cells = <1>;
1003                                 #size-cells = <0>;
1004                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1005                                 reg = <0x30a40000 0x10000>;
1006                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1007                                 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1008                                 status = "disabled";
1009                         };
1010
1011                         i2c4: i2c@30a50000 {
1012                                 #address-cells = <1>;
1013                                 #size-cells = <0>;
1014                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1015                                 reg = <0x30a50000 0x10000>;
1016                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1017                                 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1018                                 status = "disabled";
1019                         };
1020
1021                         uart4: serial@30a60000 {
1022                                 compatible = "fsl,imx7d-uart",
1023                                              "fsl,imx6q-uart";
1024                                 reg = <0x30a60000 0x10000>;
1025                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1026                                 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1027                                         <&clks IMX7D_UART4_ROOT_CLK>;
1028                                 clock-names = "ipg", "per";
1029                                 status = "disabled";
1030                         };
1031
1032                         uart5: serial@30a70000 {
1033                                 compatible = "fsl,imx7d-uart",
1034                                              "fsl,imx6q-uart";
1035                                 reg = <0x30a70000 0x10000>;
1036                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1037                                 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1038                                         <&clks IMX7D_UART5_ROOT_CLK>;
1039                                 clock-names = "ipg", "per";
1040                                 status = "disabled";
1041                         };
1042
1043                         uart6: serial@30a80000 {
1044                                 compatible = "fsl,imx7d-uart",
1045                                              "fsl,imx6q-uart";
1046                                 reg = <0x30a80000 0x10000>;
1047                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1048                                 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1049                                         <&clks IMX7D_UART6_ROOT_CLK>;
1050                                 clock-names = "ipg", "per";
1051                                 status = "disabled";
1052                         };
1053
1054                         uart7: serial@30a90000 {
1055                                 compatible = "fsl,imx7d-uart",
1056                                              "fsl,imx6q-uart";
1057                                 reg = <0x30a90000 0x10000>;
1058                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1059                                 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1060                                         <&clks IMX7D_UART7_ROOT_CLK>;
1061                                 clock-names = "ipg", "per";
1062                                 status = "disabled";
1063                         };
1064
1065                         mu0a: mailbox@30aa0000 {
1066                                 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1067                                 reg = <0x30aa0000 0x10000>;
1068                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1069                                 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1070                                 #mbox-cells = <2>;
1071                                 status = "disabled";
1072                         };
1073
1074                         mu0b: mailbox@30ab0000 {
1075                                 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1076                                 reg = <0x30ab0000 0x10000>;
1077                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1078                                 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1079                                 #mbox-cells = <2>;
1080                                 fsl,mu-side-b;
1081                                 status = "disabled";
1082                         };
1083
1084                         usbotg1: usb@30b10000 {
1085                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1086                                 reg = <0x30b10000 0x200>;
1087                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1088                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1089                                 fsl,usbphy = <&usbphynop1>;
1090                                 fsl,usbmisc = <&usbmisc1 0>;
1091                                 phy-clkgate-delay-us = <400>;
1092                                 status = "disabled";
1093                         };
1094
1095                         usbh: usb@30b30000 {
1096                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1097                                 reg = <0x30b30000 0x200>;
1098                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1099                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1100                                 fsl,usbphy = <&usbphynop3>;
1101                                 fsl,usbmisc = <&usbmisc3 0>;
1102                                 phy_type = "hsic";
1103                                 dr_mode = "host";
1104                                 phy-clkgate-delay-us = <400>;
1105                                 status = "disabled";
1106                         };
1107
1108                         usbmisc1: usbmisc@30b10200 {
1109                                 #index-cells = <1>;
1110                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1111                                 reg = <0x30b10200 0x200>;
1112                         };
1113
1114                         usbmisc3: usbmisc@30b30200 {
1115                                 #index-cells = <1>;
1116                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1117                                 reg = <0x30b30200 0x200>;
1118                         };
1119
1120                         usdhc1: usdhc@30b40000 {
1121                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1122                                 reg = <0x30b40000 0x10000>;
1123                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1124                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1125                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1126                                         <&clks IMX7D_USDHC1_ROOT_CLK>;
1127                                 clock-names = "ipg", "ahb", "per";
1128                                 bus-width = <4>;
1129                                 status = "disabled";
1130                         };
1131
1132                         usdhc2: usdhc@30b50000 {
1133                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1134                                 reg = <0x30b50000 0x10000>;
1135                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1136                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1137                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1138                                         <&clks IMX7D_USDHC2_ROOT_CLK>;
1139                                 clock-names = "ipg", "ahb", "per";
1140                                 bus-width = <4>;
1141                                 status = "disabled";
1142                         };
1143
1144                         usdhc3: usdhc@30b60000 {
1145                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1146                                 reg = <0x30b60000 0x10000>;
1147                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1148                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1149                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1150                                         <&clks IMX7D_USDHC3_ROOT_CLK>;
1151                                 clock-names = "ipg", "ahb", "per";
1152                                 bus-width = <4>;
1153                                 status = "disabled";
1154                         };
1155
1156                         sdma: sdma@30bd0000 {
1157                                 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1158                                 reg = <0x30bd0000 0x10000>;
1159                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1160                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1161                                          <&clks IMX7D_SDMA_CORE_CLK>;
1162                                 clock-names = "ipg", "ahb";
1163                                 #dma-cells = <3>;
1164                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1165                         };
1166
1167                         fec1: ethernet@30be0000 {
1168                                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1169                                 reg = <0x30be0000 0x10000>;
1170                                 interrupt-names = "int0", "int1", "int2", "pps";
1171                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1172                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1173                                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1174                                         <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1175                                 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1176                                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1177                                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1178                                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1179                                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1180                                 clock-names = "ipg", "ahb", "ptp",
1181                                         "enet_clk_ref", "enet_out";
1182                                 fsl,num-tx-queues=<3>;
1183                                 fsl,num-rx-queues=<3>;
1184                                 status = "disabled";
1185                         };
1186                 };
1187
1188                 dma_apbh: dma-apbh@33000000 {
1189                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1190                         reg = <0x33000000 0x2000>;
1191                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1192                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1193                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1194                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1195                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1196                         #dma-cells = <1>;
1197                         dma-channels = <4>;
1198                         clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1199                 };
1200
1201                 gpmi: gpmi-nand@33002000{
1202                         compatible = "fsl,imx7d-gpmi-nand";
1203                         #address-cells = <1>;
1204                         #size-cells = <1>;
1205                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1206                         reg-names = "gpmi-nand", "bch";
1207                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1208                         interrupt-names = "bch";
1209                         clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1210                                 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1211                         clock-names = "gpmi_io", "gpmi_bch_apb";
1212                         dmas = <&dma_apbh 0>;
1213                         dma-names = "rx-tx";
1214                         status = "disabled";
1215                         assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1216                         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1217                 };
1218         };
1219 };