arch/arm/boot/dts/imx7d-sdb.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright (C) 2015 Freescale Semiconductor, Inc.
   4
   5 /dts-v1/;
   6
   7 #include "imx7d.dtsi"
   8
   9 / {
  10         model = "Freescale i.MX7 SabreSD Board";
  11         compatible = "fsl,imx7d-sdb", "fsl,imx7d";
  12
  13         chosen {
  14                 stdout-path = &uart1;
  15         };
  16
  17         memory@80000000 {
  18                 reg = <0x80000000 0x80000000>;
  19         };
  20
  21         gpio-keys {
  22                 compatible = "gpio-keys";
  23                 pinctrl-names = "default";
  24                 pinctrl-0 = <&pinctrl_gpio_keys>;
  25
  26                 volume-up {
  27                         label = "Volume Up";
  28                         gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
  29                         linux,code = <KEY_VOLUMEUP>;
  30                         wakeup-source;
  31                 };
  32
  33                 volume-down {
  34                         label = "Volume Down";
  35                         gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
  36                         linux,code = <KEY_VOLUMEDOWN>;
  37                         wakeup-source;
  38                 };
  39         };
  40
  41         spi4 {
  42                 compatible = "spi-gpio";
  43                 pinctrl-names = "default";
  44                 pinctrl-0 = <&pinctrl_spi4>;
  45                 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  46                 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  47                 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  48                 num-chipselects = <1>;
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51
  52                 extended_io: gpio-expander@0 {
  53                         compatible = "fairchild,74hc595";
  54                         gpio-controller;
  55                         #gpio-cells = <2>;
  56                         reg = <0>;
  57                         registers-number = <1>;
  58                         spi-max-frequency = <100000>;
  59                 };
  60         };
  61
  62         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  63                 compatible = "regulator-fixed";
  64                 regulator-name = "usb_otg1_vbus";
  65                 regulator-min-microvolt = <5000000>;
  66                 regulator-max-microvolt = <5000000>;
  67                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  68                 enable-active-high;
  69         };
  70
  71         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  72                 compatible = "regulator-fixed";
  73                 regulator-name = "usb_otg2_vbus";
  74                 regulator-min-microvolt = <5000000>;
  75                 regulator-max-microvolt = <5000000>;
  76                 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  77                 enable-active-high;
  78         };
  79
  80         reg_vref_1v8: regulator-vref-1v8 {
  81                 compatible = "regulator-fixed";
  82                 regulator-name = "vref-1v8";
  83                 regulator-min-microvolt = <1800000>;
  84                 regulator-max-microvolt = <1800000>;
  85         };
  86
  87         reg_brcm: regulator-brcm {
  88                 compatible = "regulator-fixed";
  89                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
  90                 enable-active-high;
  91                 regulator-name = "brcm_reg";
  92                 pinctrl-names = "default";
  93                 pinctrl-0 = <&pinctrl_brcm_reg>;
  94                 regulator-min-microvolt = <3300000>;
  95                 regulator-max-microvolt = <3300000>;
  96                 startup-delay-us = <200000>;
  97         };
  98
  99         reg_lcd_3v3: regulator-lcd-3v3 {
 100                 compatible = "regulator-fixed";
 101                 regulator-name = "lcd-3v3";
 102                 regulator-min-microvolt = <3300000>;
 103                 regulator-max-microvolt = <3300000>;
 104                 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
 105         };
 106
 107         reg_can2_3v3: regulator-can2-3v3 {
 108                 compatible = "regulator-fixed";
 109                 regulator-name = "can2-3v3";
 110                 pinctrl-names = "default";
 111                 pinctrl-0 = <&pinctrl_flexcan2_reg>;
 112                 regulator-min-microvolt = <3300000>;
 113                 regulator-max-microvolt = <3300000>;
 114                 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
 115         };
 116
 117         backlight: backlight {
 118                 compatible = "pwm-backlight";
 119                 pwms = <&pwm1 0 5000000 0>;
 120                 brightness-levels = <0 4 8 16 32 64 128 255>;
 121                 default-brightness-level = <6>;
 122                 status = "okay";
 123         };
 124
 125         panel {
 126                 compatible = "innolux,at043tn24";
 127                 backlight = <&backlight>;
 128                 power-supply = <&reg_lcd_3v3>;
 129
 130                 port {
 131                         panel_in: endpoint {
 132                                 remote-endpoint = <&display_out>;
 133                         };
 134                 };
 135         };
 136 };
 137
 138 &adc1 {
 139         vref-supply = <&reg_vref_1v8>;
 140         status = "okay";
 141 };
 142
 143 &adc2 {
 144         vref-supply = <&reg_vref_1v8>;
 145         status = "okay";
 146 };
 147
 148 &cpu0 {
 149         cpu-supply = <&sw1a_reg>;
 150 };
 151
 152 &ecspi3 {
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&pinctrl_ecspi3>;
 155         cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 156         status = "okay";
 157
 158         tsc2046@0 {
 159                 compatible = "ti,tsc2046";
 160                 reg = <0>;
 161                 spi-max-frequency = <1000000>;
 162                 pinctrl-names ="default";
 163                 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
 164                 interrupt-parent = <&gpio2>;
 165                 interrupts = <29 0>;
 166                 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
 167                 ti,x-min = /bits/ 16 <0>;
 168                 ti,x-max = /bits/ 16 <0>;
 169                 ti,y-min = /bits/ 16 <0>;
 170                 ti,y-max = /bits/ 16 <0>;
 171                 ti,pressure-max = /bits/ 16 <0>;
 172                 ti,x-plate-ohms = /bits/ 16 <400>;
 173                 wakeup-source;
 174         };
 175 };
 176
 177 &fec1 {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_enet1>;
 180         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 181                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 182         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 183         assigned-clock-rates = <0>, <100000000>;
 184         phy-mode = "rgmii";
 185         phy-handle = <&ethphy0>;
 186         fsl,magic-packet;
 187         phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
 188         status = "okay";
 189
 190         mdio {
 191                 #address-cells = <1>;
 192                 #size-cells = <0>;
 193
 194                 ethphy0: ethernet-phy@0 {
 195                         reg = <0>;
 196                 };
 197
 198                 ethphy1: ethernet-phy@1 {
 199                         reg = <1>;
 200                 };
 201         };
 202 };
 203
 204 &fec2 {
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&pinctrl_enet2>;
 207         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
 208                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 209         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 210         assigned-clock-rates = <0>, <100000000>;
 211         phy-mode = "rgmii";
 212         phy-handle = <&ethphy1>;
 213         fsl,magic-packet;
 214         status = "okay";
 215 };
 216
 217 &flexcan2 {
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_flexcan2>;
 220         xceiver-supply = <&reg_can2_3v3>;
 221         status = "okay";
 222 };
 223
 224 &i2c1 {
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_i2c1>;
 227         status = "okay";
 228
 229         pmic: pfuze3000@8 {
 230                 compatible = "fsl,pfuze3000";
 231                 reg = <0x08>;
 232
 233                 regulators {
 234                         sw1a_reg: sw1a {
 235                                 regulator-min-microvolt = <700000>;
 236                                 regulator-max-microvolt = <1475000>;
 237                                 regulator-boot-on;
 238                                 regulator-always-on;
 239                                 regulator-ramp-delay = <6250>;
 240                         };
 241
 242                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 243                         sw1c_reg: sw1b {
 244                                 regulator-min-microvolt = <700000>;
 245                                 regulator-max-microvolt = <1475000>;
 246                                 regulator-boot-on;
 247                                 regulator-always-on;
 248                                 regulator-ramp-delay = <6250>;
 249                         };
 250
 251                         sw2_reg: sw2 {
 252                                 regulator-min-microvolt = <1500000>;
 253                                 regulator-max-microvolt = <1850000>;
 254                                 regulator-boot-on;
 255                                 regulator-always-on;
 256                         };
 257
 258                         sw3a_reg: sw3 {
 259                                 regulator-min-microvolt = <900000>;
 260                                 regulator-max-microvolt = <1650000>;
 261                                 regulator-boot-on;
 262                                 regulator-always-on;
 263                         };
 264
 265                         swbst_reg: swbst {
 266                                 regulator-min-microvolt = <5000000>;
 267                                 regulator-max-microvolt = <5150000>;
 268                         };
 269
 270                         snvs_reg: vsnvs {
 271                                 regulator-min-microvolt = <1000000>;
 272                                 regulator-max-microvolt = <3000000>;
 273                                 regulator-boot-on;
 274                                 regulator-always-on;
 275                         };
 276
 277                         vref_reg: vrefddr {
 278                                 regulator-boot-on;
 279                                 regulator-always-on;
 280                         };
 281
 282                         vgen1_reg: vldo1 {
 283                                 regulator-min-microvolt = <1800000>;
 284                                 regulator-max-microvolt = <3300000>;
 285                                 regulator-always-on;
 286                         };
 287
 288                         vgen2_reg: vldo2 {
 289                                 regulator-min-microvolt = <800000>;
 290                                 regulator-max-microvolt = <1550000>;
 291                         };
 292
 293                         vgen3_reg: vccsd {
 294                                 regulator-min-microvolt = <2850000>;
 295                                 regulator-max-microvolt = <3300000>;
 296                                 regulator-always-on;
 297                         };
 298
 299                         vgen4_reg: v33 {
 300                                 regulator-min-microvolt = <2850000>;
 301                                 regulator-max-microvolt = <3300000>;
 302                                 regulator-always-on;
 303                         };
 304
 305                         vgen5_reg: vldo3 {
 306                                 regulator-min-microvolt = <1800000>;
 307                                 regulator-max-microvolt = <3300000>;
 308                                 regulator-always-on;
 309                         };
 310
 311                         vgen6_reg: vldo4 {
 312                                 regulator-min-microvolt = <2800000>;
 313                                 regulator-max-microvolt = <2800000>;
 314                                 regulator-always-on;
 315                         };
 316                 };
 317         };
 318 };
 319
 320 &i2c2 {
 321         pinctrl-names = "default";
 322         pinctrl-0 = <&pinctrl_i2c2>;
 323         status = "okay";
 324
 325         mpl3115@60 {
 326                 compatible = "fsl,mpl3115";
 327                 reg = <0x60>;
 328         };
 329 };
 330
 331 &i2c3 {
 332         pinctrl-names = "default";
 333         pinctrl-0 = <&pinctrl_i2c3>;
 334         status = "okay";
 335 };
 336
 337 &i2c4 {
 338         pinctrl-names = "default";
 339         pinctrl-0 = <&pinctrl_i2c4>;
 340         status = "okay";
 341
 342         codec: wm8960@1a {
 343                 compatible = "wlf,wm8960";
 344                 reg = <0x1a>;
 345                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 346                 clock-names = "mclk";
 347                 wlf,shared-lrclk;
 348         };
 349 };
 350
 351 &lcdif {
 352         pinctrl-names = "default";
 353         pinctrl-0 = <&pinctrl_lcdif>;
 354         status = "okay";
 355
 356         port {
 357                 display_out: endpoint {
 358                         remote-endpoint = <&panel_in>;
 359                 };
 360         };
 361 };
 362
 363 &pcie {
 364         reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
 365         status = "okay";
 366 };
 367
 368 &uart1 {
 369         pinctrl-names = "default";
 370         pinctrl-0 = <&pinctrl_uart1>;
 371         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 372         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 373         status = "okay";
 374 };
 375
 376 &uart6 {
 377         pinctrl-names = "default";
 378         pinctrl-0 = <&pinctrl_uart6>;
 379         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 380         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 381         uart-has-rtscts;
 382         status = "okay";
 383 };
 384
 385 &usbotg1 {
 386         vbus-supply = <&reg_usb_otg1_vbus>;
 387         status = "okay";
 388 };
 389
 390 &usbotg2 {
 391         vbus-supply = <&reg_usb_otg2_vbus>;
 392         dr_mode = "host";
 393         status = "okay";
 394 };
 395
 396 &usdhc1 {
 397         pinctrl-names = "default";
 398         pinctrl-0 = <&pinctrl_usdhc1>;
 399         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 400         wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 401         wakeup-source;
 402         keep-power-in-suspend;
 403         status = "okay";
 404 };
 405
 406 &usdhc2 {
 407         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 408         pinctrl-0 = <&pinctrl_usdhc2>;
 409         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 410         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 411         wakeup-source;
 412         keep-power-in-suspend;
 413         non-removable;
 414         vmmc-supply = <&reg_brcm>;
 415         fsl,tuning-step = <2>;
 416         status = "okay";
 417 };
 418
 419 &usdhc3 {
 420         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 421         pinctrl-0 = <&pinctrl_usdhc3>;
 422         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 423         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 424         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 425         assigned-clock-rates = <400000000>;
 426         bus-width = <8>;
 427         fsl,tuning-step = <2>;
 428         non-removable;
 429         status = "okay";
 430 };
 431
 432 &wdog1 {
 433         pinctrl-names = "default";
 434         pinctrl-0 = <&pinctrl_wdog>;
 435         fsl,ext-reset-output;
 436 };
 437
 438 &iomuxc {
 439         pinctrl-names = "default";
 440         pinctrl-0 = <&pinctrl_hog>;
 441
 442         imx7d-sdb {
 443                 pinctrl_brcm_reg: brcmreggrp {
 444                         fsl,pins = <
 445                                 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x14
 446                         >;
 447                 };
 448
 449                 pinctrl_ecspi3: ecspi3grp {
 450                         fsl,pins = <
 451                                 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO      0x2
 452                                 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI      0x2
 453                                 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK      0x2
 454                                 MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x59
 455                         >;
 456                 };
 457
 458                 pinctrl_enet1: enet1grp {
 459                         fsl,pins = <
 460                                 MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 461                                 MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 462                                 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 463                                 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 464                                 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 465                                 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 466                                 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 467                                 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 468                                 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 469                                 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 470                                 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 471                                 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 472                                 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 473                                 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 474                         >;
 475                 };
 476
 477                 pinctrl_enet2: enet2grp {
 478                         fsl,pins = <
 479                                 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
 480                                 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
 481                                 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
 482                                 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
 483                                 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
 484                                 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
 485                                 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
 486                                 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
 487                                 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
 488                                 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
 489                                 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
 490                                 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
 491                         >;
 492                 };
 493
 494                 pinctrl_flexcan2: flexcan2grp {
 495                         fsl,pins = <
 496                                 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x59
 497                                 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x59
 498                         >;
 499                 };
 500
 501                 pinctrl_flexcan2_reg: flexcan2reggrp {
 502                         fsl,pins = <
 503                                 MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x59    /* CAN_STBY */
 504                         >;
 505                 };
 506
 507                 pinctrl_gpio_keys: gpio_keysgrp {
 508                         fsl,pins = <
 509                                 MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x59
 510                                 MX7D_PAD_SD2_WP__GPIO5_IO10             0x59
 511                         >;
 512                 };
 513
 514                 pinctrl_hog: hoggrp {
 515                         fsl,pins = <
 516                                 MX7D_PAD_UART3_CTS_B__GPIO4_IO7         0x14
 517                                 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x34  /* bt reg on */
 518                         >;
 519                 };
 520
 521                 pinctrl_i2c1: i2c1grp {
 522                         fsl,pins = <
 523                                 MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 524                                 MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 525                         >;
 526                 };
 527
 528                 pinctrl_i2c2: i2c2grp {
 529                         fsl,pins = <
 530                                 MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 531                                 MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 532                         >;
 533                 };
 534
 535                 pinctrl_i2c3: i2c3grp {
 536                         fsl,pins = <
 537                                 MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 538                                 MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 539                         >;
 540                 };
 541
 542                 pinctrl_i2c4: i2c4grp {
 543                         fsl,pins = <
 544                                 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
 545                                 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
 546                         >;
 547                 };
 548
 549                 pinctrl_lcdif: lcdifgrp {
 550                         fsl,pins = <
 551                                 MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 552                                 MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 553                                 MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 554                                 MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 555                                 MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 556                                 MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 557                                 MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 558                                 MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 559                                 MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 560                                 MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 561                                 MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 562                                 MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 563                                 MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 564                                 MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 565                                 MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 566                                 MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 567                                 MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 568                                 MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 569                                 MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 570                                 MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 571                                 MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 572                                 MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 573                                 MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 574                                 MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 575                                 MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 576                                 MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 577                                 MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 578                                 MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 579                                 MX7D_PAD_LCD_RESET__LCD_RESET           0x79
 580                         >;
 581                 };
 582
 583                 pinctrl_spi4: spi4grp {
 584                         fsl,pins = <
 585                                 MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x59
 586                                 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
 587                                 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
 588                         >;
 589                 };
 590
 591                 pinctrl_tsc2046_pendown: tsc2046_pendown {
 592                         fsl,pins = <
 593                                 MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x59
 594                         >;
 595                 };
 596
 597                 pinctrl_uart1: uart1grp {
 598                         fsl,pins = <
 599                                 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 600                                 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 601                         >;
 602                 };
 603
 604                 pinctrl_uart5: uart5grp {
 605                         fsl,pins = <
 606                                 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX     0x79
 607                                 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX     0x79
 608                                 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS    0x79
 609                                 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS    0x79
 610                         >;
 611                 };
 612
 613                 pinctrl_uart6: uart6grp {
 614                         fsl,pins = <
 615                                 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 616                                 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 617                                 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 618                                 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 619                         >;
 620                 };
 621
 622                 pinctrl_usdhc1: usdhc1grp {
 623                         fsl,pins = <
 624                                 MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 625                                 MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 626                                 MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 627                                 MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 628                                 MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 629                                 MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 630                                 MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* CD */
 631                                 MX7D_PAD_SD1_WP__GPIO5_IO1              0x59 /* WP */
 632                                 MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* vmmc */
 633                         >;
 634                 };
 635
 636                 pinctrl_usdhc2: usdhc2grp {
 637                         fsl,pins = <
 638                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 639                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 640                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 641                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 642                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 643                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 644                         >;
 645                 };
 646
 647                 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
 648                         fsl,pins = <
 649                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5a
 650                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1a
 651                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
 652                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
 653                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
 654                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
 655                         >;
 656                 };
 657
 658                 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
 659                         fsl,pins = <
 660                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5b
 661                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1b
 662                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
 663                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
 664                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
 665                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
 666                         >;
 667                 };
 668
 669
 670                 pinctrl_usdhc3: usdhc3grp {
 671                         fsl,pins = <
 672                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 673                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 674                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 675                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 676                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 677                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 678                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 679                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 680                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 681                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 682                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 683                         >;
 684                 };
 685
 686                 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 687                         fsl,pins = <
 688                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 689                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 690                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 691                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 692                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 693                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 694                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 695                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 696                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 697                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 698                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
 699                         >;
 700                 };
 701
 702                 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 703                         fsl,pins = <
 704                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 705                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 706                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 707                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 708                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 709                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 710                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 711                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 712                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 713                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 714                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
 715                         >;
 716                 };
 717         };
 718 };
 719
 720 &pwm1 {
 721         pinctrl-names = "default";
 722         pinctrl-0 = <&pinctrl_pwm1>;
 723         status = "okay";
 724 };
 725
 726 &iomuxc_lpsr {
 727         pinctrl_wdog: wdoggrp {
 728                 fsl,pins = <
 729                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B          0x74
 730                 >;
 731         };
 732
 733         pinctrl_pwm1: pwm1grp {
 734                 fsl,pins = <
 735                         MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT              0x30
 736                 >;
 737         };
 738 };