arch/arm/boot/dts/imx6ul.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6ul-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include "imx6ul-pinfunc.h"
  14
  15 / {
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         /*
  19          * The decompressor and also some bootloaders rely on a
  20          * pre-existing /chosen node to be available to insert the
  21          * command line and merge other ATAGS info.
  22          * Also for U-Boot there must be a pre-existing /memory node.
  23          */
  24         chosen {};
  25         memory { device_type = "memory"; reg = <0 0>; };
  26
  27         aliases {
  28                 ethernet0 = &fec1;
  29                 ethernet1 = &fec2;
  30                 gpio0 = &gpio1;
  31                 gpio1 = &gpio2;
  32                 gpio2 = &gpio3;
  33                 gpio3 = &gpio4;
  34                 gpio4 = &gpio5;
  35                 i2c0 = &i2c1;
  36                 i2c1 = &i2c2;
  37                 i2c2 = &i2c3;
  38                 i2c3 = &i2c4;
  39                 mmc0 = &usdhc1;
  40                 mmc1 = &usdhc2;
  41                 serial0 = &uart1;
  42                 serial1 = &uart2;
  43                 serial2 = &uart3;
  44                 serial3 = &uart4;
  45                 serial4 = &uart5;
  46                 serial5 = &uart6;
  47                 serial6 = &uart7;
  48                 serial7 = &uart8;
  49                 sai1 = &sai1;
  50                 sai2 = &sai2;
  51                 sai3 = &sai3;
  52                 spi0 = &ecspi1;
  53                 spi1 = &ecspi2;
  54                 spi2 = &ecspi3;
  55                 spi3 = &ecspi4;
  56                 usbphy0 = &usbphy1;
  57                 usbphy1 = &usbphy2;
  58         };
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 cpu0: cpu@0 {
  65                         compatible = "arm,cortex-a7";
  66                         device_type = "cpu";
  67                         reg = <0>;
  68                         clock-latency = <61036>; /* two CLK32 periods */
  69                         operating-points = <
  70                                 /* kHz  uV */
  71                                 528000  1175000
  72                                 396000  1025000
  73                                 198000  950000
  74                         >;
  75                         fsl,soc-operating-points = <
  76                                 /* KHz  uV */
  77                                 528000  1175000
  78                                 396000  1175000
  79                                 198000  1175000
  80                         >;
  81                         clocks = <&clks IMX6UL_CLK_ARM>,
  82                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  83                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  84                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  85                                  <&clks IMX6UL_CLK_STEP>,
  86                                  <&clks IMX6UL_CLK_PLL1_SW>,
  87                                  <&clks IMX6UL_CLK_PLL1_SYS>,
  88                                  <&clks IMX6UL_PLL1_BYPASS>,
  89                                  <&clks IMX6UL_CLK_PLL1>,
  90                                  <&clks IMX6UL_PLL1_BYPASS_SRC>,
  91                                  <&clks IMX6UL_CLK_OSC>;
  92                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  93                                       "secondary_sel", "step", "pll1_sw",
  94                                       "pll1_sys", "pll1_bypass", "pll1",
  95                                       "pll1_bypass_src", "osc";
  96                         arm-supply = <&reg_arm>;
  97                         soc-supply = <&reg_soc>;
  98                 };
  99         };
 100
 101         intc: interrupt-controller@a01000 {
 102                 compatible = "arm,gic-400", "arm,cortex-a7-gic";
 103                 #interrupt-cells = <3>;
 104                 interrupt-controller;
 105                 reg = <0x00a01000 0x1000>,
 106                       <0x00a02000 0x2000>,
 107                       <0x00a04000 0x2000>,
 108                       <0x00a06000 0x2000>;
 109         };
 110
 111         ckil: clock-cli {
 112                 compatible = "fixed-clock";
 113                 #clock-cells = <0>;
 114                 clock-frequency = <32768>;
 115                 clock-output-names = "ckil";
 116         };
 117
 118         osc: clock-osc {
 119                 compatible = "fixed-clock";
 120                 #clock-cells = <0>;
 121                 clock-frequency = <24000000>;
 122                 clock-output-names = "osc";
 123         };
 124
 125         ipp_di0: clock-di0 {
 126                 compatible = "fixed-clock";
 127                 #clock-cells = <0>;
 128                 clock-frequency = <0>;
 129                 clock-output-names = "ipp_di0";
 130         };
 131
 132         ipp_di1: clock-di1 {
 133                 compatible = "fixed-clock";
 134                 #clock-cells = <0>;
 135                 clock-frequency = <0>;
 136                 clock-output-names = "ipp_di1";
 137         };
 138
 139         tempmon: tempmon {
 140                 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
 141                 interrupt-parent = <&gpc>;
 142                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 143                 fsl,tempmon = <&anatop>;
 144                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 145                 nvmem-cell-names = "calib", "temp_grade";
 146                 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
 147         };
 148
 149         pmu {
 150                 compatible = "arm,cortex-a7-pmu";
 151                 interrupt-parent = <&gpc>;
 152                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 153                 status = "disabled";
 154         };
 155
 156         soc {
 157                 #address-cells = <1>;
 158                 #size-cells = <1>;
 159                 compatible = "simple-bus";
 160                 interrupt-parent = <&gpc>;
 161                 ranges;
 162
 163                 ocram: sram@900000 {
 164                         compatible = "mmio-sram";
 165                         reg = <0x00900000 0x20000>;
 166                 };
 167
 168                 dma_apbh: dma-apbh@1804000 {
 169                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 170                         reg = <0x01804000 0x2000>;
 171                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 172                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 173                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 174                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 175                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 176                         #dma-cells = <1>;
 177                         dma-channels = <4>;
 178                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 179                 };
 180
 181                 gpmi: gpmi-nand@1806000         {
 182                         compatible = "fsl,imx6q-gpmi-nand";
 183                         #address-cells = <1>;
 184                         #size-cells = <1>;
 185                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 186                         reg-names = "gpmi-nand", "bch";
 187                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 188                         interrupt-names = "bch";
 189                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 190                                  <&clks IMX6UL_CLK_GPMI_APB>,
 191                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 192                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 193                                  <&clks IMX6UL_CLK_PER_BCH>;
 194                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 195                                       "gpmi_bch_apb", "per1_bch";
 196                         dmas = <&dma_apbh 0>;
 197                         dma-names = "rx-tx";
 198                         status = "disabled";
 199                 };
 200
 201                 aips1: aips-bus@2000000 {
 202                         compatible = "fsl,aips-bus", "simple-bus";
 203                         #address-cells = <1>;
 204                         #size-cells = <1>;
 205                         reg = <0x02000000 0x100000>;
 206                         ranges;
 207
 208                         spba-bus@2000000 {
 209                                 compatible = "fsl,spba-bus", "simple-bus";
 210                                 #address-cells = <1>;
 211                                 #size-cells = <1>;
 212                                 reg = <0x02000000 0x40000>;
 213                                 ranges;
 214
 215                                 ecspi1: ecspi@2008000 {
 216                                         #address-cells = <1>;
 217                                         #size-cells = <0>;
 218                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 219                                         reg = <0x02008000 0x4000>;
 220                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 221                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 222                                                  <&clks IMX6UL_CLK_ECSPI1>;
 223                                         clock-names = "ipg", "per";
 224                                         status = "disabled";
 225                                 };
 226
 227                                 ecspi2: ecspi@200c000 {
 228                                         #address-cells = <1>;
 229                                         #size-cells = <0>;
 230                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 231                                         reg = <0x0200c000 0x4000>;
 232                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 233                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 234                                                  <&clks IMX6UL_CLK_ECSPI2>;
 235                                         clock-names = "ipg", "per";
 236                                         status = "disabled";
 237                                 };
 238
 239                                 ecspi3: ecspi@2010000 {
 240                                         #address-cells = <1>;
 241                                         #size-cells = <0>;
 242                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 243                                         reg = <0x02010000 0x4000>;
 244                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 245                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 246                                                  <&clks IMX6UL_CLK_ECSPI3>;
 247                                         clock-names = "ipg", "per";
 248                                         status = "disabled";
 249                                 };
 250
 251                                 ecspi4: ecspi@2014000 {
 252                                         #address-cells = <1>;
 253                                         #size-cells = <0>;
 254                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 255                                         reg = <0x02014000 0x4000>;
 256                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 257                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 258                                                  <&clks IMX6UL_CLK_ECSPI4>;
 259                                         clock-names = "ipg", "per";
 260                                         status = "disabled";
 261                                 };
 262
 263                                 uart7: serial@2018000 {
 264                                         compatible = "fsl,imx6ul-uart",
 265                                                      "fsl,imx6q-uart";
 266                                         reg = <0x02018000 0x4000>;
 267                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 268                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 269                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 270                                         clock-names = "ipg", "per";
 271                                         status = "disabled";
 272                                 };
 273
 274                                 uart1: serial@2020000 {
 275                                         compatible = "fsl,imx6ul-uart",
 276                                                      "fsl,imx6q-uart";
 277                                         reg = <0x02020000 0x4000>;
 278                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 279                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 280                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 281                                         clock-names = "ipg", "per";
 282                                         status = "disabled";
 283                                 };
 284
 285                                 uart8: serial@2024000 {
 286                                         compatible = "fsl,imx6ul-uart",
 287                                                      "fsl,imx6q-uart";
 288                                         reg = <0x02024000 0x4000>;
 289                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 290                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 291                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 292                                         clock-names = "ipg", "per";
 293                                         status = "disabled";
 294                                 };
 295
 296                                 sai1: sai@2028000 {
 297                                         #sound-dai-cells = <0>;
 298                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 299                                         reg = <0x02028000 0x4000>;
 300                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 301                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 302                                                  <&clks IMX6UL_CLK_SAI1>,
 303                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 304                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 305                                         dmas = <&sdma 35 24 0>,
 306                                                <&sdma 36 24 0>;
 307                                         dma-names = "rx", "tx";
 308                                         status = "disabled";
 309                                 };
 310
 311                                 sai2: sai@202c000 {
 312                                         #sound-dai-cells = <0>;
 313                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 314                                         reg = <0x0202c000 0x4000>;
 315                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 316                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 317                                                  <&clks IMX6UL_CLK_SAI2>,
 318                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 319                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 320                                         dmas = <&sdma 37 24 0>,
 321                                                <&sdma 38 24 0>;
 322                                         dma-names = "rx", "tx";
 323                                         status = "disabled";
 324                                 };
 325
 326                                 sai3: sai@2030000 {
 327                                         #sound-dai-cells = <0>;
 328                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 329                                         reg = <0x02030000 0x4000>;
 330                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 331                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 332                                                  <&clks IMX6UL_CLK_SAI3>,
 333                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 334                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 335                                         dmas = <&sdma 39 24 0>,
 336                                                <&sdma 40 24 0>;
 337                                         dma-names = "rx", "tx";
 338                                         status = "disabled";
 339                                 };
 340                         };
 341
 342                         tsc: tsc@2040000 {
 343                                 compatible = "fsl,imx6ul-tsc";
 344                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 345                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 346                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 347                                 clocks = <&clks IMX6UL_CLK_IPG>,
 348                                          <&clks IMX6UL_CLK_ADC2>;
 349                                 clock-names = "tsc", "adc";
 350                                 status = "disabled";
 351                         };
 352
 353                         pwm1: pwm@2080000 {
 354                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 355                                 reg = <0x02080000 0x4000>;
 356                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 357                                 clocks = <&clks IMX6UL_CLK_PWM1>,
 358                                          <&clks IMX6UL_CLK_PWM1>;
 359                                 clock-names = "ipg", "per";
 360                                 #pwm-cells = <2>;
 361                                 status = "disabled";
 362                         };
 363
 364                         pwm2: pwm@2084000 {
 365                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 366                                 reg = <0x02084000 0x4000>;
 367                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 368                                 clocks = <&clks IMX6UL_CLK_PWM2>,
 369                                          <&clks IMX6UL_CLK_PWM2>;
 370                                 clock-names = "ipg", "per";
 371                                 #pwm-cells = <2>;
 372                                 status = "disabled";
 373                         };
 374
 375                         pwm3: pwm@2088000 {
 376                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 377                                 reg = <0x02088000 0x4000>;
 378                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 379                                 clocks = <&clks IMX6UL_CLK_PWM3>,
 380                                          <&clks IMX6UL_CLK_PWM3>;
 381                                 clock-names = "ipg", "per";
 382                                 #pwm-cells = <2>;
 383                                 status = "disabled";
 384                         };
 385
 386                         pwm4: pwm@208c000 {
 387                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 388                                 reg = <0x0208c000 0x4000>;
 389                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 390                                 clocks = <&clks IMX6UL_CLK_PWM4>,
 391                                          <&clks IMX6UL_CLK_PWM4>;
 392                                 clock-names = "ipg", "per";
 393                                 #pwm-cells = <2>;
 394                                 status = "disabled";
 395                         };
 396
 397                         can1: flexcan@2090000 {
 398                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 399                                 reg = <0x02090000 0x4000>;
 400                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 401                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 402                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 403                                 clock-names = "ipg", "per";
 404                                 status = "disabled";
 405                         };
 406
 407                         can2: flexcan@2094000 {
 408                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 409                                 reg = <0x02094000 0x4000>;
 410                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 411                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 412                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 413                                 clock-names = "ipg", "per";
 414                                 status = "disabled";
 415                         };
 416
 417                         gpt1: gpt@2098000 {
 418                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 419                                 reg = <0x02098000 0x4000>;
 420                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 421                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 422                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 423                                 clock-names = "ipg", "per";
 424                         };
 425
 426                         gpio1: gpio@209c000 {
 427                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 428                                 reg = <0x0209c000 0x4000>;
 429                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 430                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 431                                 gpio-controller;
 432                                 #gpio-cells = <2>;
 433                                 interrupt-controller;
 434                                 #interrupt-cells = <2>;
 435                                 gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
 436                                               <&iomuxc 16 33 16>;
 437                         };
 438
 439                         gpio2: gpio@20a0000 {
 440                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 441                                 reg = <0x020a0000 0x4000>;
 442                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 443                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 444                                 gpio-controller;
 445                                 #gpio-cells = <2>;
 446                                 interrupt-controller;
 447                                 #interrupt-cells = <2>;
 448                                 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
 449                         };
 450
 451                         gpio3: gpio@20a4000 {
 452                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 453                                 reg = <0x020a4000 0x4000>;
 454                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 455                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 456                                 gpio-controller;
 457                                 #gpio-cells = <2>;
 458                                 interrupt-controller;
 459                                 #interrupt-cells = <2>;
 460                                 gpio-ranges = <&iomuxc 0 65 29>;
 461                         };
 462
 463                         gpio4: gpio@20a8000 {
 464                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 465                                 reg = <0x020a8000 0x4000>;
 466                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 467                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 468                                 gpio-controller;
 469                                 #gpio-cells = <2>;
 470                                 interrupt-controller;
 471                                 #interrupt-cells = <2>;
 472                                 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
 473                         };
 474
 475                         gpio5: gpio@20ac000 {
 476                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 477                                 reg = <0x020ac000 0x4000>;
 478                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 479                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 480                                 gpio-controller;
 481                                 #gpio-cells = <2>;
 482                                 interrupt-controller;
 483                                 #interrupt-cells = <2>;
 484                                 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
 485                         };
 486
 487                         fec2: ethernet@20b4000 {
 488                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 489                                 reg = <0x020b4000 0x4000>;
 490                                 interrupt-names = "int0", "pps";
 491                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 492                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 493                                 clocks = <&clks IMX6UL_CLK_ENET>,
 494                                          <&clks IMX6UL_CLK_ENET_AHB>,
 495                                          <&clks IMX6UL_CLK_ENET_PTP>,
 496                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 497                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 498                                 clock-names = "ipg", "ahb", "ptp",
 499                                               "enet_clk_ref", "enet_out";
 500                                 fsl,num-tx-queues=<1>;
 501                                 fsl,num-rx-queues=<1>;
 502                                 status = "disabled";
 503                         };
 504
 505                         kpp: kpp@20b8000 {
 506                                 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
 507                                 reg = <0x020b8000 0x4000>;
 508                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 509                                 clocks = <&clks IMX6UL_CLK_KPP>;
 510                                 status = "disabled";
 511                         };
 512
 513                         wdog1: wdog@20bc000 {
 514                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 515                                 reg = <0x020bc000 0x4000>;
 516                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 517                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 518                         };
 519
 520                         wdog2: wdog@20c0000 {
 521                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 522                                 reg = <0x020c0000 0x4000>;
 523                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 524                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 525                                 status = "disabled";
 526                         };
 527
 528                         clks: ccm@20c4000 {
 529                                 compatible = "fsl,imx6ul-ccm";
 530                                 reg = <0x020c4000 0x4000>;
 531                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 532                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 533                                 #clock-cells = <1>;
 534                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 535                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 536                         };
 537
 538                         anatop: anatop@20c8000 {
 539                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 540                                              "syscon", "simple-bus";
 541                                 reg = <0x020c8000 0x1000>;
 542                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 543                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 544                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 545                                 #address-cells = <1>;
 546                                 #size-cells = <0>;
 547
 548                                 reg_3p0: regulator-3p0@20c8110 {
 549                                         reg = <0x20c8110>;
 550                                         compatible = "fsl,anatop-regulator";
 551                                         regulator-name = "vdd3p0";
 552                                         regulator-min-microvolt = <2625000>;
 553                                         regulator-max-microvolt = <3400000>;
 554                                         anatop-reg-offset = <0x120>;
 555                                         anatop-vol-bit-shift = <8>;
 556                                         anatop-vol-bit-width = <5>;
 557                                         anatop-min-bit-val = <0>;
 558                                         anatop-min-voltage = <2625000>;
 559                                         anatop-max-voltage = <3400000>;
 560                                         anatop-enable-bit = <0>;
 561                                 };
 562
 563                                 reg_arm: regulator-vddcore@20c8140 {
 564                                         reg = <0x20c8140>;
 565                                         compatible = "fsl,anatop-regulator";
 566                                         regulator-name = "cpu";
 567                                         regulator-min-microvolt = <725000>;
 568                                         regulator-max-microvolt = <1450000>;
 569                                         regulator-always-on;
 570                                         anatop-reg-offset = <0x140>;
 571                                         anatop-vol-bit-shift = <0>;
 572                                         anatop-vol-bit-width = <5>;
 573                                         anatop-delay-reg-offset = <0x170>;
 574                                         anatop-delay-bit-shift = <24>;
 575                                         anatop-delay-bit-width = <2>;
 576                                         anatop-min-bit-val = <1>;
 577                                         anatop-min-voltage = <725000>;
 578                                         anatop-max-voltage = <1450000>;
 579                                 };
 580
 581                                 reg_soc: regulator-vddsoc@20c8140 {
 582                                         reg = <0x20c8140>;
 583                                         compatible = "fsl,anatop-regulator";
 584                                         regulator-name = "vddsoc";
 585                                         regulator-min-microvolt = <725000>;
 586                                         regulator-max-microvolt = <1450000>;
 587                                         regulator-always-on;
 588                                         anatop-reg-offset = <0x140>;
 589                                         anatop-vol-bit-shift = <18>;
 590                                         anatop-vol-bit-width = <5>;
 591                                         anatop-delay-reg-offset = <0x170>;
 592                                         anatop-delay-bit-shift = <28>;
 593                                         anatop-delay-bit-width = <2>;
 594                                         anatop-min-bit-val = <1>;
 595                                         anatop-min-voltage = <725000>;
 596                                         anatop-max-voltage = <1450000>;
 597                                 };
 598                         };
 599
 600                         usbphy1: usbphy@20c9000 {
 601                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 602                                 reg = <0x020c9000 0x1000>;
 603                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 604                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 605                                 phy-3p0-supply = <&reg_3p0>;
 606                                 fsl,anatop = <&anatop>;
 607                         };
 608
 609                         usbphy2: usbphy@20ca000 {
 610                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 611                                 reg = <0x020ca000 0x1000>;
 612                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 613                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 614                                 phy-3p0-supply = <&reg_3p0>;
 615                                 fsl,anatop = <&anatop>;
 616                         };
 617
 618                         snvs: snvs@20cc000 {
 619                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 620                                 reg = <0x020cc000 0x4000>;
 621
 622                                 snvs_rtc: snvs-rtc-lp {
 623                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 624                                         regmap = <&snvs>;
 625                                         offset = <0x34>;
 626                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 627                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 628                                 };
 629
 630                                 snvs_poweroff: snvs-poweroff {
 631                                         compatible = "syscon-poweroff";
 632                                         regmap = <&snvs>;
 633                                         offset = <0x38>;
 634                                         value = <0x60>;
 635                                         mask = <0x60>;
 636                                         status = "disabled";
 637                                 };
 638
 639                                 snvs_pwrkey: snvs-powerkey {
 640                                         compatible = "fsl,sec-v4.0-pwrkey";
 641                                         regmap = <&snvs>;
 642                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 643                                         linux,keycode = <KEY_POWER>;
 644                                         wakeup-source;
 645                                 };
 646
 647                                 snvs_lpgpr: snvs-lpgpr {
 648                                         compatible = "fsl,imx6ul-snvs-lpgpr";
 649                                 };
 650                         };
 651
 652                         epit1: epit@20d0000 {
 653                                 reg = <0x020d0000 0x4000>;
 654                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 655                         };
 656
 657                         epit2: epit@20d4000 {
 658                                 reg = <0x020d4000 0x4000>;
 659                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 660                         };
 661
 662                         src: src@20d8000 {
 663                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 664                                 reg = <0x020d8000 0x4000>;
 665                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 666                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 667                                 #reset-cells = <1>;
 668                         };
 669
 670                         gpc: gpc@20dc000 {
 671                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 672                                 reg = <0x020dc000 0x4000>;
 673                                 interrupt-controller;
 674                                 #interrupt-cells = <3>;
 675                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 676                                 interrupt-parent = <&intc>;
 677                         };
 678
 679                         iomuxc: iomuxc@20e0000 {
 680                                 compatible = "fsl,imx6ul-iomuxc";
 681                                 reg = <0x020e0000 0x4000>;
 682                         };
 683
 684                         gpr: iomuxc-gpr@20e4000 {
 685                                 compatible = "fsl,imx6ul-iomuxc-gpr",
 686                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 687                                 reg = <0x020e4000 0x4000>;
 688                         };
 689
 690                         gpt2: gpt@20e8000 {
 691                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 692                                 reg = <0x020e8000 0x4000>;
 693                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 694                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 695                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 696                                 clock-names = "ipg", "per";
 697                         };
 698
 699                         sdma: sdma@20ec000 {
 700                                 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
 701                                              "fsl,imx35-sdma";
 702                                 reg = <0x020ec000 0x4000>;
 703                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 704                                 clocks = <&clks IMX6UL_CLK_SDMA>,
 705                                          <&clks IMX6UL_CLK_SDMA>;
 706                                 clock-names = "ipg", "ahb";
 707                                 #dma-cells = <3>;
 708                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 709                         };
 710
 711                         pwm5: pwm@20f0000 {
 712                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 713                                 reg = <0x020f0000 0x4000>;
 714                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 715                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 716                                          <&clks IMX6UL_CLK_PWM5>;
 717                                 clock-names = "ipg", "per";
 718                                 #pwm-cells = <2>;
 719                                 status = "disabled";
 720                         };
 721
 722                         pwm6: pwm@20f4000 {
 723                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 724                                 reg = <0x020f4000 0x4000>;
 725                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 726                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 727                                          <&clks IMX6UL_CLK_PWM6>;
 728                                 clock-names = "ipg", "per";
 729                                 #pwm-cells = <2>;
 730                                 status = "disabled";
 731                         };
 732
 733                         pwm7: pwm@20f8000 {
 734                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 735                                 reg = <0x020f8000 0x4000>;
 736                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 737                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 738                                          <&clks IMX6UL_CLK_PWM7>;
 739                                 clock-names = "ipg", "per";
 740                                 #pwm-cells = <2>;
 741                                 status = "disabled";
 742                         };
 743
 744                         pwm8: pwm@20fc000 {
 745                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 746                                 reg = <0x020fc000 0x4000>;
 747                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 748                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 749                                          <&clks IMX6UL_CLK_PWM8>;
 750                                 clock-names = "ipg", "per";
 751                                 #pwm-cells = <2>;
 752                                 status = "disabled";
 753                         };
 754                 };
 755
 756                 aips2: aips-bus@2100000 {
 757                         compatible = "fsl,aips-bus", "simple-bus";
 758                         #address-cells = <1>;
 759                         #size-cells = <1>;
 760                         reg = <0x02100000 0x100000>;
 761                         ranges;
 762
 763                         usbotg1: usb@2184000 {
 764                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 765                                 reg = <0x02184000 0x200>;
 766                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 767                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 768                                 fsl,usbphy = <&usbphy1>;
 769                                 fsl,usbmisc = <&usbmisc 0>;
 770                                 fsl,anatop = <&anatop>;
 771                                 ahb-burst-config = <0x0>;
 772                                 tx-burst-size-dword = <0x10>;
 773                                 rx-burst-size-dword = <0x10>;
 774                                 status = "disabled";
 775                         };
 776
 777                         usbotg2: usb@2184200 {
 778                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 779                                 reg = <0x02184200 0x200>;
 780                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 781                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 782                                 fsl,usbphy = <&usbphy2>;
 783                                 fsl,usbmisc = <&usbmisc 1>;
 784                                 ahb-burst-config = <0x0>;
 785                                 tx-burst-size-dword = <0x10>;
 786                                 rx-burst-size-dword = <0x10>;
 787                                 status = "disabled";
 788                         };
 789
 790                         usbmisc: usbmisc@2184800 {
 791                                 #index-cells = <1>;
 792                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 793                                 reg = <0x02184800 0x200>;
 794                         };
 795
 796                         fec1: ethernet@2188000 {
 797                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 798                                 reg = <0x02188000 0x4000>;
 799                                 interrupt-names = "int0", "pps";
 800                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 801                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 802                                 clocks = <&clks IMX6UL_CLK_ENET>,
 803                                          <&clks IMX6UL_CLK_ENET_AHB>,
 804                                          <&clks IMX6UL_CLK_ENET_PTP>,
 805                                          <&clks IMX6UL_CLK_ENET_REF>,
 806                                          <&clks IMX6UL_CLK_ENET_REF>;
 807                                 clock-names = "ipg", "ahb", "ptp",
 808                                               "enet_clk_ref", "enet_out";
 809                                 fsl,num-tx-queues=<1>;
 810                                 fsl,num-rx-queues=<1>;
 811                                 status = "disabled";
 812                         };
 813
 814                         usdhc1: usdhc@2190000 {
 815                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 816                                 reg = <0x02190000 0x4000>;
 817                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 818                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 819                                          <&clks IMX6UL_CLK_USDHC1>,
 820                                          <&clks IMX6UL_CLK_USDHC1>;
 821                                 clock-names = "ipg", "ahb", "per";
 822                                 bus-width = <4>;
 823                                 status = "disabled";
 824                         };
 825
 826                         usdhc2: usdhc@2194000 {
 827                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 828                                 reg = <0x02194000 0x4000>;
 829                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 830                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 831                                          <&clks IMX6UL_CLK_USDHC2>,
 832                                          <&clks IMX6UL_CLK_USDHC2>;
 833                                 clock-names = "ipg", "ahb", "per";
 834                                 bus-width = <4>;
 835                                 status = "disabled";
 836                         };
 837
 838                         adc1: adc@2198000 {
 839                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
 840                                 reg = <0x02198000 0x4000>;
 841                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 842                                 clocks = <&clks IMX6UL_CLK_ADC1>;
 843                                 num-channels = <2>;
 844                                 clock-names = "adc";
 845                                 fsl,adck-max-frequency = <30000000>, <40000000>,
 846                                                          <20000000>;
 847                                 status = "disabled";
 848                         };
 849
 850                         i2c1: i2c@21a0000 {
 851                                 #address-cells = <1>;
 852                                 #size-cells = <0>;
 853                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 854                                 reg = <0x021a0000 0x4000>;
 855                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 856                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 857                                 status = "disabled";
 858                         };
 859
 860                         i2c2: i2c@21a4000 {
 861                                 #address-cells = <1>;
 862                                 #size-cells = <0>;
 863                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 864                                 reg = <0x021a4000 0x4000>;
 865                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 866                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 867                                 status = "disabled";
 868                         };
 869
 870                         i2c3: i2c@21a8000 {
 871                                 #address-cells = <1>;
 872                                 #size-cells = <0>;
 873                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 874                                 reg = <0x021a8000 0x4000>;
 875                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 876                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 877                                 status = "disabled";
 878                         };
 879
 880                         mmdc: mmdc@21b0000 {
 881                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 882                                 reg = <0x021b0000 0x4000>;
 883                         };
 884
 885                         ocotp: ocotp-ctrl@21bc000 {
 886                                 #address-cells = <1>;
 887                                 #size-cells = <1>;
 888                                 compatible = "fsl,imx6ul-ocotp", "syscon";
 889                                 reg = <0x021bc000 0x4000>;
 890                                 clocks = <&clks IMX6UL_CLK_OCOTP>;
 891
 892                                 tempmon_calib: calib@38 {
 893                                         reg = <0x38 4>;
 894                                 };
 895
 896                                 tempmon_temp_grade: temp-grade@20 {
 897                                         reg = <0x20 4>;
 898                                 };
 899                         };
 900
 901                         lcdif: lcdif@21c8000 {
 902                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 903                                 reg = <0x021c8000 0x4000>;
 904                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 905                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
 906                                          <&clks IMX6UL_CLK_LCDIF_APB>,
 907                                          <&clks IMX6UL_CLK_DUMMY>;
 908                                 clock-names = "pix", "axi", "disp_axi";
 909                                 status = "disabled";
 910                         };
 911
 912                         qspi: qspi@21e0000 {
 913                                 #address-cells = <1>;
 914                                 #size-cells = <0>;
 915                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 916                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 917                                 reg-names = "QuadSPI", "QuadSPI-memory";
 918                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 919                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 920                                          <&clks IMX6UL_CLK_QSPI>;
 921                                 clock-names = "qspi_en", "qspi";
 922                                 status = "disabled";
 923                         };
 924
 925                         uart2: serial@21e8000 {
 926                                 compatible = "fsl,imx6ul-uart",
 927                                              "fsl,imx6q-uart";
 928                                 reg = <0x021e8000 0x4000>;
 929                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 930                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 931                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 932                                 clock-names = "ipg", "per";
 933                                 status = "disabled";
 934                         };
 935
 936                         uart3: serial@21ec000 {
 937                                 compatible = "fsl,imx6ul-uart",
 938                                              "fsl,imx6q-uart";
 939                                 reg = <0x021ec000 0x4000>;
 940                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 941                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
 942                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
 943                                 clock-names = "ipg", "per";
 944                                 status = "disabled";
 945                         };
 946
 947                         uart4: serial@21f0000 {
 948                                 compatible = "fsl,imx6ul-uart",
 949                                              "fsl,imx6q-uart";
 950                                 reg = <0x021f0000 0x4000>;
 951                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 952                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
 953                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
 954                                 clock-names = "ipg", "per";
 955                                 status = "disabled";
 956                         };
 957
 958                         uart5: serial@21f4000 {
 959                                 compatible = "fsl,imx6ul-uart",
 960                                              "fsl,imx6q-uart";
 961                                 reg = <0x021f4000 0x4000>;
 962                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 963                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
 964                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
 965                                 clock-names = "ipg", "per";
 966                                 status = "disabled";
 967                         };
 968
 969                         i2c4: i2c@21f8000 {
 970                                 #address-cells = <1>;
 971                                 #size-cells = <0>;
 972                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 973                                 reg = <0x021f8000 0x4000>;
 974                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 975                                 clocks = <&clks IMX6UL_CLK_I2C4>;
 976                                 status = "disabled";
 977                         };
 978
 979                         uart6: serial@21fc000 {
 980                                 compatible = "fsl,imx6ul-uart",
 981                                              "fsl,imx6q-uart";
 982                                 reg = <0x021fc000 0x4000>;
 983                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 984                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
 985                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
 986                                 clock-names = "ipg", "per";
 987                                 status = "disabled";
 988                         };
 989                 };
 990         };
 991 };