arch/arm/boot/dts/imx6ul-14x14-evk.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (C) 2015 Freescale Semiconductor, Inc.
   4
   5 / {
   6         chosen {
   7                 stdout-path = &uart1;
   8         };
   9
  10         memory@80000000 {
  11                 device_type = "memory";
  12                 reg = <0x80000000 0x20000000>;
  13         };
  14
  15         backlight_display: backlight-display {
  16                 compatible = "pwm-backlight";
  17                 pwms = <&pwm1 0 5000000>;
  18                 brightness-levels = <0 4 8 16 32 64 128 255>;
  19                 default-brightness-level = <6>;
  20                 status = "okay";
  21         };
  22
  23
  24         reg_sd1_vmmc: regulator-sd1-vmmc {
  25                 compatible = "regulator-fixed";
  26                 regulator-name = "VSD_3V3";
  27                 regulator-min-microvolt = <3300000>;
  28                 regulator-max-microvolt = <3300000>;
  29                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  30                 enable-active-high;
  31         };
  32
  33         reg_sensors: regulator-sensors {
  34                 compatible = "regulator-fixed";
  35                 pinctrl-names = "default";
  36                 pinctrl-0 = <&pinctrl_sensors_reg>;
  37                 regulator-name = "sensors-supply";
  38                 regulator-min-microvolt = <3300000>;
  39                 regulator-max-microvolt = <3300000>;
  40                 gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
  41         };
  42
  43         reg_can_3v3: regulator-can-3v3 {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "can-3v3";
  46                 regulator-min-microvolt = <3300000>;
  47                 regulator-max-microvolt = <3300000>;
  48                 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
  49         };
  50
  51         sound {
  52                 compatible = "simple-audio-card";
  53                 simple-audio-card,name = "mx6ul-wm8960";
  54                 simple-audio-card,format = "i2s";
  55                 simple-audio-card,bitclock-master = <&dailink_master>;
  56                 simple-audio-card,frame-master = <&dailink_master>;
  57                 simple-audio-card,widgets =
  58                         "Microphone", "Mic Jack",
  59                         "Line", "Line In",
  60                         "Line", "Line Out",
  61                         "Speaker", "Speaker",
  62                         "Headphone", "Headphone Jack";
  63                 simple-audio-card,routing =
  64                         "Headphone Jack", "HP_L",
  65                         "Headphone Jack", "HP_R",
  66                         "Speaker", "SPK_LP",
  67                         "Speaker", "SPK_LN",
  68                         "Speaker", "SPK_RP",
  69                         "Speaker", "SPK_RN",
  70                         "LINPUT1", "Mic Jack",
  71                         "LINPUT3", "Mic Jack",
  72                         "RINPUT1", "Mic Jack",
  73                         "RINPUT2", "Mic Jack";
  74
  75                 simple-audio-card,cpu {
  76                         sound-dai = <&sai2>;
  77                 };
  78
  79                 dailink_master: simple-audio-card,codec {
  80                         sound-dai = <&codec>;
  81                         clocks = <&clks IMX6UL_CLK_SAI2>;
  82                 };
  83         };
  84
  85         spi4 {
  86                 compatible = "spi-gpio";
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pinctrl_spi4>;
  89                 status = "okay";
  90                 gpio-sck = <&gpio5 11 0>;
  91                 gpio-mosi = <&gpio5 10 0>;
  92                 cs-gpios = <&gpio5 7 0>;
  93                 num-chipselects = <1>;
  94                 #address-cells = <1>;
  95                 #size-cells = <0>;
  96
  97                 gpio_spi: gpio@0 {
  98                         compatible = "fairchild,74hc595";
  99                         gpio-controller;
 100                         #gpio-cells = <2>;
 101                         reg = <0>;
 102                         registers-number = <1>;
 103                         spi-max-frequency = <100000>;
 104                 };
 105         };
 106
 107         panel {
 108                 compatible = "innolux,at043tn24";
 109                 backlight = <&backlight_display>;
 110
 111                 port {
 112                         panel_in: endpoint {
 113                                 remote-endpoint = <&display_out>;
 114                         };
 115                 };
 116         };
 117 };
 118
 119 &clks {
 120         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 121         assigned-clock-rates = <786432000>;
 122 };
 123
 124 &i2c2 {
 125         clock-frequency = <100000>;
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&pinctrl_i2c2>;
 128         status = "okay";
 129
 130         codec: wm8960@1a {
 131                 #sound-dai-cells = <0>;
 132                 compatible = "wlf,wm8960";
 133                 reg = <0x1a>;
 134                 wlf,shared-lrclk;
 135         };
 136 };
 137
 138 &fec1 {
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&pinctrl_enet1>;
 141         phy-mode = "rmii";
 142         phy-handle = <&ethphy0>;
 143         status = "okay";
 144 };
 145
 146 &fec2 {
 147         pinctrl-names = "default";
 148         pinctrl-0 = <&pinctrl_enet2>;
 149         phy-mode = "rmii";
 150         phy-handle = <&ethphy1>;
 151         status = "okay";
 152
 153         mdio {
 154                 #address-cells = <1>;
 155                 #size-cells = <0>;
 156
 157                 ethphy0: ethernet-phy@2 {
 158                         reg = <2>;
 159                         micrel,led-mode = <1>;
 160                         clocks = <&clks IMX6UL_CLK_ENET_REF>;
 161                         clock-names = "rmii-ref";
 162                 };
 163
 164                 ethphy1: ethernet-phy@1 {
 165                         reg = <1>;
 166                         micrel,led-mode = <1>;
 167                         clocks = <&clks IMX6UL_CLK_ENET2_REF>;
 168                         clock-names = "rmii-ref";
 169                 };
 170         };
 171 };
 172
 173 &can1 {
 174         pinctrl-names = "default";
 175         pinctrl-0 = <&pinctrl_flexcan1>;
 176         xceiver-supply = <&reg_can_3v3>;
 177         status = "okay";
 178 };
 179
 180 &can2 {
 181         pinctrl-names = "default";
 182         pinctrl-0 = <&pinctrl_flexcan2>;
 183         xceiver-supply = <&reg_can_3v3>;
 184         status = "okay";
 185 };
 186
 187 &i2c1 {
 188         clock-frequency = <100000>;
 189         pinctrl-names = "default";
 190         pinctrl-0 = <&pinctrl_i2c1>;
 191         status = "okay";
 192
 193         magnetometer@e {
 194                 compatible = "fsl,mag3110";
 195                 reg = <0x0e>;
 196                 vdd-supply = <&reg_sensors>;
 197                 vddio-supply = <&reg_sensors>;
 198         };
 199 };
 200
 201 &lcdif {
 202         assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
 203         assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_lcdif_dat
 206                      &pinctrl_lcdif_ctrl>;
 207         status = "okay";
 208
 209         port {
 210                 display_out: endpoint {
 211                         remote-endpoint = <&panel_in>;
 212                 };
 213         };
 214 };
 215
 216 &pwm1 {
 217         pinctrl-names = "default";
 218         pinctrl-0 = <&pinctrl_pwm1>;
 219         status = "okay";
 220 };
 221
 222 &qspi {
 223         pinctrl-names = "default";
 224         pinctrl-0 = <&pinctrl_qspi>;
 225         status = "okay";
 226
 227         flash0: n25q256a@0 {
 228                 #address-cells = <1>;
 229                 #size-cells = <1>;
 230                 compatible = "micron,n25q256a";
 231                 spi-max-frequency = <29000000>;
 232                 spi-rx-bus-width = <4>;
 233                 spi-tx-bus-width = <4>;
 234                 reg = <0>;
 235         };
 236 };
 237
 238 &sai2 {
 239         pinctrl-names = "default";
 240         pinctrl-0 = <&pinctrl_sai2>;
 241         assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
 242                           <&clks IMX6UL_CLK_SAI2>;
 243         assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 244         assigned-clock-rates = <0>, <12288000>;
 245         fsl,sai-mclk-direction-output;
 246         status = "okay";
 247 };
 248
 249 &snvs_poweroff {
 250         status = "okay";
 251 };
 252
 253 &snvs_pwrkey {
 254         status = "okay";
 255 };
 256
 257 &tsc {
 258         pinctrl-names = "default";
 259         pinctrl-0 = <&pinctrl_tsc>;
 260         xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 261         measure-delay-time = <0xffff>;
 262         pre-charge-time = <0xfff>;
 263         status = "okay";
 264 };
 265
 266 &uart1 {
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&pinctrl_uart1>;
 269         status = "okay";
 270 };
 271
 272 &uart2 {
 273         pinctrl-names = "default";
 274         pinctrl-0 = <&pinctrl_uart2>;
 275         uart-has-rtscts;
 276         status = "okay";
 277 };
 278
 279 &usbotg1 {
 280         dr_mode = "otg";
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&pinctrl_usb_otg1>;
 283         status = "okay";
 284 };
 285
 286 &usbotg2 {
 287         dr_mode = "host";
 288         disable-over-current;
 289         status = "okay";
 290 };
 291
 292 &usbphy1 {
 293         fsl,tx-d-cal = <106>;
 294 };
 295
 296 &usbphy2 {
 297         fsl,tx-d-cal = <106>;
 298 };
 299
 300 &usdhc1 {
 301         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 302         pinctrl-0 = <&pinctrl_usdhc1>;
 303         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 304         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 305         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 306         keep-power-in-suspend;
 307         wakeup-source;
 308         vmmc-supply = <&reg_sd1_vmmc>;
 309         status = "okay";
 310 };
 311
 312 &usdhc2 {
 313         pinctrl-names = "default";
 314         pinctrl-0 = <&pinctrl_usdhc2>;
 315         no-1-8-v;
 316         keep-power-in-suspend;
 317         wakeup-source;
 318         status = "okay";
 319 };
 320
 321 &wdog1 {
 322         pinctrl-names = "default";
 323         pinctrl-0 = <&pinctrl_wdog>;
 324         fsl,ext-reset-output;
 325 };
 326
 327 &iomuxc {
 328         pinctrl-names = "default";
 329
 330         pinctrl_csi1: csi1grp {
 331                 fsl,pins = <
 332                         MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
 333                         MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
 334                         MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
 335                         MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
 336                         MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
 337                         MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
 338                         MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
 339                         MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
 340                         MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
 341                         MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
 342                         MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
 343                         MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
 344                 >;
 345         };
 346
 347         pinctrl_enet1: enet1grp {
 348                 fsl,pins = <
 349                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 350                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 351                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 352                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 353                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 354                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 355                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 356                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 357                 >;
 358         };
 359
 360         pinctrl_enet2: enet2grp {
 361                 fsl,pins = <
 362                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 363                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 364                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 365                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 366                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 367                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 368                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 369                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 370                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 371                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 372                 >;
 373         };
 374
 375         pinctrl_flexcan1: flexcan1grp{
 376                 fsl,pins = <
 377                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
 378                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
 379                 >;
 380         };
 381
 382         pinctrl_flexcan2: flexcan2grp{
 383                 fsl,pins = <
 384                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
 385                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
 386                 >;
 387         };
 388
 389         pinctrl_i2c1: i2c1grp {
 390                 fsl,pins = <
 391                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 392                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 393                 >;
 394         };
 395
 396         pinctrl_i2c2: i2c2grp {
 397                 fsl,pins = <
 398                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 399                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 400                 >;
 401         };
 402
 403         pinctrl_lcdif_dat: lcdifdatgrp {
 404                 fsl,pins = <
 405                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
 406                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
 407                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
 408                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
 409                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
 410                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
 411                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
 412                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
 413                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
 414                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
 415                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
 416                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
 417                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
 418                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
 419                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
 420                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
 421                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
 422                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
 423                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
 424                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
 425                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
 426                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
 427                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
 428                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
 429                 >;
 430         };
 431
 432         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 433                 fsl,pins = <
 434                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
 435                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
 436                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
 437                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
 438                         /* used for lcd reset */
 439                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
 440                 >;
 441         };
 442
 443         pinctrl_qspi: qspigrp {
 444                 fsl,pins = <
 445                         MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
 446                         MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
 447                         MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
 448                         MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
 449                         MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
 450                         MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
 451                 >;
 452         };
 453
 454         pinctrl_sai2: sai2grp {
 455                 fsl,pins = <
 456                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
 457                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
 458                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
 459                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
 460                         MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
 461                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x17059
 462                 >;
 463         };
 464
 465         pinctrl_sensors_reg: sensorsreggrp {
 466                 fsl,pins = <
 467                         MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0
 468                 >;
 469         };
 470
 471         pinctrl_pwm1: pwm1grp {
 472                 fsl,pins = <
 473                         MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
 474                 >;
 475         };
 476
 477         pinctrl_sim2: sim2grp {
 478                 fsl,pins = <
 479                         MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
 480                         MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
 481                         MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
 482                         MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
 483                         MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
 484                         MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
 485                 >;
 486         };
 487
 488         pinctrl_spi4: spi4grp {
 489                 fsl,pins = <
 490                         MX6UL_PAD_BOOT_MODE0__GPIO5_IO10        0x70a1
 491                         MX6UL_PAD_BOOT_MODE1__GPIO5_IO11        0x70a1
 492                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x70a1
 493                         MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x80000000
 494                 >;
 495         };
 496
 497         pinctrl_tsc: tscgrp {
 498                 fsl,pins = <
 499                         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                0xb0
 500                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0xb0
 501                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0xb0
 502                         MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0xb0
 503                 >;
 504         };
 505
 506         pinctrl_uart1: uart1grp {
 507                 fsl,pins = <
 508                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
 509                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
 510                 >;
 511         };
 512
 513         pinctrl_uart2: uart2grp {
 514                 fsl,pins = <
 515                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
 516                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
 517                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
 518                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
 519                 >;
 520         };
 521
 522         pinctrl_usb_otg1: usbotg1grp {
 523                 fsl,pins = <
 524                         MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
 525                 >;
 526         };
 527
 528         pinctrl_usdhc1: usdhc1grp {
 529                 fsl,pins = <
 530                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 531                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 532                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 533                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 534                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 535                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 536                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
 537                         MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
 538                         MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
 539                 >;
 540         };
 541
 542         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 543                 fsl,pins = <
 544                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 545                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
 546                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
 547                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
 548                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
 549                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
 550
 551                 >;
 552         };
 553
 554         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 555                 fsl,pins = <
 556                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 557                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
 558                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
 559                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
 560                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
 561                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
 562                 >;
 563         };
 564
 565         pinctrl_usdhc2: usdhc2grp {
 566                 fsl,pins = <
 567                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
 568                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
 569                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
 570                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
 571                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
 572                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
 573                 >;
 574         };
 575
 576         pinctrl_wdog: wdoggrp {
 577                 fsl,pins = <
 578                         MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
 579                 >;
 580         };
 581 };