arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         aliases {
  19                 can0 = &can1;
  20                 can1 = &can2;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 gpio5 = &gpio6;
  27                 gpio6 = &gpio7;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 mmc0 = &usdhc1;
  32                 mmc1 = &usdhc2;
  33                 mmc2 = &usdhc3;
  34                 mmc3 = &usdhc4;
  35                 serial0 = &uart1;
  36                 serial1 = &uart2;
  37                 serial2 = &uart3;
  38                 serial3 = &uart4;
  39                 serial4 = &uart5;
  40                 spi0 = &ecspi1;
  41                 spi1 = &ecspi2;
  42                 spi2 = &ecspi3;
  43                 spi3 = &ecspi4;
  44                 usbphy0 = &usbphy1;
  45                 usbphy1 = &usbphy2;
  46         };
  47
  48         intc: interrupt-controller@00a01000 {
  49                 compatible = "arm,cortex-a9-gic";
  50                 #interrupt-cells = <3>;
  51                 interrupt-controller;
  52                 reg = <0x00a01000 0x1000>,
  53                       <0x00a00100 0x100>;
  54         };
  55
  56         clocks {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 ckil {
  61                         compatible = "fsl,imx-ckil", "fixed-clock";
  62                         #clock-cells = <0>;
  63                         clock-frequency = <32768>;
  64                 };
  65
  66                 ckih1 {
  67                         compatible = "fsl,imx-ckih1", "fixed-clock";
  68                         #clock-cells = <0>;
  69                         clock-frequency = <0>;
  70                 };
  71
  72                 osc {
  73                         compatible = "fsl,imx-osc", "fixed-clock";
  74                         #clock-cells = <0>;
  75                         clock-frequency = <24000000>;
  76                 };
  77         };
  78
  79         soc {
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 compatible = "simple-bus";
  83                 interrupt-parent = <&intc>;
  84                 ranges;
  85
  86                 dma_apbh: dma-apbh@00110000 {
  87                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  88                         reg = <0x00110000 0x2000>;
  89                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  90                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  91                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  93                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  94                         #dma-cells = <1>;
  95                         dma-channels = <4>;
  96                         clocks = <&clks 106>;
  97                 };
  98
  99                 gpmi: gpmi-nand@00112000 {
 100                         compatible = "fsl,imx6q-gpmi-nand";
 101                         #address-cells = <1>;
 102                         #size-cells = <1>;
 103                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 104                         reg-names = "gpmi-nand", "bch";
 105                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 106                         interrupt-names = "bch";
 107                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
 108                                  <&clks 150>, <&clks 149>;
 109                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 110                                       "gpmi_bch_apb", "per1_bch";
 111                         dmas = <&dma_apbh 0>;
 112                         dma-names = "rx-tx";
 113                         status = "disabled";
 114                 };
 115
 116                 timer@00a00600 {
 117                         compatible = "arm,cortex-a9-twd-timer";
 118                         reg = <0x00a00600 0x20>;
 119                         interrupts = <1 13 0xf01>;
 120                         clocks = <&clks 15>;
 121                 };
 122
 123                 L2: l2-cache@00a02000 {
 124                         compatible = "arm,pl310-cache";
 125                         reg = <0x00a02000 0x1000>;
 126                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 127                         cache-unified;
 128                         cache-level = <2>;
 129                         arm,tag-latency = <4 2 3>;
 130                         arm,data-latency = <4 2 3>;
 131                 };
 132
 133                 pcie: pcie@0x01000000 {
 134                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 135                         reg = <0x01ffc000 0x4000>; /* DBI */
 136                         #address-cells = <3>;
 137                         #size-cells = <2>;
 138                         device_type = "pci";
 139                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 140                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 141                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 142                         num-lanes = <1>;
 143                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
 144                         #interrupt-cells = <1>;
 145                         interrupt-map-mask = <0 0 0 0x7>;
 146                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 147                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 148                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 149                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 150                         clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
 151                         clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
 152                         status = "disabled";
 153                 };
 154
 155                 pmu {
 156                         compatible = "arm,cortex-a9-pmu";
 157                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 158                 };
 159
 160                 aips-bus@02000000 { /* AIPS1 */
 161                         compatible = "fsl,aips-bus", "simple-bus";
 162                         #address-cells = <1>;
 163                         #size-cells = <1>;
 164                         reg = <0x02000000 0x100000>;
 165                         ranges;
 166
 167                         spba-bus@02000000 {
 168                                 compatible = "fsl,spba-bus", "simple-bus";
 169                                 #address-cells = <1>;
 170                                 #size-cells = <1>;
 171                                 reg = <0x02000000 0x40000>;
 172                                 ranges;
 173
 174                                 spdif: spdif@02004000 {
 175                                         compatible = "fsl,imx35-spdif";
 176                                         reg = <0x02004000 0x4000>;
 177                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 178                                         dmas = <&sdma 14 18 0>,
 179                                                <&sdma 15 18 0>;
 180                                         dma-names = "rx", "tx";
 181                                         clocks = <&clks 197>, <&clks 3>,
 182                                                  <&clks 197>, <&clks 107>,
 183                                                  <&clks 0>,   <&clks 118>,
 184                                                  <&clks 0>,  <&clks 139>,
 185                                                  <&clks 0>;
 186                                         clock-names = "core",  "rxtx0",
 187                                                       "rxtx1", "rxtx2",
 188                                                       "rxtx3", "rxtx4",
 189                                                       "rxtx5", "rxtx6",
 190                                                       "rxtx7";
 191                                         status = "disabled";
 192                                 };
 193
 194                                 ecspi1: ecspi@02008000 {
 195                                         #address-cells = <1>;
 196                                         #size-cells = <0>;
 197                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 198                                         reg = <0x02008000 0x4000>;
 199                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 200                                         clocks = <&clks 112>, <&clks 112>;
 201                                         clock-names = "ipg", "per";
 202                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 203                                         dma-names = "rx", "tx";
 204                                         status = "disabled";
 205                                 };
 206
 207                                 ecspi2: ecspi@0200c000 {
 208                                         #address-cells = <1>;
 209                                         #size-cells = <0>;
 210                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 211                                         reg = <0x0200c000 0x4000>;
 212                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 213                                         clocks = <&clks 113>, <&clks 113>;
 214                                         clock-names = "ipg", "per";
 215                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 216                                         dma-names = "rx", "tx";
 217                                         status = "disabled";
 218                                 };
 219
 220                                 ecspi3: ecspi@02010000 {
 221                                         #address-cells = <1>;
 222                                         #size-cells = <0>;
 223                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 224                                         reg = <0x02010000 0x4000>;
 225                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 226                                         clocks = <&clks 114>, <&clks 114>;
 227                                         clock-names = "ipg", "per";
 228                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 229                                         dma-names = "rx", "tx";
 230                                         status = "disabled";
 231                                 };
 232
 233                                 ecspi4: ecspi@02014000 {
 234                                         #address-cells = <1>;
 235                                         #size-cells = <0>;
 236                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 237                                         reg = <0x02014000 0x4000>;
 238                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 239                                         clocks = <&clks 115>, <&clks 115>;
 240                                         clock-names = "ipg", "per";
 241                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 242                                         dma-names = "rx", "tx";
 243                                         status = "disabled";
 244                                 };
 245
 246                                 uart1: serial@02020000 {
 247                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 248                                         reg = <0x02020000 0x4000>;
 249                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 250                                         clocks = <&clks 160>, <&clks 161>;
 251                                         clock-names = "ipg", "per";
 252                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 253                                         dma-names = "rx", "tx";
 254                                         status = "disabled";
 255                                 };
 256
 257                                 esai: esai@02024000 {
 258                                         reg = <0x02024000 0x4000>;
 259                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 260                                 };
 261
 262                                 ssi1: ssi@02028000 {
 263                                         compatible = "fsl,imx6q-ssi",
 264                                                         "fsl,imx51-ssi",
 265                                                         "fsl,imx21-ssi";
 266                                         reg = <0x02028000 0x4000>;
 267                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 268                                         clocks = <&clks 178>;
 269                                         dmas = <&sdma 37 1 0>,
 270                                                <&sdma 38 1 0>;
 271                                         dma-names = "rx", "tx";
 272                                         fsl,fifo-depth = <15>;
 273                                         fsl,ssi-dma-events = <38 37>;
 274                                         status = "disabled";
 275                                 };
 276
 277                                 ssi2: ssi@0202c000 {
 278                                         compatible = "fsl,imx6q-ssi",
 279                                                         "fsl,imx51-ssi",
 280                                                         "fsl,imx21-ssi";
 281                                         reg = <0x0202c000 0x4000>;
 282                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 283                                         clocks = <&clks 179>;
 284                                         dmas = <&sdma 41 1 0>,
 285                                                <&sdma 42 1 0>;
 286                                         dma-names = "rx", "tx";
 287                                         fsl,fifo-depth = <15>;
 288                                         fsl,ssi-dma-events = <42 41>;
 289                                         status = "disabled";
 290                                 };
 291
 292                                 ssi3: ssi@02030000 {
 293                                         compatible = "fsl,imx6q-ssi",
 294                                                         "fsl,imx51-ssi",
 295                                                         "fsl,imx21-ssi";
 296                                         reg = <0x02030000 0x4000>;
 297                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 298                                         clocks = <&clks 180>;
 299                                         dmas = <&sdma 45 1 0>,
 300                                                <&sdma 46 1 0>;
 301                                         dma-names = "rx", "tx";
 302                                         fsl,fifo-depth = <15>;
 303                                         fsl,ssi-dma-events = <46 45>;
 304                                         status = "disabled";
 305                                 };
 306
 307                                 asrc: asrc@02034000 {
 308                                         reg = <0x02034000 0x4000>;
 309                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 310                                 };
 311
 312                                 spba@0203c000 {
 313                                         reg = <0x0203c000 0x4000>;
 314                                 };
 315                         };
 316
 317                         vpu: vpu@02040000 {
 318                                 reg = <0x02040000 0x3c000>;
 319                                 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
 320                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 321                         };
 322
 323                         aipstz@0207c000 { /* AIPSTZ1 */
 324                                 reg = <0x0207c000 0x4000>;
 325                         };
 326
 327                         pwm1: pwm@02080000 {
 328                                 #pwm-cells = <2>;
 329                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 330                                 reg = <0x02080000 0x4000>;
 331                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 332                                 clocks = <&clks 62>, <&clks 145>;
 333                                 clock-names = "ipg", "per";
 334                         };
 335
 336                         pwm2: pwm@02084000 {
 337                                 #pwm-cells = <2>;
 338                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 339                                 reg = <0x02084000 0x4000>;
 340                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 341                                 clocks = <&clks 62>, <&clks 146>;
 342                                 clock-names = "ipg", "per";
 343                         };
 344
 345                         pwm3: pwm@02088000 {
 346                                 #pwm-cells = <2>;
 347                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 348                                 reg = <0x02088000 0x4000>;
 349                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 350                                 clocks = <&clks 62>, <&clks 147>;
 351                                 clock-names = "ipg", "per";
 352                         };
 353
 354                         pwm4: pwm@0208c000 {
 355                                 #pwm-cells = <2>;
 356                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 357                                 reg = <0x0208c000 0x4000>;
 358                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 359                                 clocks = <&clks 62>, <&clks 148>;
 360                                 clock-names = "ipg", "per";
 361                         };
 362
 363                         can1: flexcan@02090000 {
 364                                 compatible = "fsl,imx6q-flexcan";
 365                                 reg = <0x02090000 0x4000>;
 366                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 367                                 clocks = <&clks 108>, <&clks 109>;
 368                                 clock-names = "ipg", "per";
 369                                 status = "disabled";
 370                         };
 371
 372                         can2: flexcan@02094000 {
 373                                 compatible = "fsl,imx6q-flexcan";
 374                                 reg = <0x02094000 0x4000>;
 375                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 376                                 clocks = <&clks 110>, <&clks 111>;
 377                                 clock-names = "ipg", "per";
 378                                 status = "disabled";
 379                         };
 380
 381                         gpt: gpt@02098000 {
 382                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 383                                 reg = <0x02098000 0x4000>;
 384                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 385                                 clocks = <&clks 119>, <&clks 120>;
 386                                 clock-names = "ipg", "per";
 387                         };
 388
 389                         gpio1: gpio@0209c000 {
 390                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 391                                 reg = <0x0209c000 0x4000>;
 392                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 393                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 394                                 gpio-controller;
 395                                 #gpio-cells = <2>;
 396                                 interrupt-controller;
 397                                 #interrupt-cells = <2>;
 398                         };
 399
 400                         gpio2: gpio@020a0000 {
 401                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 402                                 reg = <0x020a0000 0x4000>;
 403                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 404                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 405                                 gpio-controller;
 406                                 #gpio-cells = <2>;
 407                                 interrupt-controller;
 408                                 #interrupt-cells = <2>;
 409                         };
 410
 411                         gpio3: gpio@020a4000 {
 412                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 413                                 reg = <0x020a4000 0x4000>;
 414                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 415                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 416                                 gpio-controller;
 417                                 #gpio-cells = <2>;
 418                                 interrupt-controller;
 419                                 #interrupt-cells = <2>;
 420                         };
 421
 422                         gpio4: gpio@020a8000 {
 423                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 424                                 reg = <0x020a8000 0x4000>;
 425                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 426                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 427                                 gpio-controller;
 428                                 #gpio-cells = <2>;
 429                                 interrupt-controller;
 430                                 #interrupt-cells = <2>;
 431                         };
 432
 433                         gpio5: gpio@020ac000 {
 434                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 435                                 reg = <0x020ac000 0x4000>;
 436                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 437                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 438                                 gpio-controller;
 439                                 #gpio-cells = <2>;
 440                                 interrupt-controller;
 441                                 #interrupt-cells = <2>;
 442                         };
 443
 444                         gpio6: gpio@020b0000 {
 445                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 446                                 reg = <0x020b0000 0x4000>;
 447                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 448                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 449                                 gpio-controller;
 450                                 #gpio-cells = <2>;
 451                                 interrupt-controller;
 452                                 #interrupt-cells = <2>;
 453                         };
 454
 455                         gpio7: gpio@020b4000 {
 456                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 457                                 reg = <0x020b4000 0x4000>;
 458                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 459                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 460                                 gpio-controller;
 461                                 #gpio-cells = <2>;
 462                                 interrupt-controller;
 463                                 #interrupt-cells = <2>;
 464                         };
 465
 466                         kpp: kpp@020b8000 {
 467                                 reg = <0x020b8000 0x4000>;
 468                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 469                         };
 470
 471                         wdog1: wdog@020bc000 {
 472                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 473                                 reg = <0x020bc000 0x4000>;
 474                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 475                                 clocks = <&clks 0>;
 476                         };
 477
 478                         wdog2: wdog@020c0000 {
 479                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 480                                 reg = <0x020c0000 0x4000>;
 481                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 482                                 clocks = <&clks 0>;
 483                                 status = "disabled";
 484                         };
 485
 486                         clks: ccm@020c4000 {
 487                                 compatible = "fsl,imx6q-ccm";
 488                                 reg = <0x020c4000 0x4000>;
 489                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 490                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 491                                 #clock-cells = <1>;
 492                         };
 493
 494                         anatop: anatop@020c8000 {
 495                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 496                                 reg = <0x020c8000 0x1000>;
 497                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 498                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 499                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 500
 501                                 regulator-1p1@110 {
 502                                         compatible = "fsl,anatop-regulator";
 503                                         regulator-name = "vdd1p1";
 504                                         regulator-min-microvolt = <800000>;
 505                                         regulator-max-microvolt = <1375000>;
 506                                         regulator-always-on;
 507                                         anatop-reg-offset = <0x110>;
 508                                         anatop-vol-bit-shift = <8>;
 509                                         anatop-vol-bit-width = <5>;
 510                                         anatop-min-bit-val = <4>;
 511                                         anatop-min-voltage = <800000>;
 512                                         anatop-max-voltage = <1375000>;
 513                                 };
 514
 515                                 regulator-3p0@120 {
 516                                         compatible = "fsl,anatop-regulator";
 517                                         regulator-name = "vdd3p0";
 518                                         regulator-min-microvolt = <2800000>;
 519                                         regulator-max-microvolt = <3150000>;
 520                                         regulator-always-on;
 521                                         anatop-reg-offset = <0x120>;
 522                                         anatop-vol-bit-shift = <8>;
 523                                         anatop-vol-bit-width = <5>;
 524                                         anatop-min-bit-val = <0>;
 525                                         anatop-min-voltage = <2625000>;
 526                                         anatop-max-voltage = <3400000>;
 527                                 };
 528
 529                                 regulator-2p5@130 {
 530                                         compatible = "fsl,anatop-regulator";
 531                                         regulator-name = "vdd2p5";
 532                                         regulator-min-microvolt = <2000000>;
 533                                         regulator-max-microvolt = <2750000>;
 534                                         regulator-always-on;
 535                                         anatop-reg-offset = <0x130>;
 536                                         anatop-vol-bit-shift = <8>;
 537                                         anatop-vol-bit-width = <5>;
 538                                         anatop-min-bit-val = <0>;
 539                                         anatop-min-voltage = <2000000>;
 540                                         anatop-max-voltage = <2750000>;
 541                                 };
 542
 543                                 reg_arm: regulator-vddcore@140 {
 544                                         compatible = "fsl,anatop-regulator";
 545                                         regulator-name = "vddarm";
 546                                         regulator-min-microvolt = <725000>;
 547                                         regulator-max-microvolt = <1450000>;
 548                                         regulator-always-on;
 549                                         anatop-reg-offset = <0x140>;
 550                                         anatop-vol-bit-shift = <0>;
 551                                         anatop-vol-bit-width = <5>;
 552                                         anatop-delay-reg-offset = <0x170>;
 553                                         anatop-delay-bit-shift = <24>;
 554                                         anatop-delay-bit-width = <2>;
 555                                         anatop-min-bit-val = <1>;
 556                                         anatop-min-voltage = <725000>;
 557                                         anatop-max-voltage = <1450000>;
 558                                 };
 559
 560                                 reg_pu: regulator-vddpu@140 {
 561                                         compatible = "fsl,anatop-regulator";
 562                                         regulator-name = "vddpu";
 563                                         regulator-min-microvolt = <725000>;
 564                                         regulator-max-microvolt = <1450000>;
 565                                         regulator-always-on;
 566                                         anatop-reg-offset = <0x140>;
 567                                         anatop-vol-bit-shift = <9>;
 568                                         anatop-vol-bit-width = <5>;
 569                                         anatop-delay-reg-offset = <0x170>;
 570                                         anatop-delay-bit-shift = <26>;
 571                                         anatop-delay-bit-width = <2>;
 572                                         anatop-min-bit-val = <1>;
 573                                         anatop-min-voltage = <725000>;
 574                                         anatop-max-voltage = <1450000>;
 575                                 };
 576
 577                                 reg_soc: regulator-vddsoc@140 {
 578                                         compatible = "fsl,anatop-regulator";
 579                                         regulator-name = "vddsoc";
 580                                         regulator-min-microvolt = <725000>;
 581                                         regulator-max-microvolt = <1450000>;
 582                                         regulator-always-on;
 583                                         anatop-reg-offset = <0x140>;
 584                                         anatop-vol-bit-shift = <18>;
 585                                         anatop-vol-bit-width = <5>;
 586                                         anatop-delay-reg-offset = <0x170>;
 587                                         anatop-delay-bit-shift = <28>;
 588                                         anatop-delay-bit-width = <2>;
 589                                         anatop-min-bit-val = <1>;
 590                                         anatop-min-voltage = <725000>;
 591                                         anatop-max-voltage = <1450000>;
 592                                 };
 593                         };
 594
 595                         tempmon: tempmon {
 596                                 compatible = "fsl,imx6q-tempmon";
 597                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 598                                 fsl,tempmon = <&anatop>;
 599                                 fsl,tempmon-data = <&ocotp>;
 600                                 clocks = <&clks 172>;
 601                         };
 602
 603                         usbphy1: usbphy@020c9000 {
 604                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 605                                 reg = <0x020c9000 0x1000>;
 606                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 607                                 clocks = <&clks 182>;
 608                                 fsl,anatop = <&anatop>;
 609                         };
 610
 611                         usbphy2: usbphy@020ca000 {
 612                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 613                                 reg = <0x020ca000 0x1000>;
 614                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 615                                 clocks = <&clks 183>;
 616                                 fsl,anatop = <&anatop>;
 617                         };
 618
 619                         snvs@020cc000 {
 620                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 621                                 #address-cells = <1>;
 622                                 #size-cells = <1>;
 623                                 ranges = <0 0x020cc000 0x4000>;
 624
 625                                 snvs-rtc-lp@34 {
 626                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 627                                         reg = <0x34 0x58>;
 628                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 629                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 630                                 };
 631                         };
 632
 633                         epit1: epit@020d0000 { /* EPIT1 */
 634                                 reg = <0x020d0000 0x4000>;
 635                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 636                         };
 637
 638                         epit2: epit@020d4000 { /* EPIT2 */
 639                                 reg = <0x020d4000 0x4000>;
 640                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 641                         };
 642
 643                         src: src@020d8000 {
 644                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 645                                 reg = <0x020d8000 0x4000>;
 646                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 647                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 648                                 #reset-cells = <1>;
 649                         };
 650
 651                         gpc: gpc@020dc000 {
 652                                 compatible = "fsl,imx6q-gpc";
 653                                 reg = <0x020dc000 0x4000>;
 654                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 655                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 656                         };
 657
 658                         gpr: iomuxc-gpr@020e0000 {
 659                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 660                                 reg = <0x020e0000 0x38>;
 661                         };
 662
 663                         iomuxc: iomuxc@020e0000 {
 664                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 665                                 reg = <0x020e0000 0x4000>;
 666                         };
 667
 668                         ldb: ldb@020e0008 {
 669                                 #address-cells = <1>;
 670                                 #size-cells = <0>;
 671                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 672                                 gpr = <&gpr>;
 673                                 status = "disabled";
 674
 675                                 lvds-channel@0 {
 676                                         #address-cells = <1>;
 677                                         #size-cells = <0>;
 678                                         reg = <0>;
 679                                         status = "disabled";
 680
 681                                         port@0 {
 682                                                 reg = <0>;
 683
 684                                                 lvds0_mux_0: endpoint {
 685                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 686                                                 };
 687                                         };
 688
 689                                         port@1 {
 690                                                 reg = <1>;
 691
 692                                                 lvds0_mux_1: endpoint {
 693                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 694                                                 };
 695                                         };
 696                                 };
 697
 698                                 lvds-channel@1 {
 699                                         #address-cells = <1>;
 700                                         #size-cells = <0>;
 701                                         reg = <1>;
 702                                         status = "disabled";
 703
 704                                         port@0 {
 705                                                 reg = <0>;
 706
 707                                                 lvds1_mux_0: endpoint {
 708                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 709                                                 };
 710                                         };
 711
 712                                         port@1 {
 713                                                 reg = <1>;
 714
 715                                                 lvds1_mux_1: endpoint {
 716                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 717                                                 };
 718                                         };
 719                                 };
 720                         };
 721
 722                         hdmi: hdmi@0120000 {
 723                                 #address-cells = <1>;
 724                                 #size-cells = <0>;
 725                                 reg = <0x00120000 0x9000>;
 726                                 interrupts = <0 115 0x04>;
 727                                 gpr = <&gpr>;
 728                                 clocks = <&clks 123>, <&clks 124>;
 729                                 clock-names = "iahb", "isfr";
 730                                 status = "disabled";
 731
 732                                 port@0 {
 733                                         reg = <0>;
 734
 735                                         hdmi_mux_0: endpoint {
 736                                                 remote-endpoint = <&ipu1_di0_hdmi>;
 737                                         };
 738                                 };
 739
 740                                 port@1 {
 741                                         reg = <1>;
 742
 743                                         hdmi_mux_1: endpoint {
 744                                                 remote-endpoint = <&ipu1_di1_hdmi>;
 745                                         };
 746                                 };
 747                         };
 748
 749                         dcic1: dcic@020e4000 {
 750                                 reg = <0x020e4000 0x4000>;
 751                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 752                         };
 753
 754                         dcic2: dcic@020e8000 {
 755                                 reg = <0x020e8000 0x4000>;
 756                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 757                         };
 758
 759                         sdma: sdma@020ec000 {
 760                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 761                                 reg = <0x020ec000 0x4000>;
 762                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 763                                 clocks = <&clks 155>, <&clks 155>;
 764                                 clock-names = "ipg", "ahb";
 765                                 #dma-cells = <3>;
 766                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 767                         };
 768                 };
 769
 770                 aips-bus@02100000 { /* AIPS2 */
 771                         compatible = "fsl,aips-bus", "simple-bus";
 772                         #address-cells = <1>;
 773                         #size-cells = <1>;
 774                         reg = <0x02100000 0x100000>;
 775                         ranges;
 776
 777                         caam@02100000 {
 778                                 reg = <0x02100000 0x40000>;
 779                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 780                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 781                         };
 782
 783                         aipstz@0217c000 { /* AIPSTZ2 */
 784                                 reg = <0x0217c000 0x4000>;
 785                         };
 786
 787                         usbotg: usb@02184000 {
 788                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 789                                 reg = <0x02184000 0x200>;
 790                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 791                                 clocks = <&clks 162>;
 792                                 fsl,usbphy = <&usbphy1>;
 793                                 fsl,usbmisc = <&usbmisc 0>;
 794                                 status = "disabled";
 795                         };
 796
 797                         usbh1: usb@02184200 {
 798                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 799                                 reg = <0x02184200 0x200>;
 800                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 801                                 clocks = <&clks 162>;
 802                                 fsl,usbphy = <&usbphy2>;
 803                                 fsl,usbmisc = <&usbmisc 1>;
 804                                 status = "disabled";
 805                         };
 806
 807                         usbh2: usb@02184400 {
 808                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 809                                 reg = <0x02184400 0x200>;
 810                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 811                                 clocks = <&clks 162>;
 812                                 fsl,usbmisc = <&usbmisc 2>;
 813                                 status = "disabled";
 814                         };
 815
 816                         usbh3: usb@02184600 {
 817                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 818                                 reg = <0x02184600 0x200>;
 819                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 820                                 clocks = <&clks 162>;
 821                                 fsl,usbmisc = <&usbmisc 3>;
 822                                 status = "disabled";
 823                         };
 824
 825                         usbmisc: usbmisc@02184800 {
 826                                 #index-cells = <1>;
 827                                 compatible = "fsl,imx6q-usbmisc";
 828                                 reg = <0x02184800 0x200>;
 829                                 clocks = <&clks 162>;
 830                         };
 831
 832                         fec: ethernet@02188000 {
 833                                 compatible = "fsl,imx6q-fec";
 834                                 reg = <0x02188000 0x4000>;
 835                                 interrupts-extended =
 836                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 837                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 838                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 839                                 clock-names = "ipg", "ahb", "ptp";
 840                                 status = "disabled";
 841                         };
 842
 843                         mlb@0218c000 {
 844                                 reg = <0x0218c000 0x4000>;
 845                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 846                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 847                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 848                         };
 849
 850                         usdhc1: usdhc@02190000 {
 851                                 compatible = "fsl,imx6q-usdhc";
 852                                 reg = <0x02190000 0x4000>;
 853                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 854                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
 855                                 clock-names = "ipg", "ahb", "per";
 856                                 bus-width = <4>;
 857                                 status = "disabled";
 858                         };
 859
 860                         usdhc2: usdhc@02194000 {
 861                                 compatible = "fsl,imx6q-usdhc";
 862                                 reg = <0x02194000 0x4000>;
 863                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 864                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
 865                                 clock-names = "ipg", "ahb", "per";
 866                                 bus-width = <4>;
 867                                 status = "disabled";
 868                         };
 869
 870                         usdhc3: usdhc@02198000 {
 871                                 compatible = "fsl,imx6q-usdhc";
 872                                 reg = <0x02198000 0x4000>;
 873                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 874                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
 875                                 clock-names = "ipg", "ahb", "per";
 876                                 bus-width = <4>;
 877                                 status = "disabled";
 878                         };
 879
 880                         usdhc4: usdhc@0219c000 {
 881                                 compatible = "fsl,imx6q-usdhc";
 882                                 reg = <0x0219c000 0x4000>;
 883                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 884                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
 885                                 clock-names = "ipg", "ahb", "per";
 886                                 bus-width = <4>;
 887                                 status = "disabled";
 888                         };
 889
 890                         i2c1: i2c@021a0000 {
 891                                 #address-cells = <1>;
 892                                 #size-cells = <0>;
 893                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 894                                 reg = <0x021a0000 0x4000>;
 895                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 896                                 clocks = <&clks 125>;
 897                                 status = "disabled";
 898                         };
 899
 900                         i2c2: i2c@021a4000 {
 901                                 #address-cells = <1>;
 902                                 #size-cells = <0>;
 903                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 904                                 reg = <0x021a4000 0x4000>;
 905                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 906                                 clocks = <&clks 126>;
 907                                 status = "disabled";
 908                         };
 909
 910                         i2c3: i2c@021a8000 {
 911                                 #address-cells = <1>;
 912                                 #size-cells = <0>;
 913                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 914                                 reg = <0x021a8000 0x4000>;
 915                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 916                                 clocks = <&clks 127>;
 917                                 status = "disabled";
 918                         };
 919
 920                         romcp@021ac000 {
 921                                 reg = <0x021ac000 0x4000>;
 922                         };
 923
 924                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 925                                 compatible = "fsl,imx6q-mmdc";
 926                                 reg = <0x021b0000 0x4000>;
 927                         };
 928
 929                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 930                                 reg = <0x021b4000 0x4000>;
 931                         };
 932
 933                         weim: weim@021b8000 {
 934                                 compatible = "fsl,imx6q-weim";
 935                                 reg = <0x021b8000 0x4000>;
 936                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 937                                 clocks = <&clks 196>;
 938                         };
 939
 940                         ocotp: ocotp@021bc000 {
 941                                 compatible = "fsl,imx6q-ocotp", "syscon";
 942                                 reg = <0x021bc000 0x4000>;
 943                         };
 944
 945                         tzasc@021d0000 { /* TZASC1 */
 946                                 reg = <0x021d0000 0x4000>;
 947                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 948                         };
 949
 950                         tzasc@021d4000 { /* TZASC2 */
 951                                 reg = <0x021d4000 0x4000>;
 952                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 953                         };
 954
 955                         audmux: audmux@021d8000 {
 956                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 957                                 reg = <0x021d8000 0x4000>;
 958                                 status = "disabled";
 959                         };
 960
 961                         mipi_csi: mipi@021dc000 {
 962                                 reg = <0x021dc000 0x4000>;
 963                         };
 964
 965                         mipi_dsi: mipi@021e0000 {
 966                                 #address-cells = <1>;
 967                                 #size-cells = <0>;
 968                                 reg = <0x021e0000 0x4000>;
 969                                 status = "disabled";
 970
 971                                 port@0 {
 972                                         reg = <0>;
 973
 974                                         mipi_mux_0: endpoint {
 975                                                 remote-endpoint = <&ipu1_di0_mipi>;
 976                                         };
 977                                 };
 978
 979                                 port@1 {
 980                                         reg = <1>;
 981
 982                                         mipi_mux_1: endpoint {
 983                                                 remote-endpoint = <&ipu1_di1_mipi>;
 984                                         };
 985                                 };
 986                         };
 987
 988                         vdoa@021e4000 {
 989                                 reg = <0x021e4000 0x4000>;
 990                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 991                         };
 992
 993                         uart2: serial@021e8000 {
 994                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 995                                 reg = <0x021e8000 0x4000>;
 996                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 997                                 clocks = <&clks 160>, <&clks 161>;
 998                                 clock-names = "ipg", "per";
 999                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1000                                 dma-names = "rx", "tx";
1001                                 status = "disabled";
1002                         };
1003
1004                         uart3: serial@021ec000 {
1005                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1006                                 reg = <0x021ec000 0x4000>;
1007                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1008                                 clocks = <&clks 160>, <&clks 161>;
1009                                 clock-names = "ipg", "per";
1010                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1011                                 dma-names = "rx", "tx";
1012                                 status = "disabled";
1013                         };
1014
1015                         uart4: serial@021f0000 {
1016                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1017                                 reg = <0x021f0000 0x4000>;
1018                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1019                                 clocks = <&clks 160>, <&clks 161>;
1020                                 clock-names = "ipg", "per";
1021                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1022                                 dma-names = "rx", "tx";
1023                                 status = "disabled";
1024                         };
1025
1026                         uart5: serial@021f4000 {
1027                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1028                                 reg = <0x021f4000 0x4000>;
1029                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1030                                 clocks = <&clks 160>, <&clks 161>;
1031                                 clock-names = "ipg", "per";
1032                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1033                                 dma-names = "rx", "tx";
1034                                 status = "disabled";
1035                         };
1036                 };
1037
1038                 ipu1: ipu@02400000 {
1039                         #address-cells = <1>;
1040                         #size-cells = <0>;
1041                         compatible = "fsl,imx6q-ipu";
1042                         reg = <0x02400000 0x400000>;
1043                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1044                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1045                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1046                         clock-names = "bus", "di0", "di1";
1047                         resets = <&src 2>;
1048
1049                         ipu1_di0: port@2 {
1050                                 #address-cells = <1>;
1051                                 #size-cells = <0>;
1052                                 reg = <2>;
1053
1054                                 ipu1_di0_disp0: endpoint@0 {
1055                                 };
1056
1057                                 ipu1_di0_hdmi: endpoint@1 {
1058                                         remote-endpoint = <&hdmi_mux_0>;
1059                                 };
1060
1061                                 ipu1_di0_mipi: endpoint@2 {
1062                                         remote-endpoint = <&mipi_mux_0>;
1063                                 };
1064
1065                                 ipu1_di0_lvds0: endpoint@3 {
1066                                         remote-endpoint = <&lvds0_mux_0>;
1067                                 };
1068
1069                                 ipu1_di0_lvds1: endpoint@4 {
1070                                         remote-endpoint = <&lvds1_mux_0>;
1071                                 };
1072                         };
1073
1074                         ipu1_di1: port@3 {
1075                                 #address-cells = <1>;
1076                                 #size-cells = <0>;
1077                                 reg = <3>;
1078
1079                                 ipu1_di0_disp1: endpoint@0 {
1080                                 };
1081
1082                                 ipu1_di1_hdmi: endpoint@1 {
1083                                         remote-endpoint = <&hdmi_mux_1>;
1084                                 };
1085
1086                                 ipu1_di1_mipi: endpoint@2 {
1087                                         remote-endpoint = <&mipi_mux_1>;
1088                                 };
1089
1090                                 ipu1_di1_lvds0: endpoint@3 {
1091                                         remote-endpoint = <&lvds0_mux_1>;
1092                                 };
1093
1094                                 ipu1_di1_lvds1: endpoint@4 {
1095                                         remote-endpoint = <&lvds1_mux_1>;
1096                                 };
1097                         };
1098                 };
1099         };
1100 };