arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi

   1 /*
   2  * Copyright (C) 2016-2017 Zodiac Inflight Innovations
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/sound/fsl-imx-audmux.h>
  44
  45 / {
  46         chosen {
  47                 stdout-path = &uart1;
  48         };
  49
  50         aliases {
  51                 mdio-gpio0 = &mdio1;
  52         };
  53
  54         mdio1: mdio {
  55                 compatible = "virtual,mdio-gpio";
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58                 pinctrl-names = "default";
  59                 pinctrl-0 = <&pinctrl_mdio1>;
  60                 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
  61                          &gpio6 4 GPIO_ACTIVE_HIGH>;
  62
  63                 phy: ethernet-phy@0 {
  64                         pinctrl-0 = <&pinctrl_rmii_phy_irq>;
  65                         pinctrl-names = "default";
  66                         reg = <0>;
  67                         interrupt-parent = <&gpio3>;
  68                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
  69                 };
  70         };
  71
  72         reg_28p0v: regulator-28p0v {
  73                 compatible = "regulator-fixed";
  74                 regulator-name = "28V_IN";
  75                 regulator-min-microvolt = <28000000>;
  76                 regulator-max-microvolt = <28000000>;
  77                 regulator-always-on;
  78         };
  79
  80         reg_12p0v: regulator-12p0v {
  81                 compatible = "regulator-fixed";
  82                 vin-supply = <&reg_28p0v>;
  83                 regulator-name = "12V_MAIN";
  84                 regulator-min-microvolt = <12000000>;
  85                 regulator-max-microvolt = <12000000>;
  86                 regulator-always-on;
  87         };
  88
  89         reg_5p0v_main: regulator-5p0v-main {
  90                 compatible = "regulator-fixed";
  91                 vin-supply = <&reg_12p0v>;
  92                 regulator-name = "5V_MAIN";
  93                 regulator-min-microvolt = <5000000>;
  94                 regulator-max-microvolt = <5000000>;
  95                 regulator-always-on;
  96         };
  97
  98         reg_5p0v_user_usb: regulator-5p0v-user-usb {
  99                 compatible = "regulator-fixed";
 100                 pinctrl-names = "default";
 101                 pinctrl-0 = <&pinctrl_reg_user_usb>;
 102                 vin-supply = <&reg_5p0v_main>;
 103                 regulator-name = "5V_USER_USB";
 104                 regulator-min-microvolt = <5000000>;
 105                 regulator-max-microvolt = <5000000>;
 106                 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
 107                 startup-delay-us = <1000>;
 108         };
 109
 110         reg_3p3v_pmic: regulator-3p3v-pmic {
 111                 compatible = "regulator-fixed";
 112                 vin-supply = <&reg_12p0v>;
 113                 regulator-name = "PMIC_3V3";
 114                 regulator-min-microvolt = <3300000>;
 115                 regulator-max-microvolt = <3300000>;
 116                 regulator-always-on;
 117         };
 118
 119         reg_3p3v: regulator-3p3v {
 120                 compatible = "regulator-fixed";
 121                 vin-supply = <&reg_3p3v_pmic>;
 122                 regulator-name = "GEN_3V3";
 123                 regulator-min-microvolt = <3300000>;
 124                 regulator-max-microvolt = <3300000>;
 125                 regulator-always-on;
 126         };
 127
 128         reg_3p3v_sd: regulator-3p3v-sd {
 129                 compatible = "regulator-fixed";
 130                 pinctrl-names = "default";
 131                 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
 132                 vin-supply = <&reg_3p3v>;
 133                 regulator-name = "3V3_SD";
 134                 regulator-min-microvolt = <3300000>;
 135                 regulator-max-microvolt = <3300000>;
 136                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
 137                 startup-delay-us = <1000>;
 138                 enable-active-high;
 139                 regulator-always-on;
 140         };
 141
 142         reg_3p3v_display: regulator-3p3v-display {
 143                 compatible = "regulator-fixed";
 144                 vin-supply = <&reg_12p0v>;
 145                 regulator-name = "3V3_DISPLAY";
 146                 regulator-min-microvolt = <3300000>;
 147                 regulator-max-microvolt = <3300000>;
 148                 regulator-always-on;
 149         };
 150
 151         reg_3p3v_ssd: regulator-3p3v-ssd {
 152                 compatible = "regulator-fixed";
 153                 vin-supply = <&reg_12p0v>;
 154                 regulator-name = "3V3_SSD";
 155                 regulator-min-microvolt = <3300000>;
 156                 regulator-max-microvolt = <3300000>;
 157                 regulator-always-on;
 158         };
 159
 160         sound1 {
 161                 compatible = "simple-audio-card";
 162                 simple-audio-card,name = "Front";
 163                 simple-audio-card,format = "i2s";
 164                 simple-audio-card,bitclock-master = <&sound1_codec>;
 165                 simple-audio-card,frame-master = <&sound1_codec>;
 166                 simple-audio-card,widgets =
 167                         "Headphone", "Headphone Jack";
 168                 simple-audio-card,routing =
 169                         "Headphone Jack", "HPLEFT",
 170                         "Headphone Jack", "HPRIGHT",
 171                         "LEFTIN", "HPL",
 172                         "RIGHTIN", "HPR";
 173                 simple-audio-card,aux-devs = <&hpa1>;
 174
 175                 sound1_cpu: simple-audio-card,cpu {
 176                         sound-dai = <&ssi2>;
 177                 };
 178
 179                 sound1_codec: simple-audio-card,codec {
 180                         sound-dai = <&codec1>;
 181                         clocks = <&cs2000>;
 182                 };
 183         };
 184
 185         sound2 {
 186                 compatible = "simple-audio-card";
 187                 simple-audio-card,name = "Back";
 188                 simple-audio-card,format = "i2s";
 189                 simple-audio-card,bitclock-master = <&sound2_codec>;
 190                 simple-audio-card,frame-master = <&sound2_codec>;
 191                 simple-audio-card,widgets =
 192                         "Headphone", "Headphone Jack";
 193                 simple-audio-card,routing =
 194                         "Headphone Jack", "HPLEFT",
 195                         "Headphone Jack", "HPRIGHT",
 196                         "LEFTIN", "HPL",
 197                         "RIGHTIN", "HPR";
 198                 simple-audio-card,aux-devs = <&hpa2>;
 199
 200                 sound2_cpu: simple-audio-card,cpu {
 201                         sound-dai = <&ssi1>;
 202                 };
 203
 204                 sound2_codec: simple-audio-card,codec {
 205                         sound-dai = <&codec2>;
 206                         clocks = <&cs2000>;
 207                 };
 208         };
 209
 210         panel {
 211                 power-supply = <&reg_3p3v_display>;
 212                 status = "disabled";
 213
 214                 port {
 215                         panel_in: endpoint {
 216                                 remote-endpoint = <&lvds0_out>;
 217                         };
 218                 };
 219         };
 220
 221         disp0: disp0 {
 222                 #address-cells = <1>;
 223                 #size-cells = <0>;
 224                 compatible = "fsl,imx-parallel-display";
 225                 pinctrl-names = "default";
 226                 pinctrl-0 = <&pinctrl_disp0>;
 227                 status = "disabled";
 228
 229                 port@0 {
 230                         reg = <0>;
 231
 232                         disp0_in_0: endpoint {
 233                                 remote-endpoint = <&ipu1_di0_disp0>;
 234                         };
 235                 };
 236
 237                 port@1 {
 238                         reg = <1>;
 239
 240                         disp0_out: endpoint {
 241                                 remote-endpoint = <&tc358767_in>;
 242                         };
 243                 };
 244         };
 245
 246         cs2000_ref: cs2000-ref {
 247                 compatible = "fixed-clock";
 248                 #clock-cells = <0>;
 249                 clock-frequency = <24576000>;
 250         };
 251
 252         cs2000_in_dummy: cs2000-in-dummy {
 253                 compatible = "fixed-clock";
 254                 #clock-cells = <0>;
 255                 clock-frequency = <0>;
 256         };
 257
 258         edp_refclk: edp-refclk {
 259                 compatible = "fixed-clock";
 260                 #clock-cells = <0>;
 261                 clock-frequency = <19200000>;
 262         };
 263 };
 264
 265 &reg_arm {
 266         vin-supply = <&sw1a_reg>;
 267 };
 268
 269 &reg_pu {
 270         vin-supply = <&sw1c_reg>;
 271 };
 272
 273 &reg_soc {
 274         vin-supply = <&sw1c_reg>;
 275 };
 276
 277 &ldb {
 278         lvds-channel@0 {
 279                 port@4 {
 280                         reg = <4>;
 281
 282                         lvds0_out: endpoint {
 283                                 remote-endpoint = <&panel_in>;
 284                         };
 285                 };
 286         };
 287 };
 288
 289 &uart1 {
 290         pinctrl-names = "default";
 291         pinctrl-0 = <&pinctrl_uart1>;
 292         status = "okay";
 293 };
 294
 295 &uart3 {
 296         pinctrl-names = "default";
 297         pinctrl-0 = <&pinctrl_uart3>;
 298         uart-has-rtscts;
 299         linux,rs485-enabled-at-boot-time;
 300         status = "okay";
 301 };
 302
 303 &uart4 {
 304         pinctrl-names = "default";
 305         pinctrl-0 = <&pinctrl_uart4>;
 306         status = "okay";
 307 };
 308
 309 &ecspi1 {
 310         pinctrl-names = "default";
 311         pinctrl-0 = <&pinctrl_ecspi1>;
 312         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
 313         status = "okay";
 314
 315         flash@0 {
 316                 compatible = "st,m25p128", "jedec,spi-nor";
 317                 spi-max-frequency = <20000000>;
 318                 reg = <0>;
 319         };
 320 };
 321
 322 &i2c1 {
 323         pinctrl-names = "default";
 324         pinctrl-0 = <&pinctrl_i2c1>;
 325         clock-frequency = <100000>;
 326         status = "okay";
 327
 328         codec2: codec@18 {
 329                 compatible = "ti,tlv320dac3100";
 330                 pinctrl-names = "default";
 331                 pinctrl-0 = <&pinctrl_codec2>;
 332                 reg = <0x18>;
 333                 #sound-dai-cells = <0>;
 334                 HPVDD-supply = <&reg_3p3v>;
 335                 SPRVDD-supply = <&reg_3p3v>;
 336                 SPLVDD-supply = <&reg_3p3v>;
 337                 AVDD-supply = <&reg_3p3v>;
 338                 IOVDD-supply = <&reg_3p3v>;
 339                 DVDD-supply = <&vgen4_reg>;
 340                 gpio-reset = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 341         };
 342
 343         accel@1c {
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&pinctrl_accel>;
 346                 compatible = "fsl,mma8451";
 347                 reg = <0x1c>;
 348                 interrupt-parent = <&gpio1>;
 349                 interrupt-names = "int1", "int2";
 350                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>, <20 IRQ_TYPE_LEVEL_LOW>;
 351         };
 352
 353         hpa2: amp@60 {
 354                 compatible = "ti,tpa6130a2";
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&pinctrl_tpa2>;
 357                 reg = <0x60>;
 358                 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 359                 Vdd-supply = <&reg_5p0v_main>;
 360         };
 361
 362         edp-bridge@68 {
 363                 compatible = "toshiba,tc358767";
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&pinctrl_tc358767>;
 366                 reg = <0x68>;
 367                 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 368                 clock-names = "ref";
 369                 clocks = <&edp_refclk>;
 370                 status = "disabled";
 371
 372                 ports {
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375
 376                         port@1 {
 377                                 reg = <1>;
 378
 379                                 tc358767_in: endpoint {
 380                                         remote-endpoint = <&disp0_out>;
 381                                 };
 382                         };
 383                 };
 384         };
 385 };
 386
 387 &i2c2 {
 388         pinctrl-names = "default";
 389         pinctrl-0 = <&pinctrl_i2c2>;
 390         clock-frequency = <100000>;
 391         status = "okay";
 392
 393         pmic@8 {
 394                 compatible = "fsl,pfuze100";
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&pinctrl_pfuze100_irq>;
 397                 reg = <0x08>;
 398                 interrupt-parent = <&gpio7>;
 399                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
 400
 401                 regulators {
 402                         sw1a_reg: sw1ab {
 403                                 regulator-min-microvolt = <300000>;
 404                                 regulator-max-microvolt = <1875000>;
 405                                 regulator-boot-on;
 406                                 regulator-always-on;
 407                                 regulator-ramp-delay = <6250>;
 408                         };
 409
 410                         sw1c_reg: sw1c {
 411                                 regulator-min-microvolt = <300000>;
 412                                 regulator-max-microvolt = <1875000>;
 413                                 regulator-boot-on;
 414                                 regulator-always-on;
 415                                 regulator-ramp-delay = <6250>;
 416                         };
 417
 418                         sw2_reg: sw2 {
 419                                 regulator-min-microvolt = <800000>;
 420                                 regulator-max-microvolt = <3000000>;
 421                                 regulator-boot-on;
 422                                 regulator-always-on;
 423                         };
 424
 425                         sw3a_reg: sw3a {
 426                                 regulator-min-microvolt = <400000>;
 427                                 regulator-max-microvolt = <1500000>;
 428                                 regulator-boot-on;
 429                                 regulator-always-on;
 430                         };
 431
 432                         sw3b_reg: sw3b {
 433                                 regulator-min-microvolt = <400000>;
 434                                 regulator-max-microvolt = <1500000>;
 435                                 regulator-boot-on;
 436                                 regulator-always-on;
 437                         };
 438
 439                         sw4_reg: sw4 {
 440                                 regulator-min-microvolt = <800000>;
 441                                 regulator-max-microvolt = <1800000>;
 442                                 regulator-boot-on;
 443                                 regulator-always-on;
 444                         };
 445
 446                         snvs_reg: vsnvs {
 447                                 regulator-min-microvolt = <1000000>;
 448                                 regulator-max-microvolt = <3000000>;
 449                                 regulator-boot-on;
 450                                 regulator-always-on;
 451                         };
 452
 453                         vref_reg: vrefddr {
 454                                 regulator-boot-on;
 455                                 regulator-always-on;
 456                         };
 457
 458                         vgen2_reg: vgen2 {
 459                                 regulator-min-microvolt = <1000000>;
 460                                 regulator-max-microvolt = <1500000>;
 461                                 regulator-always-on;
 462                         };
 463
 464                         vgen4_reg: vgen4 {
 465                                 regulator-min-microvolt = <1200000>;
 466                                 regulator-max-microvolt = <1800000>;
 467                                 regulator-always-on;
 468                         };
 469
 470                         vgen5_reg: vgen5 {
 471                                 regulator-min-microvolt = <1800000>;
 472                                 regulator-max-microvolt = <2500000>;
 473                                 regulator-always-on;
 474                         };
 475
 476                         vgen6_reg: vgen6 {
 477                                 regulator-min-microvolt = <1800000>;
 478                                 regulator-max-microvolt = <2800000>;
 479                                 regulator-always-on;
 480                         };
 481                 };
 482         };
 483
 484         temp-sense@48 {
 485                 compatible = "national,lm75";
 486                 reg = <0x48>;
 487         };
 488
 489         cs2000: clkgen@4e {
 490                 compatible = "cirrus,cs2000-cp";
 491                 reg = <0x4e>;
 492                 #clock-cells = <0>;
 493                 clock-names = "clk_in", "ref_clk";
 494                 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
 495                 assigned-clocks = <&cs2000>;
 496                 assigned-clock-rates = <24000000>;
 497         };
 498
 499         eeprom@54 {
 500                 compatible = "at,24c128";
 501                 reg = <0x54>;
 502         };
 503
 504         rtc@68 {
 505                 compatible = "dallas,ds1341";
 506                 reg = <0x68>;
 507         };
 508 };
 509
 510 &i2c3 {
 511         pinctrl-names = "default";
 512         pinctrl-0 = <&pinctrl_i2c3>;
 513         clock-frequency = <400000>;
 514         status = "okay";
 515
 516         codec1: codec@18 {
 517                 compatible = "ti,tlv320dac3100";
 518                 pinctrl-names = "default";
 519                 pinctrl-0 = <&pinctrl_codec1>;
 520                 reg = <0x18>;
 521                 #sound-dai-cells = <0>;
 522                 HPVDD-supply = <&reg_3p3v>;
 523                 SPRVDD-supply = <&reg_3p3v>;
 524                 SPLVDD-supply = <&reg_3p3v>;
 525                 AVDD-supply = <&reg_3p3v>;
 526                 IOVDD-supply = <&reg_3p3v>;
 527                 DVDD-supply = <&vgen4_reg>;
 528                 gpio-reset = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 529         };
 530
 531         touchscreen@20 {
 532                 compatible = "syna,rmi4-i2c";
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&pinctrl_ts>;
 535                 reg = <0x20>;
 536                 interrupt-parent = <&gpio1>;
 537                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 538                 vdd-supply = <&reg_5p0v_main>;
 539                 vio-supply = <&reg_3p3v>;
 540
 541                 #address-cells = <1>;
 542                 #size-cells = <0>;
 543
 544                 rmi4-f01@1 {
 545                         reg = <0x1>;
 546                         syna,nosleep-mode = <1>;
 547                 };
 548
 549                 rmi4-f11@11 {
 550                         reg = <0x11>;
 551                         touchscreen-inverted-y;
 552                         touchscreen-swapped-x-y;
 553                         syna,sensor-type = <1>;
 554                 };
 555
 556                 rmi4-f12@12 {
 557                         reg = <0x12>;
 558                         touchscreen-inverted-y;
 559                         touchscreen-swapped-x-y;
 560                         syna,sensor-type = <1>;
 561                 };
 562         };
 563
 564         hpa1: amp@60 {
 565                 compatible = "ti,tpa6130a2";
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&pinctrl_tpa1>;
 568                 reg = <0x60>;
 569                 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 570                 Vdd-supply = <&reg_5p0v_main>;
 571         };
 572 };
 573
 574 &ipu1_di0_disp0 {
 575         remote-endpoint = <&disp0_in_0>;
 576 };
 577
 578 &pcie {
 579         pinctrl-names = "default";
 580         pinctrl-0 = <&pinctrl_pcie>;
 581         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 582         status = "okay";
 583 };
 584
 585 &usdhc2 {
 586         pinctrl-names = "default";
 587         pinctrl-0 = <&pinctrl_usdhc2>;
 588         bus-width = <4>;
 589         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 590         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 591         vmmc-supply = <&reg_3p3v_sd>;
 592         vqmmc-supply = <&reg_3p3v>;
 593         status = "okay";
 594 };
 595
 596 &usdhc3 {
 597         pinctrl-names = "default";
 598         pinctrl-0 = <&pinctrl_usdhc3>;
 599         bus-width = <4>;
 600         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 601         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 602         vmmc-supply = <&reg_3p3v_sd>;
 603         vqmmc-supply = <&reg_3p3v>;
 604         status = "okay";
 605 };
 606
 607 &usdhc4 {
 608         pinctrl-names = "default";
 609         pinctrl-0 = <&pinctrl_usdhc4>;
 610         bus-width = <8>;
 611         vmmc-supply = <&reg_3p3v>;
 612         vqmmc-supply = <&reg_3p3v>;
 613         non-removable;
 614         status = "okay";
 615 };
 616
 617 &sata {
 618         target-supply = <&reg_3p3v_ssd>;
 619         status = "okay";
 620 };
 621
 622 &fec {
 623         pinctrl-names = "default";
 624         pinctrl-0 = <&pinctrl_enet>;
 625         phy-mode = "rmii";
 626         phy-handle = <&phy>;
 627         phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
 628         phy-reset-duration = <100>;
 629         phy-supply = <&reg_3p3v>;
 630         status = "okay";
 631
 632         mdio {
 633                 #address-cells = <1>;
 634                 #size-cells = <0>;
 635                 status = "okay";
 636
 637                 switch: switch@0 {
 638                         compatible = "marvell,mv88e6085";
 639                         pinctrl-0 = <&pinctrl_switch_irq>;
 640                         pinctrl-names = "default";
 641                         #address-cells = <1>;
 642                         #size-cells = <0>;
 643                         reg = <0>;
 644                         dsa,member = <0 0>;
 645                         eeprom-length = <512>;
 646                         interrupt-parent = <&gpio6>;
 647                         interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
 648                         interrupt-controller;
 649                         #interrupt-cells = <2>;
 650
 651                         ports {
 652                                 #address-cells = <1>;
 653                                 #size-cells = <0>;
 654
 655                                 port@0 {
 656                                         reg = <0>;
 657                                         label = "gigabit_proc";
 658                                         phy-handle = <&switchphy0>;
 659                                 };
 660
 661                                 port@1 {
 662                                         reg = <1>;
 663                                         label = "netaux";
 664                                         phy-handle = <&switchphy1>;
 665                                 };
 666
 667                                 port@2 {
 668                                         reg = <2>;
 669                                         label = "cpu";
 670                                         ethernet = <&fec>;
 671
 672                                         fixed-link {
 673                                                 speed = <100>;
 674                                                 full-duplex;
 675                                         };
 676                                 };
 677
 678                                 port@3 {
 679                                         reg = <3>;
 680                                         label = "netright";
 681                                         phy-handle = <&switchphy3>;
 682                                 };
 683
 684                                 port@4 {
 685                                         reg = <4>;
 686                                         label = "netleft";
 687                                         phy-handle = <&switchphy4>;
 688                                 };
 689                         };
 690
 691                         mdio {
 692                                 #address-cells = <1>;
 693                                 #size-cells = <0>;
 694
 695                                 switchphy0: switchphy@0 {
 696                                         reg = <0>;
 697                                         interrupt-parent = <&switch>;
 698                                         interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 699                                 };
 700
 701                                 switchphy1: switchphy@1 {
 702                                         reg = <1>;
 703                                         interrupt-parent = <&switch>;
 704                                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 705                                 };
 706
 707                                 switchphy2: switchphy@2 {
 708                                         reg = <2>;
 709                                         interrupt-parent = <&switch>;
 710                                         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 711                                 };
 712
 713                                 switchphy3: switchphy@3 {
 714                                         reg = <3>;
 715                                         interrupt-parent = <&switch>;
 716                                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 717                                 };
 718
 719                                 switchphy4: switchphy@4 {
 720                                         reg = <4>;
 721                                         interrupt-parent = <&switch>;
 722                                         interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 723                                 };
 724                         };
 725                 };
 726         };
 727 };
 728
 729 &usbh1 {
 730         vbus-supply = <&reg_5p0v_main>;
 731         status = "okay";
 732 };
 733
 734 &usbotg {
 735         vbus-supply = <&reg_5p0v_user_usb>;
 736         disable-over-current;
 737         dr_mode = "host";
 738         status = "okay";
 739 };
 740
 741 &ssi1 {
 742         status = "okay";
 743 };
 744
 745 &ssi2 {
 746         status = "okay";
 747 };
 748
 749 &audmux {
 750         pinctrl-names = "default";
 751         pinctrl-0 = <&pinctrl_audmux>;
 752         status = "okay";
 753
 754         ssi1 {
 755                 fsl,audmux-port = <0>;
 756                 fsl,port-config = <
 757                         (IMX_AUDMUX_V2_PTCR_SYN |
 758                          IMX_AUDMUX_V2_PTCR_TFSEL(2) |
 759                          IMX_AUDMUX_V2_PTCR_TCSEL(2) |
 760                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 761                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 762                         IMX_AUDMUX_V2_PDCR_RXDSEL(2)
 763                 >;
 764         };
 765
 766         aud3 {
 767                 fsl,audmux-port = <2>;
 768                 fsl,port-config = <
 769                         IMX_AUDMUX_V2_PTCR_SYN
 770                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)
 771                 >;
 772         };
 773
 774         ssi2 {
 775                 fsl,audmux-port = <1>;
 776                 fsl,port-config = <
 777                         (IMX_AUDMUX_V2_PTCR_SYN |
 778                          IMX_AUDMUX_V2_PTCR_TFSEL(4) |
 779                          IMX_AUDMUX_V2_PTCR_TCSEL(4) |
 780                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 781                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 782                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 783                 >;
 784         };
 785
 786         aud5 {
 787                 fsl,audmux-port = <4>;
 788                 fsl,port-config = <
 789                         IMX_AUDMUX_V2_PTCR_SYN
 790                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
 791                 >;
 792         };
 793 };
 794
 795 &iomuxc {
 796         pinctrl_accel: accelgrp {
 797                 fsl,pins = <
 798                         MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x4001b000
 799                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x4001b000
 800                 >;
 801         };
 802
 803         pinctrl_audmux: audmuxgrp {
 804                 fsl,pins = <
 805                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0
 806                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x130b0
 807                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0
 808                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 809                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x130b0
 810                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 811                 >;
 812         };
 813
 814         pinctrl_codec1: dac1grp {
 815                 fsl,pins = <
 816                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x40000038
 817                 >;
 818         };
 819
 820         pinctrl_codec2: dac2grp {
 821                 fsl,pins = <
 822                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x40000038
 823                 >;
 824         };
 825
 826         pinctrl_disp0: disp0grp {
 827                 fsl,pins = <
 828                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
 829                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f9
 830                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f9
 831                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f9
 832                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x100f9
 833                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x100f9
 834                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x100f9
 835                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x100f9
 836                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x100f9
 837                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x100f9
 838                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x100f9
 839                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x100f9
 840                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x100f9
 841                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x100f9
 842                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x100f9
 843                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x100f9
 844                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x100f9
 845                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x100f9
 846                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x100f9
 847                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x100f9
 848                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x100f9
 849                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x100f9
 850                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x100f9
 851                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x100f9
 852                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x100f9
 853                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x100f9
 854                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x100f9
 855                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x100f9
 856                 >;
 857         };
 858
 859         pinctrl_ecspi1: ecspi1grp {
 860                 fsl,pins = <
 861                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 862                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 863                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 864                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b1
 865                 >;
 866         };
 867
 868         pinctrl_enet: enetgrp {
 869                 fsl,pins = <
 870                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x000b1
 871                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b1
 872                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x100f5
 873                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x100f5
 874                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x100c0
 875                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x100c0
 876                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x100f5
 877                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x100f5
 878                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x40010040
 879                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x100b0
 880                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 881                 >;
 882         };
 883
 884         pinctrl_i2c1: i2c1grp {
 885                 fsl,pins = <
 886                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 887                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 888                 >;
 889         };
 890
 891         pinctrl_i2c2: i2c2grp {
 892                 fsl,pins = <
 893                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 894                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 895                 >;
 896         };
 897
 898         pinctrl_i2c3: i2c3grp {
 899                 fsl,pins = <
 900                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 901                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 902                 >;
 903         };
 904
 905         pinctrl_mdio1: bitbangmdiogrp {
 906                 fsl,pins = <
 907                         /* Bitbang MDIO for DEB Switch */
 908                         MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05       0x4001b030
 909                         MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04       0x40018830
 910                 >;
 911         };
 912
 913         pinctrl_pcie: pciegrp {
 914                 fsl,pins = <
 915                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x10038
 916                 >;
 917         };
 918
 919         pinctrl_pfuze100_irq: pfuze100grp {
 920                 fsl,pins = <
 921                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x40010000
 922                 >;
 923         };
 924
 925         pinctrl_reg_3p3v_sd: mmcsupply1grp {
 926                 fsl,pins = <
 927                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x858
 928                 >;
 929         };
 930
 931         pinctrl_reg_user_usb: usbotggrp {
 932                 fsl,pins = <
 933                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x40000038
 934                 >;
 935         };
 936
 937         pinctrl_rmii_phy_irq: phygrp {
 938                 fsl,pins = <
 939                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x40010000
 940                 >;
 941         };
 942
 943         pinctrl_switch_irq: switchgrp {
 944                 fsl,pins = <
 945                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x4001b000
 946                 >;
 947         };
 948
 949         pinctrl_tc358767: tc358767grp {
 950                 fsl,pins = <
 951                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x10
 952                 >;
 953         };
 954
 955         pinctrl_tpa1: tpa6130-1grp {
 956                 fsl,pins = <
 957                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x40000038
 958                 >;
 959         };
 960
 961         pinctrl_tpa2: tpa6130-2grp {
 962                 fsl,pins = <
 963                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x40000038
 964                 >;
 965         };
 966
 967         pinctrl_ts: tsgrp {
 968                 fsl,pins = <
 969                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x1b0b0
 970                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
 971                 >;
 972         };
 973
 974         pinctrl_uart1: uart1grp {
 975                 fsl,pins = <
 976                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 977                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 978                 >;
 979         };
 980
 981         pinctrl_uart3: uart3grp {
 982                 fsl,pins = <
 983                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 984                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 985                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 986                 >;
 987         };
 988
 989         pinctrl_uart4: uart4grp {
 990                 fsl,pins = <
 991                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 992                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 993                 >;
 994         };
 995
 996         pinctrl_usdhc2: usdhc2grp {
 997                 fsl,pins = <
 998                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x10059
 999                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
1000                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
1001                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
1002                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
1003                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
1004                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x40010040
1005                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x40010040
1006                 >;
1007         };
1008
1009         pinctrl_usdhc3: usdhc3grp {
1010                 fsl,pins = <
1011                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x10059
1012                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10069
1013                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
1014                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
1015                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
1016                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
1017                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x40010040
1018                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x40010040
1019
1020                 >;
1021         };
1022
1023         pinctrl_usdhc4: usdhc4grp {
1024                 fsl,pins = <
1025                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
1026                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
1027                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
1028                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
1029                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
1030                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
1031                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
1032                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
1033                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
1034                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
1035                         MX6QDL_PAD_NANDF_ALE__SD4_RESET         0x1b0b1
1036                 >;
1037         };
1038 };