1 // SPDX-License-Identifier: (GPL-2.0 or MIT)
3 // Copyright (C) 2018 emtrion GmbH
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/pwm/pwm.h>
8 #include <dt-bindings/input/input.h>
12 model = "emtrion SoM emCON-MX6";
13 compatible = "emtrion,emcon-mx6";
27 device_type = "memory";
28 reg = <0x10000000 0x40000000>;
32 compatible = "gpio-keys";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_emcon_wake>;
38 linux,code = <KEY_WAKEUP>;
39 gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
45 compatible = "gpio-leds";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_som_leds>;
51 gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
52 linux,default-trigger = "heartbeat";
58 gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
59 default-state = "keep";
64 lvds_backlight: lvds-backlight {
65 compatible = "pwm-backlight";
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_lvds_bl>;
68 enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
69 pwms = <&pwm1 0 50000>;
71 0 4 8 16 32 64 80 96 112
74 default-brightness-level = <13>;
79 compatible = "pwm-fan";
80 cooling-min-state = <0>;
81 cooling-max-state = <4>;
83 pwms = <&pwm4 0 50000>;
84 cooling-levels = <0 64 127 191 255>;
89 rgb_encoder: display {
90 compatible = "fsl,imx-parallel-display";
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_rgb24_display>;
100 rgb_encoder_in: endpoint {
101 remote-endpoint = <&ipu1_di0_disp0>;
108 rgb_encoder_out: endpoint {
109 remote-endpoint = <&rgb_panel_in>;
115 backlight = <&rgb_backlight>;
116 power-supply = <®_parallel_disp>;
119 rgb_panel_in: endpoint {
120 remote-endpoint = <&rgb_encoder_out>;
125 reg_parallel_disp: reg-parallel-display {
126 compatible = "regulator-fixed";
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_rgb_bl_en>;
129 regulator-name = "LCD-Supply";
130 regulator-min-microvolt = <5000000>;
131 regulator-max-microvolt = <5000000>;
132 gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;
136 reg_lvds_disp: reg-lvds-display {
137 compatible = "regulator-fixed";
138 regulator-name = "LVDS-Supply";
139 regulator-min-microvolt = <5000000>;
140 regulator-max-microvolt = <5000000>;
141 gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>;
145 rgb_backlight: rgb-backlight {
146 compatible = "pwm-backlight";
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_rgb_bl>;
149 enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
150 pwms = <&pwm3 0 5000000>;
151 brightness-levels = <
152 250 176 160 144 128 112
153 96 80 64 48 32 16 8 1
155 default-brightness-level = <13>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_can1>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_can2>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_ecspi2>;
173 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>,
174 <&gpio2 27 GPIO_ACTIVE_HIGH>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_nor_flash>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_enet>;
186 phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
187 phy-reset-duration = <50>;
188 phy-supply = <&vdd_1V8_reg>;
189 phy-handle = <&ksz9031>;
193 #address-cells = <1>;
197 compatible = "ethernet-phy-ieee802.3-c22";
199 interrupt-parent = <&gpio1>;
200 interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
201 rxdv-skew-ps = <480>;
202 txen-skew-ps = <480>;
203 rxd0-skew-ps = <480>;
204 rxd1-skew-ps = <480>;
205 rxd2-skew-ps = <480>;
206 rxd3-skew-ps = <480>;
207 txd0-skew-ps = <420>;
208 txd1-skew-ps = <420>;
209 txd2-skew-ps = <360>;
210 txd3-skew-ps = <360>;
211 txc-skew-ps = <1020>;
218 clock-frequency = <100000>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_i2c1>;
224 compatible = "dlg,da9063";
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_pmic>;
228 interrupt-parent = <&gpio2>;
229 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
230 interrupt-controller;
233 compatible = "dlg,da9063-onkey";
238 compatible = "dlg,da9063-watchdog";
243 vddcore_reg: bcore1 {
244 regulator-min-microvolt = <1100000>;
245 regulator-max-microvolt = <1450000>;
246 regulator-ramp-delay = <2>;
247 regulator-name = "DA9063_CORE";
252 regulator-min-microvolt = <1100000>;
253 regulator-max-microvolt = <1450000>;
254 regulator-ramp-delay = <2>;
255 regulator-name = "DA9063_SOC";
260 regulator-min-microvolt = <1500000>;
261 regulator-max-microvolt = <1500000>;
262 regulator-ramp-delay = <2>;
267 regulator-min-microvolt = <3300000>;
268 regulator-max-microvolt = <3300000>;
269 regulator-ramp-delay = <2>;
274 regulator-min-microvolt = <2500000>;
275 regulator-max-microvolt = <2500000>;
279 regulator-min-microvolt = <2500000>;
280 regulator-max-microvolt = <2500000>;
284 vdd_mx6_snvs_reg: ldo5 {
285 regulator-min-microvolt = <3300000>;
286 regulator-max-microvolt = <3300000>;
291 regulator-min-microvolt = <2500000>;
292 regulator-max-microvolt = <2500000>;
298 regulator-min-microvolt = <2500000>;
299 regulator-max-microvolt = <2500000>;
304 regulator-min-microvolt = <1800000>;
305 regulator-max-microvolt = <1800000>;
309 vdd_3V3_sdc_reg: ldo9 {
310 regulator-min-microvolt = <1800000>;
311 regulator-max-microvolt = <3300000>;
316 regulator-min-microvolt = <1200000>;
317 regulator-max-microvolt = <1200000>;
324 compatible = "dallas,ds1307";
330 clock-frequency = <100000>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_i2c2>;
337 pinctrl_audmux: audmuxgrp {
339 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
340 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060
341 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0
342 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060
346 pinctrl_can1: can1grp {
348 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
349 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
353 pinctrl_can2: can2grp {
355 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1
356 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1
360 pinctrl_cpi1: csi0grp {
362 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
363 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1
364 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1
365 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1
366 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1
367 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1
368 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1
369 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1
370 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1
371 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1
372 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1
376 /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/
378 pinctrl_ecspi2: ecspi2grp {
380 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
381 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
382 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
383 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1
384 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
388 pinctrl_emcon_gpio1: emcongpio1 {
390 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1
394 pinctrl_emcon_gpio2: emcongpio2 {
396 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1
400 pinctrl_emcon_gpio3: emcongpio3 {
402 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1
406 pinctrl_emcon_gpio4: emcongpio4 {
408 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1
412 pinctrl_emcon_gpio5: emcongpio5 {
414 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1
418 pinctrl_emcon_gpio6: emcongpio6 {
420 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1
424 pinctrl_emcon_gpio7: emcongpio7 {
426 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1
430 pinctrl_emcon_gpio8: emcongpio8 {
432 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1
436 pinctrl_emcon_irq_a: emconirqa {
438 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1
442 pinctrl_emcon_irq_b: emconirqb {
444 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1
448 pinctrl_emcon_irq_c: emconirqc {
450 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1
454 pinctrl_emcon_irq_pwr: emconirqpwr {
456 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1
460 pinctrl_emcon_wake: emconwake {
462 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1
466 pinctrl_enet: enetgrp {
468 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030
469 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030
470 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
471 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
472 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
473 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
474 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
475 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
476 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1
477 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
478 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
479 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
480 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
481 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
482 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
483 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058
484 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
488 pinctrl_i2c1: i2c1grp {
490 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
491 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
495 pinctrl_i2c2: i2c2grp {
497 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
498 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
502 pinctrl_i2c3: i2c3grp {
504 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070
505 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870
509 pinctrl_irq_touch1: irqtouch1 {
511 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1
515 pinctrl_irq_touch2: irqtouch2 {
517 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1
521 pinctrl_lvds_bl: lvdsbacklightgrp {
523 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1
524 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1
528 pinctrl_lvds_reg: lvdsreggrp {
530 MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1
535 pinctrl_nor_flash: norflashgrp {
537 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1
538 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
539 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
540 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
541 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
545 pinctrl_pcie_ctrl: pciegrp {
547 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1
548 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1
552 pinctrl_pmic: pmicgrp {
554 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1
558 pinctrl_pwm_fan: pwmfan {
560 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1
564 pinctrl_rgb_bl: rgbbacklightgrp {
566 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1
567 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1
571 pinctrl_rgb_bl_en: rgbenable {
573 MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1
577 pinctrl_rgb24_display: rgbgrp {
579 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
580 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
581 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
582 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
583 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
584 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
585 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
586 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
587 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
588 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
589 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
590 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
591 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
592 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
593 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
594 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
595 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
596 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
597 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
598 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
599 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
600 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
601 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
602 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
603 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
604 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
605 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
606 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
610 pinctrl_secure: securegrp {
612 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
616 pinctrl_som_leds: somledgrp {
618 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1
619 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1
623 pinctrl_spdif_in: spdifin {
625 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
629 pinctrl_spdif_out: spdifout {
631 MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
635 pinctrl_uart1: uart1grp {
637 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
638 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
642 pinctrl_uart2: uart2grp {
644 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
645 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
646 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
647 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
651 pinctrl_uart3: uart3grp {
653 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
654 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
658 pinctrl_uart4: uart4grp {
660 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
661 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
665 pinctrl_uart5: uart5grp {
667 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
668 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
672 pinctrl_usb_host1: usbhgrp {
674 MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058
675 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058
679 pinctrl_usb_otg: usbotggrp {
681 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
682 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059
683 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059
687 pinctrl_usdhc1: usdhc1grp {
689 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
690 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
691 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
692 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
693 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
694 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
695 MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1
696 MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1
700 pinctrl_usdhc2: usdhc2grp {
702 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
703 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
704 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
705 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
706 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
707 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
708 MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1
709 MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1
713 pinctrl_usdhc3: usdhc3grp {
715 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
716 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
717 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
718 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
719 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
720 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
721 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
722 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
723 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
724 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
725 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
731 remote-endpoint = <&rgb_encoder_in>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&pinctrl_pcie_ctrl>;
737 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
738 disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>;
754 pinctrl-names = "default";
755 pinctrl-0 = <&pinctrl_uart1>;
760 pinctrl-names = "default";
761 pinctrl-0 = <&pinctrl_uart2>;
765 pinctrl-names = "default";
766 pinctrl-0 = <&pinctrl_uart3>;
770 pinctrl-names = "default";
771 pinctrl-0 = <&pinctrl_uart4>;
775 pinctrl-names = "default";
776 pinctrl-0 = <&pinctrl_uart5>;
780 pinctrl-names = "default";
781 pinctrl-0 = <&pinctrl_usb_host1>;
785 pinctrl-names = "default";
786 pinctrl-0 = <&pinctrl_usb_otg>;
787 vbus-supply = <®_usb_otg>;
788 dr_mode = "peripheral";
792 pinctrl-names = "default";
793 pinctrl-0 = <&pinctrl_usdhc1>;
798 pinctrl-names = "default";
799 pinctrl-0 = <&pinctrl_usdhc2>;
804 pinctrl-names = "default";
805 pinctrl-0 = <&pinctrl_usdhc3>;
811 /******device power Management*********/
814 voltage-tolerance = <2>;
818 vin-supply = <&vddcore_reg>;
822 vin-supply = <&vddsoc_reg>;
826 vin-supply = <&vddsoc_reg>;
829 /*******Disabled HW following***********/