arch/arm/boot/dts/imx6q.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6q-pinfunc.h"
   7 #include "imx6qdl.dtsi"
   8
   9 / {
  10         aliases {
  11                 ipu1 = &ipu2;
  12                 spi4 = &ecspi5;
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                         operating-points = <
  25                                 /* kHz    uV */
  26                                 1200000 1275000
  27                                 996000  1250000
  28                                 852000  1250000
  29                                 792000  1175000
  30                                 396000  975000
  31                         >;
  32                         fsl,soc-operating-points = <
  33                                 /* ARM kHz  SOC-PU uV */
  34                                 1200000 1275000
  35                                 996000  1250000
  36                                 852000  1250000
  37                                 792000  1175000
  38                                 396000  1175000
  39                         >;
  40                         clock-latency = <61036>; /* two CLK32 periods */
  41                         #cooling-cells = <2>;
  42                         clocks = <&clks IMX6QDL_CLK_ARM>,
  43                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  44                                  <&clks IMX6QDL_CLK_STEP>,
  45                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  46                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  47                         clock-names = "arm", "pll2_pfd2_396m", "step",
  48                                       "pll1_sw", "pll1_sys";
  49                         arm-supply = <&reg_arm>;
  50                         pu-supply = <&reg_pu>;
  51                         soc-supply = <&reg_soc>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         compatible = "arm,cortex-a9";
  56                         device_type = "cpu";
  57                         reg = <1>;
  58                         next-level-cache = <&L2>;
  59                         operating-points = <
  60                                 /* kHz    uV */
  61                                 1200000 1275000
  62                                 996000  1250000
  63                                 852000  1250000
  64                                 792000  1175000
  65                                 396000  975000
  66                         >;
  67                         fsl,soc-operating-points = <
  68                                 /* ARM kHz  SOC-PU uV */
  69                                 1200000 1275000
  70                                 996000  1250000
  71                                 852000  1250000
  72                                 792000  1175000
  73                                 396000  1175000
  74                         >;
  75                         clock-latency = <61036>; /* two CLK32 periods */
  76                         clocks = <&clks IMX6QDL_CLK_ARM>,
  77                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  78                                  <&clks IMX6QDL_CLK_STEP>,
  79                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  80                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  81                         clock-names = "arm", "pll2_pfd2_396m", "step",
  82                                       "pll1_sw", "pll1_sys";
  83                         arm-supply = <&reg_arm>;
  84                         pu-supply = <&reg_pu>;
  85                         soc-supply = <&reg_soc>;
  86                 };
  87
  88                 cpu2: cpu@2 {
  89                         compatible = "arm,cortex-a9";
  90                         device_type = "cpu";
  91                         reg = <2>;
  92                         next-level-cache = <&L2>;
  93                         operating-points = <
  94                                 /* kHz    uV */
  95                                 1200000 1275000
  96                                 996000  1250000
  97                                 852000  1250000
  98                                 792000  1175000
  99                                 396000  975000
 100                         >;
 101                         fsl,soc-operating-points = <
 102                                 /* ARM kHz  SOC-PU uV */
 103                                 1200000 1275000
 104                                 996000  1250000
 105                                 852000  1250000
 106                                 792000  1175000
 107                                 396000  1175000
 108                         >;
 109                         clock-latency = <61036>; /* two CLK32 periods */
 110                         clocks = <&clks IMX6QDL_CLK_ARM>,
 111                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 112                                  <&clks IMX6QDL_CLK_STEP>,
 113                                  <&clks IMX6QDL_CLK_PLL1_SW>,
 114                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
 115                         clock-names = "arm", "pll2_pfd2_396m", "step",
 116                                       "pll1_sw", "pll1_sys";
 117                         arm-supply = <&reg_arm>;
 118                         pu-supply = <&reg_pu>;
 119                         soc-supply = <&reg_soc>;
 120                 };
 121
 122                 cpu3: cpu@3 {
 123                         compatible = "arm,cortex-a9";
 124                         device_type = "cpu";
 125                         reg = <3>;
 126                         next-level-cache = <&L2>;
 127                         operating-points = <
 128                                 /* kHz    uV */
 129                                 1200000 1275000
 130                                 996000  1250000
 131                                 852000  1250000
 132                                 792000  1175000
 133                                 396000  975000
 134                         >;
 135                         fsl,soc-operating-points = <
 136                                 /* ARM kHz  SOC-PU uV */
 137                                 1200000 1275000
 138                                 996000  1250000
 139                                 852000  1250000
 140                                 792000  1175000
 141                                 396000  1175000
 142                         >;
 143                         clock-latency = <61036>; /* two CLK32 periods */
 144                         clocks = <&clks IMX6QDL_CLK_ARM>,
 145                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 146                                  <&clks IMX6QDL_CLK_STEP>,
 147                                  <&clks IMX6QDL_CLK_PLL1_SW>,
 148                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
 149                         clock-names = "arm", "pll2_pfd2_396m", "step",
 150                                       "pll1_sw", "pll1_sys";
 151                         arm-supply = <&reg_arm>;
 152                         pu-supply = <&reg_pu>;
 153                         soc-supply = <&reg_soc>;
 154                 };
 155         };
 156
 157         soc {
 158                 ocram: sram@900000 {
 159                         compatible = "mmio-sram";
 160                         reg = <0x00900000 0x40000>;
 161                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
 162                 };
 163
 164                 aips-bus@2000000 { /* AIPS1 */
 165                         spba-bus@2000000 {
 166                                 ecspi5: spi@2018000 {
 167                                         #address-cells = <1>;
 168                                         #size-cells = <0>;
 169                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 170                                         reg = <0x02018000 0x4000>;
 171                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 172                                         clocks = <&clks IMX6Q_CLK_ECSPI5>,
 173                                                  <&clks IMX6Q_CLK_ECSPI5>;
 174                                         clock-names = "ipg", "per";
 175                                         dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
 176                                         dma-names = "rx", "tx";
 177                                         status = "disabled";
 178                                 };
 179                         };
 180
 181                         iomuxc: iomuxc@20e0000 {
 182                                 compatible = "fsl,imx6q-iomuxc";
 183                         };
 184                 };
 185
 186                 sata: sata@2200000 {
 187                         compatible = "fsl,imx6q-ahci";
 188                         reg = <0x02200000 0x4000>;
 189                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 190                         clocks = <&clks IMX6QDL_CLK_SATA>,
 191                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 192                                  <&clks IMX6QDL_CLK_AHB>;
 193                         clock-names = "sata", "sata_ref", "ahb";
 194                         status = "disabled";
 195                 };
 196
 197                 gpu_vg: gpu@2204000 {
 198                         compatible = "vivante,gc";
 199                         reg = <0x02204000 0x4000>;
 200                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 201                         clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 202                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 203                         clock-names = "bus", "core";
 204                         power-domains = <&pd_pu>;
 205                 };
 206
 207                 ipu2: ipu@2800000 {
 208                         #address-cells = <1>;
 209                         #size-cells = <0>;
 210                         compatible = "fsl,imx6q-ipu";
 211                         reg = <0x02800000 0x400000>;
 212                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 213                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 214                         clocks = <&clks IMX6QDL_CLK_IPU2>,
 215                                  <&clks IMX6QDL_CLK_IPU2_DI0>,
 216                                  <&clks IMX6QDL_CLK_IPU2_DI1>;
 217                         clock-names = "bus", "di0", "di1";
 218                         resets = <&src 4>;
 219
 220                         ipu2_csi0: port@0 {
 221                                 reg = <0>;
 222
 223                                 ipu2_csi0_from_mipi_vc2: endpoint {
 224                                         remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
 225                                 };
 226                         };
 227
 228                         ipu2_csi1: port@1 {
 229                                 reg = <1>;
 230
 231                                 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
 232                                         remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
 233                                 };
 234                         };
 235
 236                         ipu2_di0: port@2 {
 237                                 #address-cells = <1>;
 238                                 #size-cells = <0>;
 239                                 reg = <2>;
 240
 241                                 ipu2_di0_disp0: endpoint@0 {
 242                                         reg = <0>;
 243                                 };
 244
 245                                 ipu2_di0_hdmi: endpoint@1 {
 246                                         reg = <1>;
 247                                         remote-endpoint = <&hdmi_mux_2>;
 248                                 };
 249
 250                                 ipu2_di0_mipi: endpoint@2 {
 251                                         reg = <2>;
 252                                         remote-endpoint = <&mipi_mux_2>;
 253                                 };
 254
 255                                 ipu2_di0_lvds0: endpoint@3 {
 256                                         reg = <3>;
 257                                         remote-endpoint = <&lvds0_mux_2>;
 258                                 };
 259
 260                                 ipu2_di0_lvds1: endpoint@4 {
 261                                         reg = <4>;
 262                                         remote-endpoint = <&lvds1_mux_2>;
 263                                 };
 264                         };
 265
 266                         ipu2_di1: port@3 {
 267                                 #address-cells = <1>;
 268                                 #size-cells = <0>;
 269                                 reg = <3>;
 270
 271                                 ipu2_di1_hdmi: endpoint@1 {
 272                                         reg = <1>;
 273                                         remote-endpoint = <&hdmi_mux_3>;
 274                                 };
 275
 276                                 ipu2_di1_mipi: endpoint@2 {
 277                                         reg = <2>;
 278                                         remote-endpoint = <&mipi_mux_3>;
 279                                 };
 280
 281                                 ipu2_di1_lvds0: endpoint@3 {
 282                                         reg = <3>;
 283                                         remote-endpoint = <&lvds0_mux_3>;
 284                                 };
 285
 286                                 ipu2_di1_lvds1: endpoint@4 {
 287                                         reg = <4>;
 288                                         remote-endpoint = <&lvds1_mux_3>;
 289                                 };
 290                         };
 291                 };
 292         };
 293
 294         capture-subsystem {
 295                 compatible = "fsl,imx-capture-subsystem";
 296                 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
 297         };
 298
 299         display-subsystem {
 300                 compatible = "fsl,imx-display-subsystem";
 301                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 302         };
 303 };
 304
 305 &gpio1 {
 306         gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
 307                       <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
 308                       <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
 309                       <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
 310                       <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
 311                       <&iomuxc 22 116 10>;
 312 };
 313
 314 &gpio2 {
 315         gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
 316                       <&iomuxc 31  44  1>;
 317 };
 318
 319 &gpio3 {
 320         gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
 321 };
 322
 323 &gpio4 {
 324         gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
 325 };
 326
 327 &gpio5 {
 328         gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
 329                       <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
 330 };
 331
 332 &gpio6 {
 333         gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
 334                       <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
 335                       <&iomuxc 31  86 1>;
 336 };
 337
 338 &gpio7 {
 339         gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
 340 };
 341
 342 &gpr {
 343         ipu1_csi0_mux {
 344                 compatible = "video-mux";
 345                 mux-controls = <&mux 0>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348
 349                 port@0 {
 350                         reg = <0>;
 351
 352                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 353                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 354                         };
 355                 };
 356
 357                 port@1 {
 358                         reg = <1>;
 359
 360                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 361                         };
 362                 };
 363
 364                 port@2 {
 365                         reg = <2>;
 366
 367                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 368                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 369                         };
 370                 };
 371         };
 372
 373         ipu2_csi1_mux {
 374                 compatible = "video-mux";
 375                 mux-controls = <&mux 1>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378
 379                 port@0 {
 380                         reg = <0>;
 381
 382                         ipu2_csi1_mux_from_mipi_vc3: endpoint {
 383                                 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
 384                         };
 385                 };
 386
 387                 port@1 {
 388                         reg = <1>;
 389
 390                         ipu2_csi1_mux_from_parallel_sensor: endpoint {
 391                         };
 392                 };
 393
 394                 port@2 {
 395                         reg = <2>;
 396
 397                         ipu2_csi1_mux_to_ipu2_csi1: endpoint {
 398                                 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
 399                         };
 400                 };
 401         };
 402 };
 403
 404 &hdmi {
 405         compatible = "fsl,imx6q-hdmi";
 406
 407         port@2 {
 408                 reg = <2>;
 409
 410                 hdmi_mux_2: endpoint {
 411                         remote-endpoint = <&ipu2_di0_hdmi>;
 412                 };
 413         };
 414
 415         port@3 {
 416                 reg = <3>;
 417
 418                 hdmi_mux_3: endpoint {
 419                         remote-endpoint = <&ipu2_di1_hdmi>;
 420                 };
 421         };
 422 };
 423
 424 &ipu1_csi1 {
 425         ipu1_csi1_from_mipi_vc1: endpoint {
 426                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
 427         };
 428 };
 429
 430 &ldb {
 431         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 432                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 433                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 434                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 435         clock-names = "di0_pll", "di1_pll",
 436                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 437                       "di0", "di1";
 438
 439         lvds-channel@0 {
 440                 port@2 {
 441                         reg = <2>;
 442
 443                         lvds0_mux_2: endpoint {
 444                                 remote-endpoint = <&ipu2_di0_lvds0>;
 445                         };
 446                 };
 447
 448                 port@3 {
 449                         reg = <3>;
 450
 451                         lvds0_mux_3: endpoint {
 452                                 remote-endpoint = <&ipu2_di1_lvds0>;
 453                         };
 454                 };
 455         };
 456
 457         lvds-channel@1 {
 458                 port@2 {
 459                         reg = <2>;
 460
 461                         lvds1_mux_2: endpoint {
 462                                 remote-endpoint = <&ipu2_di0_lvds1>;
 463                         };
 464                 };
 465
 466                 port@3 {
 467                         reg = <3>;
 468
 469                         lvds1_mux_3: endpoint {
 470                                 remote-endpoint = <&ipu2_di1_lvds1>;
 471                         };
 472                 };
 473         };
 474 };
 475
 476 &mipi_csi {
 477         port@1 {
 478                 reg = <1>;
 479
 480                 mipi_vc0_to_ipu1_csi0_mux: endpoint {
 481                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 482                 };
 483         };
 484
 485         port@2 {
 486                 reg = <2>;
 487
 488                 mipi_vc1_to_ipu1_csi1: endpoint {
 489                         remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
 490                 };
 491         };
 492
 493         port@3 {
 494                 reg = <3>;
 495
 496                 mipi_vc2_to_ipu2_csi0: endpoint {
 497                         remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
 498                 };
 499         };
 500
 501         port@4 {
 502                 reg = <4>;
 503
 504                 mipi_vc3_to_ipu2_csi1_mux: endpoint {
 505                         remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
 506                 };
 507         };
 508 };
 509
 510 &mipi_dsi {
 511         ports {
 512                 port@2 {
 513                         reg = <2>;
 514
 515                         mipi_mux_2: endpoint {
 516                                 remote-endpoint = <&ipu2_di0_mipi>;
 517                         };
 518                 };
 519
 520                 port@3 {
 521                         reg = <3>;
 522
 523                         mipi_mux_3: endpoint {
 524                                 remote-endpoint = <&ipu2_di1_mipi>;
 525                         };
 526                 };
 527         };
 528 };
 529
 530 &mux {
 531         mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
 532                         <0x04 0x00100000>, /* MIPI_IPU2_MUX */
 533                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 534                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 535                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 536                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 537                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 538 };
 539
 540 &vpu {
 541         compatible = "fsl,imx6q-vpu", "cnm,coda960";
 542 };