ARM: dts: Add missing ranges for dra7 mcasp l3 ports
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / hip04.dtsi
1 /*
2  * Hisilicon Ltd. HiP04 SoC
3  *
4  * Copyright (C) 2013-2014 Hisilicon Ltd.
5  * Copyright (C) 2013-2014 Linaro Ltd.
6  *
7  * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13
14 / {
15         /* memory bus is 64-bit */
16         #address-cells = <2>;
17         #size-cells = <2>;
18
19         aliases {
20                 serial0 = &uart0;
21         };
22
23         bootwrapper {
24                 compatible = "hisilicon,hip04-bootwrapper";
25                 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26         };
27
28         cpus {
29                 #address-cells = <1>;
30                 #size-cells = <0>;
31
32                 cpu-map {
33                         cluster0 {
34                                 core0 {
35                                         cpu = <&CPU0>;
36                                 };
37                                 core1 {
38                                         cpu = <&CPU1>;
39                                 };
40                                 core2 {
41                                         cpu = <&CPU2>;
42                                 };
43                                 core3 {
44                                         cpu = <&CPU3>;
45                                 };
46                         };
47                         cluster1 {
48                                 core0 {
49                                         cpu = <&CPU4>;
50                                 };
51                                 core1 {
52                                         cpu = <&CPU5>;
53                                 };
54                                 core2 {
55                                         cpu = <&CPU6>;
56                                 };
57                                 core3 {
58                                         cpu = <&CPU7>;
59                                 };
60                         };
61                         cluster2 {
62                                 core0 {
63                                         cpu = <&CPU8>;
64                                 };
65                                 core1 {
66                                         cpu = <&CPU9>;
67                                 };
68                                 core2 {
69                                         cpu = <&CPU10>;
70                                 };
71                                 core3 {
72                                         cpu = <&CPU11>;
73                                 };
74                         };
75                         cluster3 {
76                                 core0 {
77                                         cpu = <&CPU12>;
78                                 };
79                                 core1 {
80                                         cpu = <&CPU13>;
81                                 };
82                                 core2 {
83                                         cpu = <&CPU14>;
84                                 };
85                                 core3 {
86                                         cpu = <&CPU15>;
87                                 };
88                         };
89                 };
90                 CPU0: cpu@0 {
91                         device_type = "cpu";
92                         compatible = "arm,cortex-a15";
93                         reg = <0>;
94                 };
95                 CPU1: cpu@1 {
96                         device_type = "cpu";
97                         compatible = "arm,cortex-a15";
98                         reg = <1>;
99                 };
100                 CPU2: cpu@2 {
101                         device_type = "cpu";
102                         compatible = "arm,cortex-a15";
103                         reg = <2>;
104                 };
105                 CPU3: cpu@3 {
106                         device_type = "cpu";
107                         compatible = "arm,cortex-a15";
108                         reg = <3>;
109                 };
110                 CPU4: cpu@100 {
111                         device_type = "cpu";
112                         compatible = "arm,cortex-a15";
113                         reg = <0x100>;
114                 };
115                 CPU5: cpu@101 {
116                         device_type = "cpu";
117                         compatible = "arm,cortex-a15";
118                         reg = <0x101>;
119                 };
120                 CPU6: cpu@102 {
121                         device_type = "cpu";
122                         compatible = "arm,cortex-a15";
123                         reg = <0x102>;
124                 };
125                 CPU7: cpu@103 {
126                         device_type = "cpu";
127                         compatible = "arm,cortex-a15";
128                         reg = <0x103>;
129                 };
130                 CPU8: cpu@200 {
131                         device_type = "cpu";
132                         compatible = "arm,cortex-a15";
133                         reg = <0x200>;
134                 };
135                 CPU9: cpu@201 {
136                         device_type = "cpu";
137                         compatible = "arm,cortex-a15";
138                         reg = <0x201>;
139                 };
140                 CPU10: cpu@202 {
141                         device_type = "cpu";
142                         compatible = "arm,cortex-a15";
143                         reg = <0x202>;
144                 };
145                 CPU11: cpu@203 {
146                         device_type = "cpu";
147                         compatible = "arm,cortex-a15";
148                         reg = <0x203>;
149                 };
150                 CPU12: cpu@300 {
151                         device_type = "cpu";
152                         compatible = "arm,cortex-a15";
153                         reg = <0x300>;
154                 };
155                 CPU13: cpu@301 {
156                         device_type = "cpu";
157                         compatible = "arm,cortex-a15";
158                         reg = <0x301>;
159                 };
160                 CPU14: cpu@302 {
161                         device_type = "cpu";
162                         compatible = "arm,cortex-a15";
163                         reg = <0x302>;
164                 };
165                 CPU15: cpu@303 {
166                         device_type = "cpu";
167                         compatible = "arm,cortex-a15";
168                         reg = <0x303>;
169                 };
170         };
171
172         timer {
173                 compatible = "arm,armv7-timer";
174                 interrupt-parent = <&gic>;
175                 interrupts = <1 13 0xf08>,
176                              <1 14 0xf08>,
177                              <1 11 0xf08>,
178                              <1 10 0xf08>;
179         };
180
181         clk_50m: clk_50m {
182                 #clock-cells = <0>;
183                 compatible = "fixed-clock";
184                 clock-frequency = <50000000>;
185         };
186
187         clk_168m: clk_168m {
188                 #clock-cells = <0>;
189                 compatible = "fixed-clock";
190                 clock-frequency = <168000000>;
191         };
192
193         clk_375m: clk_375m {
194                 #clock-cells = <0>;
195                 compatible = "fixed-clock";
196                 clock-frequency = <375000000>;
197         };
198
199         soc {
200                 /* It's a 32-bit SoC. */
201                 #address-cells = <1>;
202                 #size-cells = <1>;
203                 compatible = "simple-bus";
204                 interrupt-parent = <&gic>;
205                 ranges = <0 0 0xe0000000 0x10000000>;
206
207                 gic: interrupt-controller@c01000 {
208                         compatible = "hisilicon,hip04-intc";
209                         #interrupt-cells = <3>;
210                         #address-cells = <0>;
211                         interrupt-controller;
212                         interrupts = <1 9 0xf04>;
213
214                         reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
215                               <0xc04000 0x2000>, <0xc06000 0x2000>;
216                 };
217
218                 sysctrl: sysctrl {
219                         compatible = "hisilicon,sysctrl";
220                         reg = <0x3e00000 0x00100000>;
221                 };
222
223                 fabric: fabric {
224                         compatible = "hisilicon,hip04-fabric";
225                         reg = <0x302a000 0x1000>;
226                 };
227
228                 dual_timer0: dual_timer@3000000 {
229                         compatible = "arm,sp804", "arm,primecell";
230                         reg = <0x3000000 0x1000>;
231                         interrupts = <0 224 4>;
232                         clocks = <&clk_50m>, <&clk_50m>;
233                         clock-names = "apb_pclk";
234                 };
235
236                 arm-pmu {
237                         compatible = "arm,cortex-a15-pmu";
238                         interrupts = <0 64 4>,
239                                      <0 65 4>,
240                                      <0 66 4>,
241                                      <0 67 4>,
242                                      <0 68 4>,
243                                      <0 69 4>,
244                                      <0 70 4>,
245                                      <0 71 4>,
246                                      <0 72 4>,
247                                      <0 73 4>,
248                                      <0 74 4>,
249                                      <0 75 4>,
250                                      <0 76 4>,
251                                      <0 77 4>,
252                                      <0 78 4>,
253                                      <0 79 4>;
254                 };
255
256                 uart0: uart@4007000 {
257                         compatible = "snps,dw-apb-uart";
258                         reg = <0x4007000 0x1000>;
259                         interrupts = <0 381 4>;
260                         clocks = <&clk_168m>;
261                         clock-names = "uartclk";
262                         reg-shift = <2>;
263                         status = "disabled";
264                 };
265
266                 sata0: sata@a000000 {
267                         compatible = "hisilicon,hisi-ahci";
268                         reg = <0xa000000 0x1000000>;
269                         interrupts = <0 372 4>;
270                 };
271
272         };
273
274         etb@0,e3c42000 {
275                 compatible = "arm,coresight-etb10", "arm,primecell";
276                 reg = <0 0xe3c42000 0 0x1000>;
277
278                 clocks = <&clk_375m>;
279                 clock-names = "apb_pclk";
280                 in-ports {
281                         port {
282                                 etb0_in_port: endpoint@0 {
283                                         remote-endpoint = <&replicator0_out_port0>;
284                                 };
285                         };
286                 };
287         };
288
289         etb@0,e3c82000 {
290                 compatible = "arm,coresight-etb10", "arm,primecell";
291                 reg = <0 0xe3c82000 0 0x1000>;
292
293                 clocks = <&clk_375m>;
294                 clock-names = "apb_pclk";
295                 in-ports {
296                         port {
297                                 etb1_in_port: endpoint@0 {
298                                         remote-endpoint = <&replicator1_out_port0>;
299                                 };
300                         };
301                 };
302         };
303
304         etb@0,e3cc2000 {
305                 compatible = "arm,coresight-etb10", "arm,primecell";
306                 reg = <0 0xe3cc2000 0 0x1000>;
307
308                 clocks = <&clk_375m>;
309                 clock-names = "apb_pclk";
310                 in-ports {
311                         port {
312                                 etb2_in_port: endpoint@0 {
313                                         remote-endpoint = <&replicator2_out_port0>;
314                                 };
315                         };
316                 };
317         };
318
319         etb@0,e3d02000 {
320                 compatible = "arm,coresight-etb10", "arm,primecell";
321                 reg = <0 0xe3d02000 0 0x1000>;
322
323                 clocks = <&clk_375m>;
324                 clock-names = "apb_pclk";
325                 in-ports {
326                         port {
327                                 etb3_in_port: endpoint@0 {
328                                         remote-endpoint = <&replicator3_out_port0>;
329                                 };
330                         };
331                 };
332         };
333
334         tpiu@0,e3c05000 {
335                 compatible = "arm,coresight-tpiu", "arm,primecell";
336                 reg = <0 0xe3c05000 0 0x1000>;
337
338                 clocks = <&clk_375m>;
339                 clock-names = "apb_pclk";
340                 in-ports {
341                         port {
342                                 tpiu_in_port: endpoint@0 {
343                                         remote-endpoint = <&funnel4_out_port0>;
344                                 };
345                         };
346                 };
347         };
348
349         replicator0 {
350                 /* non-configurable replicators don't show up on the
351                  * AMBA bus.  As such no need to add "arm,primecell".
352                  */
353                 compatible = "arm,coresight-replicator";
354
355                 out-ports {
356                         #address-cells = <1>;
357                         #size-cells = <0>;
358
359                         /* replicator output ports */
360                         port@0 {
361                                 reg = <0>;
362                                 replicator0_out_port0: endpoint {
363                                         remote-endpoint = <&etb0_in_port>;
364                                 };
365                         };
366
367                         port@1 {
368                                 reg = <1>;
369                                 replicator0_out_port1: endpoint {
370                                         remote-endpoint = <&funnel4_in_port0>;
371                                 };
372                         };
373                 };
374
375                 in-ports {
376                         port {
377                                 replicator0_in_port0: endpoint {
378                                         remote-endpoint = <&funnel0_out_port0>;
379                                 };
380                         };
381                 };
382         };
383
384         replicator1 {
385                 /* non-configurable replicators don't show up on the
386                  * AMBA bus.  As such no need to add "arm,primecell".
387                  */
388                 compatible = "arm,coresight-replicator";
389
390                 out-ports {
391                         #address-cells = <1>;
392                         #size-cells = <0>;
393
394                         /* replicator output ports */
395                         port@0 {
396                                 reg = <0>;
397                                 replicator1_out_port0: endpoint {
398                                         remote-endpoint = <&etb1_in_port>;
399                                 };
400                         };
401
402                         port@1 {
403                                 reg = <1>;
404                                 replicator1_out_port1: endpoint {
405                                         remote-endpoint = <&funnel4_in_port1>;
406                                 };
407                         };
408                 };
409
410                 in-ports {
411                         port {
412                                 replicator1_in_port0: endpoint {
413                                         remote-endpoint = <&funnel1_out_port0>;
414                                 };
415                         };
416                 };
417         };
418
419         replicator2 {
420                 /* non-configurable replicators don't show up on the
421                  * AMBA bus.  As such no need to add "arm,primecell".
422                  */
423                 compatible = "arm,coresight-replicator";
424
425                 out-ports {
426                         #address-cells = <1>;
427                         #size-cells = <0>;
428
429                         port@0 {
430                                 reg = <0>;
431                                 replicator2_out_port0: endpoint {
432                                         remote-endpoint = <&etb2_in_port>;
433                                 };
434                         };
435
436                         port@1 {
437                                 reg = <1>;
438                                         replicator2_out_port1: endpoint {
439                                         remote-endpoint = <&funnel4_in_port2>;
440                                 };
441                         };
442                 };
443
444                 in-ports {
445                         port {
446                                 replicator2_in_port0: endpoint {
447                                         remote-endpoint = <&funnel2_out_port0>;
448                                 };
449                         };
450                 };
451         };
452
453         replicator3 {
454                 /* non-configurable replicators don't show up on the
455                  * AMBA bus.  As such no need to add "arm,primecell".
456                  */
457                 compatible = "arm,coresight-replicator";
458
459                 out-ports {
460                         #address-cells = <1>;
461                         #size-cells = <0>;
462
463                         port@0 {
464                                 reg = <0>;
465                                 replicator3_out_port0: endpoint {
466                                         remote-endpoint = <&etb3_in_port>;
467                                 };
468                         };
469
470                         port@1 {
471                                 reg = <1>;
472                                 replicator3_out_port1: endpoint {
473                                         remote-endpoint = <&funnel4_in_port3>;
474                                 };
475                         };
476                 };
477
478                 in-ports {
479                         port {
480                                 replicator3_in_port0: endpoint {
481                                         remote-endpoint = <&funnel3_out_port0>;
482                                 };
483                         };
484                 };
485         };
486
487         funnel@0,e3c41000 {
488                 compatible = "arm,coresight-funnel", "arm,primecell";
489                 reg = <0 0xe3c41000 0 0x1000>;
490
491                 clocks = <&clk_375m>;
492                 clock-names = "apb_pclk";
493                 out-ports {
494                         port {
495                                 funnel0_out_port0: endpoint {
496                                         remote-endpoint =
497                                                 <&replicator0_in_port0>;
498                                 };
499                         };
500                 };
501
502                 in-ports {
503                         #address-cells = <1>;
504                         #size-cells = <0>;
505
506                         port@0 {
507                                 reg = <0>;
508                                 funnel0_in_port0: endpoint {
509                                         remote-endpoint = <&ptm0_out_port>;
510                                 };
511                         };
512
513                         port@1 {
514                                 reg = <1>;
515                                 funnel0_in_port1: endpoint {
516                                         remote-endpoint = <&ptm1_out_port>;
517                                 };
518                         };
519
520                         port@2 {
521                                 reg = <2>;
522                                 funnel0_in_port2: endpoint {
523                                         remote-endpoint = <&ptm2_out_port>;
524                                 };
525                         };
526
527                         port@3 {
528                                 reg = <3>;
529                                 funnel0_in_port3: endpoint {
530                                         remote-endpoint = <&ptm3_out_port>;
531                                 };
532                         };
533                 };
534         };
535
536         funnel@0,e3c81000 {
537                 compatible = "arm,coresight-funnel", "arm,primecell";
538                 reg = <0 0xe3c81000 0 0x1000>;
539
540                 clocks = <&clk_375m>;
541                 clock-names = "apb_pclk";
542                 out-ports {
543                         port {
544                                 funnel1_out_port0: endpoint {
545                                         remote-endpoint =
546                                                 <&replicator1_in_port0>;
547                                 };
548                         };
549                 };
550
551                 in-ports {
552                         #address-cells = <1>;
553                         #size-cells = <0>;
554
555                         port@0 {
556                                 reg = <0>;
557                                 funnel1_in_port0: endpoint {
558                                         remote-endpoint = <&ptm4_out_port>;
559                                 };
560                         };
561
562                         port@1 {
563                                 reg = <1>;
564                                 funnel1_in_port1: endpoint {
565                                         remote-endpoint = <&ptm5_out_port>;
566                                 };
567                         };
568
569                         port@2 {
570                                 reg = <2>;
571                                 funnel1_in_port2: endpoint {
572                                         remote-endpoint = <&ptm6_out_port>;
573                                 };
574                         };
575
576                         port@3 {
577                                 reg = <3>;
578                                 funnel1_in_port3: endpoint {
579                                         remote-endpoint = <&ptm7_out_port>;
580                                 };
581                         };
582                 };
583         };
584
585         funnel@0,e3cc1000 {
586                 compatible = "arm,coresight-funnel", "arm,primecell";
587                 reg = <0 0xe3cc1000 0 0x1000>;
588
589                 clocks = <&clk_375m>;
590                 clock-names = "apb_pclk";
591                 out-ports {
592                         port {
593                                 funnel2_out_port0: endpoint {
594                                         remote-endpoint =
595                                                 <&replicator2_in_port0>;
596                                 };
597                         };
598                 };
599
600                 in-ports {
601                         #address-cells = <1>;
602                         #size-cells = <0>;
603
604                         port@0 {
605                                 reg = <0>;
606                                 funnel2_in_port0: endpoint {
607                                         remote-endpoint = <&ptm8_out_port>;
608                                 };
609                         };
610
611                         port@1 {
612                                 reg = <1>;
613                                 funnel2_in_port1: endpoint {
614                                         remote-endpoint = <&ptm9_out_port>;
615                                 };
616                         };
617
618                         port@2 {
619                                 reg = <2>;
620                                 funnel2_in_port2: endpoint {
621                                         remote-endpoint = <&ptm10_out_port>;
622                                 };
623                         };
624
625                         port@3 {
626                                 reg = <3>;
627                                 funnel2_in_port3: endpoint {
628                                         remote-endpoint = <&ptm11_out_port>;
629                                 };
630                         };
631                 };
632         };
633
634         funnel@0,e3d01000 {
635                 compatible = "arm,coresight-funnel", "arm,primecell";
636                 reg = <0 0xe3d01000 0 0x1000>;
637
638                 clocks = <&clk_375m>;
639                 clock-names = "apb_pclk";
640                 out-ports {
641                         port {
642                                 funnel3_out_port0: endpoint {
643                                         remote-endpoint =
644                                                 <&replicator3_in_port0>;
645                                 };
646                         };
647                 };
648
649                 in-ports {
650                         #address-cells = <1>;
651                         #size-cells = <0>;
652
653                         port@0 {
654                                 reg = <0>;
655                                 funnel3_in_port0: endpoint {
656                                         remote-endpoint = <&ptm12_out_port>;
657                                 };
658                         };
659
660                         port@1 {
661                                 reg = <1>;
662                                 funnel3_in_port1: endpoint {
663                                         remote-endpoint = <&ptm13_out_port>;
664                                 };
665                         };
666
667                         port@2 {
668                                 reg = <2>;
669                                 funnel3_in_port2: endpoint {
670                                         remote-endpoint = <&ptm14_out_port>;
671                                 };
672                         };
673
674                         port@3 {
675                                 reg = <3>;
676                                 funnel3_in_port3: endpoint {
677                                         remote-endpoint = <&ptm15_out_port>;
678                                 };
679                         };
680                 };
681         };
682
683         funnel@0,e3c04000 {
684                 compatible = "arm,coresight-funnel", "arm,primecell";
685                 reg = <0 0xe3c04000 0 0x1000>;
686
687                 clocks = <&clk_375m>;
688                 clock-names = "apb_pclk";
689                 out-ports {
690                         port {
691                                 funnel4_out_port0: endpoint {
692                                         remote-endpoint = <&tpiu_in_port>;
693                                 };
694                         };
695                 };
696
697                 in-ports {
698                         #address-cells = <1>;
699                         #size-cells = <0>;
700
701                         port@0 {
702                                 reg = <0>;
703                                 funnel4_in_port0: endpoint {
704                                         remote-endpoint =
705                                                 <&replicator0_out_port1>;
706                                 };
707                         };
708
709                         port@1 {
710                                 reg = <1>;
711                                 funnel4_in_port1: endpoint {
712                                         remote-endpoint =
713                                                 <&replicator1_out_port1>;
714                                 };
715                         };
716
717                         port@2 {
718                                 reg = <2>;
719                                 funnel4_in_port2: endpoint {
720                                         remote-endpoint =
721                                                 <&replicator2_out_port1>;
722                                 };
723                         };
724
725                         port@3 {
726                                 reg = <3>;
727                                 funnel4_in_port3: endpoint {
728                                         remote-endpoint =
729                                                 <&replicator3_out_port1>;
730                                 };
731                         };
732                 };
733         };
734
735         ptm@0,e3c7c000 {
736                 compatible = "arm,coresight-etm3x", "arm,primecell";
737                 reg = <0 0xe3c7c000 0 0x1000>;
738
739                 clocks = <&clk_375m>;
740                 clock-names = "apb_pclk";
741                 cpu = <&CPU0>;
742                 out-ports {
743                         port {
744                                 ptm0_out_port: endpoint {
745                                         remote-endpoint = <&funnel0_in_port0>;
746                                 };
747                         };
748                 };
749         };
750
751         ptm@0,e3c7d000 {
752                 compatible = "arm,coresight-etm3x", "arm,primecell";
753                 reg = <0 0xe3c7d000 0 0x1000>;
754
755                 clocks = <&clk_375m>;
756                 clock-names = "apb_pclk";
757                 cpu = <&CPU1>;
758                 out-ports {
759                         port {
760                                 ptm1_out_port: endpoint {
761                                         remote-endpoint = <&funnel0_in_port1>;
762                                 };
763                         };
764                 };
765         };
766
767         ptm@0,e3c7e000 {
768                 compatible = "arm,coresight-etm3x", "arm,primecell";
769                 reg = <0 0xe3c7e000 0 0x1000>;
770
771                 clocks = <&clk_375m>;
772                 clock-names = "apb_pclk";
773                 cpu = <&CPU2>;
774                 out-ports {
775                         port {
776                                 ptm2_out_port: endpoint {
777                                         remote-endpoint = <&funnel0_in_port2>;
778                                 };
779                         };
780                 };
781         };
782
783         ptm@0,e3c7f000 {
784                 compatible = "arm,coresight-etm3x", "arm,primecell";
785                 reg = <0 0xe3c7f000 0 0x1000>;
786
787                 clocks = <&clk_375m>;
788                 clock-names = "apb_pclk";
789                 cpu = <&CPU3>;
790                 out-ports {
791                         port {
792                                 ptm3_out_port: endpoint {
793                                         remote-endpoint = <&funnel0_in_port3>;
794                                 };
795                         };
796                 };
797         };
798
799         ptm@0,e3cbc000 {
800                 compatible = "arm,coresight-etm3x", "arm,primecell";
801                 reg = <0 0xe3cbc000 0 0x1000>;
802
803                 clocks = <&clk_375m>;
804                 clock-names = "apb_pclk";
805                 cpu = <&CPU4>;
806                 out-ports {
807                         port {
808                                 ptm4_out_port: endpoint {
809                                         remote-endpoint = <&funnel1_in_port0>;
810                                 };
811                         };
812                 };
813         };
814
815         ptm@0,e3cbd000 {
816                 compatible = "arm,coresight-etm3x", "arm,primecell";
817                 reg = <0 0xe3cbd000 0 0x1000>;
818
819                 clocks = <&clk_375m>;
820                 clock-names = "apb_pclk";
821                 cpu = <&CPU5>;
822                 out-ports {
823                         port {
824                                 ptm5_out_port: endpoint {
825                                         remote-endpoint = <&funnel1_in_port1>;
826                                 };
827                         };
828                 };
829         };
830
831         ptm@0,e3cbe000 {
832                 compatible = "arm,coresight-etm3x", "arm,primecell";
833                 reg = <0 0xe3cbe000 0 0x1000>;
834
835                 clocks = <&clk_375m>;
836                 clock-names = "apb_pclk";
837                 cpu = <&CPU6>;
838                 out-ports {
839                         port {
840                                 ptm6_out_port: endpoint {
841                                         remote-endpoint = <&funnel1_in_port2>;
842                                 };
843                         };
844                 };
845         };
846
847         ptm@0,e3cbf000 {
848                 compatible = "arm,coresight-etm3x", "arm,primecell";
849                 reg = <0 0xe3cbf000 0 0x1000>;
850
851                 clocks = <&clk_375m>;
852                 clock-names = "apb_pclk";
853                 cpu = <&CPU7>;
854                 out-ports {
855                         port {
856                                 ptm7_out_port: endpoint {
857                                         remote-endpoint = <&funnel1_in_port3>;
858                                 };
859                         };
860                 };
861         };
862
863         ptm@0,e3cfc000 {
864                 compatible = "arm,coresight-etm3x", "arm,primecell";
865                 reg = <0 0xe3cfc000 0 0x1000>;
866
867                 clocks = <&clk_375m>;
868                 clock-names = "apb_pclk";
869                 cpu = <&CPU8>;
870                 out-ports {
871                         port {
872                                 ptm8_out_port: endpoint {
873                                         remote-endpoint = <&funnel2_in_port0>;
874                                 };
875                         };
876                 };
877         };
878
879         ptm@0,e3cfd000 {
880                 compatible = "arm,coresight-etm3x", "arm,primecell";
881                 reg = <0 0xe3cfd000 0 0x1000>;
882                 clocks = <&clk_375m>;
883                 clock-names = "apb_pclk";
884                 cpu = <&CPU9>;
885                 out-ports {
886                         port {
887                                 ptm9_out_port: endpoint {
888                                         remote-endpoint = <&funnel2_in_port1>;
889                                 };
890                         };
891                 };
892         };
893
894         ptm@0,e3cfe000 {
895                 compatible = "arm,coresight-etm3x", "arm,primecell";
896                 reg = <0 0xe3cfe000 0 0x1000>;
897
898                 clocks = <&clk_375m>;
899                 clock-names = "apb_pclk";
900                 cpu = <&CPU10>;
901                 out-ports {
902                         port {
903                                 ptm10_out_port: endpoint {
904                                         remote-endpoint = <&funnel2_in_port2>;
905                                 };
906                         };
907                 };
908         };
909
910         ptm@0,e3cff000 {
911                 compatible = "arm,coresight-etm3x", "arm,primecell";
912                 reg = <0 0xe3cff000 0 0x1000>;
913
914                 clocks = <&clk_375m>;
915                 clock-names = "apb_pclk";
916                 cpu = <&CPU11>;
917                 out-ports {
918                         port {
919                                 ptm11_out_port: endpoint {
920                                         remote-endpoint = <&funnel2_in_port3>;
921                                 };
922                         };
923                 };
924         };
925
926         ptm@0,e3d3c000 {
927                 compatible = "arm,coresight-etm3x", "arm,primecell";
928                 reg = <0 0xe3d3c000 0 0x1000>;
929
930                 clocks = <&clk_375m>;
931                 clock-names = "apb_pclk";
932                 cpu = <&CPU12>;
933                 out-ports {
934                         port {
935                                 ptm12_out_port: endpoint {
936                                         remote-endpoint = <&funnel3_in_port0>;
937                                 };
938                         };
939                 };
940         };
941
942         ptm@0,e3d3d000 {
943                 compatible = "arm,coresight-etm3x", "arm,primecell";
944                 reg = <0 0xe3d3d000 0 0x1000>;
945
946                 clocks = <&clk_375m>;
947                 clock-names = "apb_pclk";
948                 cpu = <&CPU13>;
949                 out-ports {
950                         port {
951                                 ptm13_out_port: endpoint {
952                                         remote-endpoint = <&funnel3_in_port1>;
953                                 };
954                         };
955                 };
956         };
957
958         ptm@0,e3d3e000 {
959                 compatible = "arm,coresight-etm3x", "arm,primecell";
960                 reg = <0 0xe3d3e000 0 0x1000>;
961
962                 clocks = <&clk_375m>;
963                 clock-names = "apb_pclk";
964                 cpu = <&CPU14>;
965                 out-ports {
966                         port {
967                                 ptm14_out_port: endpoint {
968                                         remote-endpoint = <&funnel3_in_port2>;
969                                 };
970                         };
971                 };
972         };
973
974         ptm@0,e3d3f000 {
975                 compatible = "arm,coresight-etm3x", "arm,primecell";
976                 reg = <0 0xe3d3f000 0 0x1000>;
977
978                 clocks = <&clk_375m>;
979                 clock-names = "apb_pclk";
980                 cpu = <&CPU15>;
981                 out-ports {
982                         port {
983                                 ptm15_out_port: endpoint {
984                                         remote-endpoint = <&funnel3_in_port3>;
985                                 };
986                         };
987                 };
988         };
989 };