arch/arm/boot/dts/exynos5410.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5410 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
   8  * EXYNOS5410 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "skeleton.dtsi"
  17 #include <dt-bindings/clock/exynos5410.h>
  18
  19 / {
  20         compatible = "samsung,exynos5410", "samsung,exynos5";
  21         interrupt-parent = <&gic>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 CPU0: cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a15";
  30                         reg = <0x0>;
  31                 };
  32
  33                 CPU1: cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a15";
  36                         reg = <0x1>;
  37                 };
  38
  39                 CPU2: cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a15";
  42                         reg = <0x2>;
  43                 };
  44
  45                 CPU3: cpu@3 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x3>;
  49                 };
  50         };
  51
  52         soc: soc {
  53                 compatible = "simple-bus";
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 ranges;
  57
  58                 combiner: interrupt-controller@10440000 {
  59                         compatible = "samsung,exynos4210-combiner";
  60                         #interrupt-cells = <2>;
  61                         interrupt-controller;
  62                         samsung,combiner-nr = <32>;
  63                         reg = <0x10440000 0x1000>;
  64                         interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  65                                         <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  66                                         <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  67                                         <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
  68                                         <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
  69                                         <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
  70                                         <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
  71                                         <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
  72                 };
  73
  74                 gic: interrupt-controller@10481000 {
  75                         compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  76                         #interrupt-cells = <3>;
  77                         interrupt-controller;
  78                         reg =   <0x10481000 0x1000>,
  79                                 <0x10482000 0x1000>,
  80                                 <0x10484000 0x2000>,
  81                                 <0x10486000 0x2000>;
  82                         interrupts = <1 9 0xf04>;
  83                 };
  84
  85                 chipid@10000000 {
  86                         compatible = "samsung,exynos4210-chipid";
  87                         reg = <0x10000000 0x100>;
  88                 };
  89
  90                 mct: mct@101C0000 {
  91                         compatible = "samsung,exynos4210-mct";
  92                         reg = <0x101C0000 0xB00>;
  93                         interrupt-parent = <&interrupt_map>;
  94                         interrupts = <0>, <1>, <2>, <3>,
  95                                 <4>, <5>, <6>, <7>,
  96                                 <8>, <9>, <10>, <11>;
  97                         clocks = <&fin_pll>, <&clock CLK_MCT>;
  98                         clock-names = "fin_pll", "mct";
  99
 100                         interrupt_map: interrupt-map {
 101                                 #interrupt-cells = <1>;
 102                                 #address-cells = <0>;
 103                                 #size-cells = <0>;
 104                                 interrupt-map = <0 &combiner 23 3>,
 105                                                 <1 &combiner 23 4>,
 106                                                 <2 &combiner 25 2>,
 107                                                 <3 &combiner 25 3>,
 108                                                 <4 &gic 0 120 0>,
 109                                                 <5 &gic 0 121 0>,
 110                                                 <6 &gic 0 122 0>,
 111                                                 <7 &gic 0 123 0>,
 112                                                 <8 &gic 0 128 0>,
 113                                                 <9 &gic 0 129 0>,
 114                                                 <10 &gic 0 130 0>,
 115                                                 <11 &gic 0 131 0>;
 116                         };
 117                 };
 118
 119                 sysram@02020000 {
 120                         compatible = "mmio-sram";
 121                         reg = <0x02020000 0x54000>;
 122                         #address-cells = <1>;
 123                         #size-cells = <1>;
 124                         ranges = <0 0x02020000 0x54000>;
 125
 126                         smp-sysram@0 {
 127                                 compatible = "samsung,exynos4210-sysram";
 128                                 reg = <0x0 0x1000>;
 129                         };
 130
 131                         smp-sysram@53000 {
 132                                 compatible = "samsung,exynos4210-sysram-ns";
 133                                 reg = <0x53000 0x1000>;
 134                         };
 135                 };
 136
 137                 clock: clock-controller@10010000 {
 138                         compatible = "samsung,exynos5410-clock";
 139                         reg = <0x10010000 0x30000>;
 140                         #clock-cells = <1>;
 141                 };
 142
 143                 mmc_0: mmc@12200000 {
 144                         compatible = "samsung,exynos5250-dw-mshc";
 145                         reg = <0x12200000 0x1000>;
 146                         interrupts = <0 75 0>;
 147                         #address-cells = <1>;
 148                         #size-cells = <0>;
 149                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 150                         clock-names = "biu", "ciu";
 151                         fifo-depth = <0x80>;
 152                         status = "disabled";
 153                 };
 154
 155                 mmc_1: mmc@12210000 {
 156                         compatible = "samsung,exynos5250-dw-mshc";
 157                         reg = <0x12210000 0x1000>;
 158                         interrupts = <0 76 0>;
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 162                         clock-names = "biu", "ciu";
 163                         fifo-depth = <0x80>;
 164                         status = "disabled";
 165                 };
 166
 167                 mmc_2: mmc@12220000 {
 168                         compatible = "samsung,exynos5250-dw-mshc";
 169                         reg = <0x12220000 0x1000>;
 170                         interrupts = <0 77 0>;
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 174                         clock-names = "biu", "ciu";
 175                         fifo-depth = <0x80>;
 176                         status = "disabled";
 177                 };
 178
 179                 uart0: serial@12C00000 {
 180                         compatible = "samsung,exynos4210-uart";
 181                         reg = <0x12C00000 0x100>;
 182                         interrupts = <0 51 0>;
 183                         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 184                         clock-names = "uart", "clk_uart_baud0";
 185                         status = "disabled";
 186                 };
 187
 188                 uart1: serial@12C10000 {
 189                         compatible = "samsung,exynos4210-uart";
 190                         reg = <0x12C10000 0x100>;
 191                         interrupts = <0 52 0>;
 192                         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 193                         clock-names = "uart", "clk_uart_baud0";
 194                         status = "disabled";
 195                 };
 196
 197                 uart2: serial@12C20000 {
 198                         compatible = "samsung,exynos4210-uart";
 199                         reg = <0x12C20000 0x100>;
 200                         interrupts = <0 53 0>;
 201                         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 202                         clock-names = "uart", "clk_uart_baud0";
 203                         status = "disabled";
 204                 };
 205         };
 206 };