2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
14 #define MAX_SOURCES 400
20 compatible = "ti,dra7xx";
21 interrupt-parent = <&crossbar_mpu>;
40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
53 interrupt-parent = <&gic>;
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
59 #interrupt-cells = <3>;
60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x2000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
65 interrupt-parent = <&gic>;
68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
71 #interrupt-cells = <3>;
72 reg = <0x0 0x48281000 0x0 0x1000>;
73 interrupt-parent = <&gic>;
82 compatible = "arm,cortex-a15";
85 operating-points-v2 = <&cpu0_opp_table>;
87 clocks = <&dpll_mpu_ck>;
90 clock-latency = <300000>; /* From omap-cpufreq driver */
93 cooling-min-level = <0>;
94 cooling-max-level = <2>;
95 #cooling-cells = <2>; /* min followed by max */
97 vbb-supply = <&abb_mpu>;
101 cpu0_opp_table: opp-table {
102 compatible = "operating-points-v2-ti-cpu";
103 syscon = <&scm_wkup>;
106 opp-hz = /bits/ 64 <1000000000>;
107 opp-microvolt = <1060000 850000 1150000>,
108 <1060000 850000 1150000>;
109 opp-supported-hw = <0xFF 0x01>;
114 opp-hz = /bits/ 64 <1176000000>;
115 opp-microvolt = <1160000 885000 1160000>,
116 <1160000 885000 1160000>;
118 opp-supported-hw = <0xFF 0x02>;
121 opp_high@1500000000 {
122 opp-hz = /bits/ 64 <1500000000>;
123 opp-microvolt = <1210000 950000 1250000>,
124 <1210000 950000 1250000>;
125 opp-supported-hw = <0xFF 0x04>;
130 * The soc node represents the soc top level view. It is used for IPs
131 * that are not memory mapped in the MPU view or for the MPU itself.
134 compatible = "ti,omap-infra";
136 compatible = "ti,omap5-mpu";
142 * XXX: Use a flat representation of the SOC interconnect.
143 * The real OMAP interconnect network is quite complex.
144 * Since it will not bring real advantage to represent that in DT for
145 * the moment, just use a fake OCP bus entry to represent the whole bus
149 compatible = "ti,dra7-l3-noc", "simple-bus";
150 #address-cells = <1>;
152 ranges = <0x0 0x0 0x0 0xc0000000>;
153 ti,hwmods = "l3_main_1", "l3_main_2";
154 reg = <0x0 0x44000000 0x0 0x1000000>,
155 <0x0 0x45000000 0x0 0x1000>;
156 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
157 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
159 l4_cfg: l4@4a000000 {
160 compatible = "ti,dra7-l4-cfg", "simple-bus";
161 #address-cells = <1>;
163 ranges = <0 0x4a000000 0x22c000>;
166 compatible = "ti,dra7-scm-core", "simple-bus";
167 reg = <0x2000 0x2000>;
168 #address-cells = <1>;
170 ranges = <0 0x2000 0x2000>;
172 scm_conf: scm_conf@0 {
173 compatible = "syscon", "simple-bus";
175 #address-cells = <1>;
177 ranges = <0 0x0 0x1400>;
179 pbias_regulator: pbias_regulator@e00 {
180 compatible = "ti,pbias-dra7", "ti,pbias-omap";
182 syscon = <&scm_conf>;
183 pbias_mmc_reg: pbias_mmc_omap5 {
184 regulator-name = "pbias_mmc_omap5";
185 regulator-min-microvolt = <1800000>;
186 regulator-max-microvolt = <3300000>;
190 scm_conf_clocks: clocks {
191 #address-cells = <1>;
196 dra7_pmx_core: pinmux@1400 {
197 compatible = "ti,dra7-padconf",
199 reg = <0x1400 0x0468>;
200 #address-cells = <1>;
202 #pinctrl-cells = <1>;
203 #interrupt-cells = <1>;
204 interrupt-controller;
205 pinctrl-single,register-width = <32>;
206 pinctrl-single,function-mask = <0x3fffffff>;
209 scm_conf1: scm_conf@1c04 {
210 compatible = "syscon";
211 reg = <0x1c04 0x0020>;
215 scm_conf_pcie: scm_conf@1c24 {
216 compatible = "syscon";
217 reg = <0x1c24 0x0024>;
220 sdma_xbar: dma-router@b78 {
221 compatible = "ti,dra7-dma-crossbar";
224 dma-requests = <205>;
225 ti,dma-safe-map = <0>;
226 dma-masters = <&sdma>;
229 edma_xbar: dma-router@c78 {
230 compatible = "ti,dra7-dma-crossbar";
233 dma-requests = <204>;
234 ti,dma-safe-map = <0>;
235 dma-masters = <&edma>;
239 cm_core_aon: cm_core_aon@5000 {
240 compatible = "ti,dra7-cm-core-aon",
242 #address-cells = <1>;
244 reg = <0x5000 0x2000>;
245 ranges = <0 0x5000 0x2000>;
247 cm_core_aon_clocks: clocks {
248 #address-cells = <1>;
252 cm_core_aon_clockdomains: clockdomains {
256 cm_core: cm_core@8000 {
257 compatible = "ti,dra7-cm-core", "simple-bus";
258 #address-cells = <1>;
260 reg = <0x8000 0x3000>;
261 ranges = <0 0x8000 0x3000>;
263 cm_core_clocks: clocks {
264 #address-cells = <1>;
268 cm_core_clockdomains: clockdomains {
273 l4_wkup: l4@4ae00000 {
274 compatible = "ti,dra7-l4-wkup", "simple-bus";
275 #address-cells = <1>;
277 ranges = <0 0x4ae00000 0x3f000>;
279 counter32k: counter@4000 {
280 compatible = "ti,omap-counter32k";
282 ti,hwmods = "counter_32k";
286 compatible = "ti,dra7-prm", "simple-bus";
287 reg = <0x6000 0x3000>;
288 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
289 #address-cells = <1>;
291 ranges = <0 0x6000 0x3000>;
294 #address-cells = <1>;
298 prm_clockdomains: clockdomains {
302 scm_wkup: scm_conf@c000 {
303 compatible = "syscon";
304 reg = <0xc000 0x1000>;
309 compatible = "simple-bus";
311 #address-cells = <1>;
312 ranges = <0x51000000 0x51000000 0x3000
313 0x0 0x20000000 0x10000000>;
315 * To enable PCI endpoint mode, disable the pcie1_rc
316 * node and enable pcie1_ep mode.
318 pcie1_rc: pcie@51000000 {
319 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
320 reg-names = "rc_dbics", "ti_conf", "config";
321 interrupts = <0 232 0x4>, <0 233 0x4>;
322 #address-cells = <3>;
325 ranges = <0x81000000 0 0 0x03000 0 0x00010000
326 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
327 bus-range = <0x00 0xff>;
328 #interrupt-cells = <1>;
330 linux,pci-domain = <0>;
333 phy-names = "pcie-phy0";
334 interrupt-map-mask = <0 0 0 7>;
335 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
336 <0 0 0 2 &pcie1_intc 2>,
337 <0 0 0 3 &pcie1_intc 3>,
338 <0 0 0 4 &pcie1_intc 4>;
340 pcie1_intc: interrupt-controller {
341 interrupt-controller;
342 #address-cells = <0>;
343 #interrupt-cells = <1>;
347 pcie1_ep: pcie_ep@51000000 {
348 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
349 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
350 interrupts = <0 232 0x4>;
352 num-ib-windows = <4>;
353 num-ob-windows = <16>;
356 phy-names = "pcie-phy0";
357 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
363 compatible = "simple-bus";
365 #address-cells = <1>;
366 ranges = <0x51800000 0x51800000 0x3000
367 0x0 0x30000000 0x10000000>;
369 pcie2_rc: pcie@51800000 {
370 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
371 reg-names = "rc_dbics", "ti_conf", "config";
372 interrupts = <0 355 0x4>, <0 356 0x4>;
373 #address-cells = <3>;
376 ranges = <0x81000000 0 0 0x03000 0 0x00010000
377 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
378 bus-range = <0x00 0xff>;
379 #interrupt-cells = <1>;
381 linux,pci-domain = <1>;
384 phy-names = "pcie-phy0";
385 interrupt-map-mask = <0 0 0 7>;
386 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
387 <0 0 0 2 &pcie2_intc 2>,
388 <0 0 0 3 &pcie2_intc 3>,
389 <0 0 0 4 &pcie2_intc 4>;
390 pcie2_intc: interrupt-controller {
391 interrupt-controller;
392 #address-cells = <0>;
393 #interrupt-cells = <1>;
398 ocmcram1: ocmcram@40300000 {
399 compatible = "mmio-sram";
400 reg = <0x40300000 0x80000>;
401 ranges = <0x0 0x40300000 0x80000>;
402 #address-cells = <1>;
405 * This is a placeholder for an optional reserved
406 * region for use by secure software. The size
407 * of this region is not known until runtime so it
408 * is set as zero to either be updated to reserve
409 * space or left unchanged to leave all SRAM for use.
410 * On HS parts that that require the reserved region
411 * either the bootloader can update the size to
412 * the required amount or the node can be overridden
413 * from the board dts file for the secure platform.
416 compatible = "ti,secure-ram";
422 * NOTE: ocmcram2 and ocmcram3 are not available on all
423 * DRA7xx and AM57xx variants. Confirm availability in
424 * the data manual for the exact part number in use
425 * before enabling these nodes in the board dts file.
427 ocmcram2: ocmcram@40400000 {
429 compatible = "mmio-sram";
430 reg = <0x40400000 0x100000>;
431 ranges = <0x0 0x40400000 0x100000>;
432 #address-cells = <1>;
436 ocmcram3: ocmcram@40500000 {
438 compatible = "mmio-sram";
439 reg = <0x40500000 0x100000>;
440 ranges = <0x0 0x40500000 0x100000>;
441 #address-cells = <1>;
445 bandgap: bandgap@4a0021e0 {
446 reg = <0x4a0021e0 0xc
452 compatible = "ti,dra752-bandgap";
453 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
454 #thermal-sensor-cells = <1>;
457 dsp1_system: dsp_system@40d00000 {
458 compatible = "syscon";
459 reg = <0x40d00000 0x100>;
462 dra7_iodelay_core: padconf@4844a000 {
463 compatible = "ti,dra7-iodelay";
464 reg = <0x4844a000 0x0d1c>;
465 #address-cells = <1>;
467 #pinctrl-cells = <2>;
470 sdma: dma-controller@4a056000 {
471 compatible = "ti,omap4430-sdma";
472 reg = <0x4a056000 0x1000>;
473 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
479 dma-requests = <127>;
480 ti,hwmods = "dma_system";
483 edma: edma@43300000 {
484 compatible = "ti,edma3-tpcc";
486 reg = <0x43300000 0x100000>;
487 reg-names = "edma3_cc";
488 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
491 interrupt-names = "edma3_ccint", "edma3_mperr",
496 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
499 * memcpy is disabled, can be enabled with:
500 * ti,edma-memcpy-channels = <20 21>;
501 * for example. Note that these channels need to be
502 * masked in the xbar as well.
506 edma_tptc0: tptc@43400000 {
507 compatible = "ti,edma3-tptc";
509 reg = <0x43400000 0x100000>;
510 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
511 interrupt-names = "edma3_tcerrint";
514 edma_tptc1: tptc@43500000 {
515 compatible = "ti,edma3-tptc";
517 reg = <0x43500000 0x100000>;
518 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
519 interrupt-names = "edma3_tcerrint";
522 gpio1: gpio@4ae10000 {
523 compatible = "ti,omap4-gpio";
524 reg = <0x4ae10000 0x200>;
525 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
529 interrupt-controller;
530 #interrupt-cells = <2>;
533 gpio2: gpio@48055000 {
534 compatible = "ti,omap4-gpio";
535 reg = <0x48055000 0x200>;
536 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
540 interrupt-controller;
541 #interrupt-cells = <2>;
544 gpio3: gpio@48057000 {
545 compatible = "ti,omap4-gpio";
546 reg = <0x48057000 0x200>;
547 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
551 interrupt-controller;
552 #interrupt-cells = <2>;
555 gpio4: gpio@48059000 {
556 compatible = "ti,omap4-gpio";
557 reg = <0x48059000 0x200>;
558 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
562 interrupt-controller;
563 #interrupt-cells = <2>;
566 gpio5: gpio@4805b000 {
567 compatible = "ti,omap4-gpio";
568 reg = <0x4805b000 0x200>;
569 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
577 gpio6: gpio@4805d000 {
578 compatible = "ti,omap4-gpio";
579 reg = <0x4805d000 0x200>;
580 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
588 gpio7: gpio@48051000 {
589 compatible = "ti,omap4-gpio";
590 reg = <0x48051000 0x200>;
591 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
599 gpio8: gpio@48053000 {
600 compatible = "ti,omap4-gpio";
601 reg = <0x48053000 0x200>;
602 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
606 interrupt-controller;
607 #interrupt-cells = <2>;
610 uart1: serial@4806a000 {
611 compatible = "ti,dra742-uart", "ti,omap4-uart";
612 reg = <0x4806a000 0x100>;
613 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
615 clock-frequency = <48000000>;
617 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
618 dma-names = "tx", "rx";
621 uart2: serial@4806c000 {
622 compatible = "ti,dra742-uart", "ti,omap4-uart";
623 reg = <0x4806c000 0x100>;
624 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
626 clock-frequency = <48000000>;
628 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
629 dma-names = "tx", "rx";
632 uart3: serial@48020000 {
633 compatible = "ti,dra742-uart", "ti,omap4-uart";
634 reg = <0x48020000 0x100>;
635 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
637 clock-frequency = <48000000>;
639 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
640 dma-names = "tx", "rx";
643 uart4: serial@4806e000 {
644 compatible = "ti,dra742-uart", "ti,omap4-uart";
645 reg = <0x4806e000 0x100>;
646 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
648 clock-frequency = <48000000>;
650 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
651 dma-names = "tx", "rx";
654 uart5: serial@48066000 {
655 compatible = "ti,dra742-uart", "ti,omap4-uart";
656 reg = <0x48066000 0x100>;
657 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
659 clock-frequency = <48000000>;
661 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
662 dma-names = "tx", "rx";
665 uart6: serial@48068000 {
666 compatible = "ti,dra742-uart", "ti,omap4-uart";
667 reg = <0x48068000 0x100>;
668 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
670 clock-frequency = <48000000>;
672 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
673 dma-names = "tx", "rx";
676 uart7: serial@48420000 {
677 compatible = "ti,dra742-uart", "ti,omap4-uart";
678 reg = <0x48420000 0x100>;
679 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
681 clock-frequency = <48000000>;
685 uart8: serial@48422000 {
686 compatible = "ti,dra742-uart", "ti,omap4-uart";
687 reg = <0x48422000 0x100>;
688 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
690 clock-frequency = <48000000>;
694 uart9: serial@48424000 {
695 compatible = "ti,dra742-uart", "ti,omap4-uart";
696 reg = <0x48424000 0x100>;
697 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
699 clock-frequency = <48000000>;
703 uart10: serial@4ae2b000 {
704 compatible = "ti,dra742-uart", "ti,omap4-uart";
705 reg = <0x4ae2b000 0x100>;
706 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
707 ti,hwmods = "uart10";
708 clock-frequency = <48000000>;
712 mailbox1: mailbox@4a0f4000 {
713 compatible = "ti,omap4-mailbox";
714 reg = <0x4a0f4000 0x200>;
715 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
718 ti,hwmods = "mailbox1";
720 ti,mbox-num-users = <3>;
721 ti,mbox-num-fifos = <8>;
725 mailbox2: mailbox@4883a000 {
726 compatible = "ti,omap4-mailbox";
727 reg = <0x4883a000 0x200>;
728 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
732 ti,hwmods = "mailbox2";
734 ti,mbox-num-users = <4>;
735 ti,mbox-num-fifos = <12>;
739 mailbox3: mailbox@4883c000 {
740 compatible = "ti,omap4-mailbox";
741 reg = <0x4883c000 0x200>;
742 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
746 ti,hwmods = "mailbox3";
748 ti,mbox-num-users = <4>;
749 ti,mbox-num-fifos = <12>;
753 mailbox4: mailbox@4883e000 {
754 compatible = "ti,omap4-mailbox";
755 reg = <0x4883e000 0x200>;
756 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
760 ti,hwmods = "mailbox4";
762 ti,mbox-num-users = <4>;
763 ti,mbox-num-fifos = <12>;
767 mailbox5: mailbox@48840000 {
768 compatible = "ti,omap4-mailbox";
769 reg = <0x48840000 0x200>;
770 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
774 ti,hwmods = "mailbox5";
776 ti,mbox-num-users = <4>;
777 ti,mbox-num-fifos = <12>;
781 mailbox6: mailbox@48842000 {
782 compatible = "ti,omap4-mailbox";
783 reg = <0x48842000 0x200>;
784 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
788 ti,hwmods = "mailbox6";
790 ti,mbox-num-users = <4>;
791 ti,mbox-num-fifos = <12>;
795 mailbox7: mailbox@48844000 {
796 compatible = "ti,omap4-mailbox";
797 reg = <0x48844000 0x200>;
798 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
799 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
800 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
801 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
802 ti,hwmods = "mailbox7";
804 ti,mbox-num-users = <4>;
805 ti,mbox-num-fifos = <12>;
809 mailbox8: mailbox@48846000 {
810 compatible = "ti,omap4-mailbox";
811 reg = <0x48846000 0x200>;
812 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
814 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
816 ti,hwmods = "mailbox8";
818 ti,mbox-num-users = <4>;
819 ti,mbox-num-fifos = <12>;
823 mailbox9: mailbox@4885e000 {
824 compatible = "ti,omap4-mailbox";
825 reg = <0x4885e000 0x200>;
826 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
829 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
830 ti,hwmods = "mailbox9";
832 ti,mbox-num-users = <4>;
833 ti,mbox-num-fifos = <12>;
837 mailbox10: mailbox@48860000 {
838 compatible = "ti,omap4-mailbox";
839 reg = <0x48860000 0x200>;
840 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
841 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
842 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
843 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
844 ti,hwmods = "mailbox10";
846 ti,mbox-num-users = <4>;
847 ti,mbox-num-fifos = <12>;
851 mailbox11: mailbox@48862000 {
852 compatible = "ti,omap4-mailbox";
853 reg = <0x48862000 0x200>;
854 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
855 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
856 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
858 ti,hwmods = "mailbox11";
860 ti,mbox-num-users = <4>;
861 ti,mbox-num-fifos = <12>;
865 mailbox12: mailbox@48864000 {
866 compatible = "ti,omap4-mailbox";
867 reg = <0x48864000 0x200>;
868 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
869 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
870 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
871 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
872 ti,hwmods = "mailbox12";
874 ti,mbox-num-users = <4>;
875 ti,mbox-num-fifos = <12>;
879 mailbox13: mailbox@48802000 {
880 compatible = "ti,omap4-mailbox";
881 reg = <0x48802000 0x200>;
882 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
886 ti,hwmods = "mailbox13";
888 ti,mbox-num-users = <4>;
889 ti,mbox-num-fifos = <12>;
893 timer1: timer@4ae18000 {
894 compatible = "ti,omap5430-timer";
895 reg = <0x4ae18000 0x80>;
896 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
897 ti,hwmods = "timer1";
900 clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
903 timer2: timer@48032000 {
904 compatible = "ti,omap5430-timer";
905 reg = <0x48032000 0x80>;
906 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
907 ti,hwmods = "timer2";
910 timer3: timer@48034000 {
911 compatible = "ti,omap5430-timer";
912 reg = <0x48034000 0x80>;
913 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
914 ti,hwmods = "timer3";
917 timer4: timer@48036000 {
918 compatible = "ti,omap5430-timer";
919 reg = <0x48036000 0x80>;
920 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
921 ti,hwmods = "timer4";
924 timer5: timer@48820000 {
925 compatible = "ti,omap5430-timer";
926 reg = <0x48820000 0x80>;
927 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
928 ti,hwmods = "timer5";
931 timer6: timer@48822000 {
932 compatible = "ti,omap5430-timer";
933 reg = <0x48822000 0x80>;
934 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
935 ti,hwmods = "timer6";
938 timer7: timer@48824000 {
939 compatible = "ti,omap5430-timer";
940 reg = <0x48824000 0x80>;
941 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
942 ti,hwmods = "timer7";
945 timer8: timer@48826000 {
946 compatible = "ti,omap5430-timer";
947 reg = <0x48826000 0x80>;
948 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
949 ti,hwmods = "timer8";
952 timer9: timer@4803e000 {
953 compatible = "ti,omap5430-timer";
954 reg = <0x4803e000 0x80>;
955 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
956 ti,hwmods = "timer9";
959 timer10: timer@48086000 {
960 compatible = "ti,omap5430-timer";
961 reg = <0x48086000 0x80>;
962 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
963 ti,hwmods = "timer10";
966 timer11: timer@48088000 {
967 compatible = "ti,omap5430-timer";
968 reg = <0x48088000 0x80>;
969 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
970 ti,hwmods = "timer11";
973 timer12: timer@4ae20000 {
974 compatible = "ti,omap5430-timer";
975 reg = <0x4ae20000 0x80>;
976 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
977 ti,hwmods = "timer12";
982 timer13: timer@48828000 {
983 compatible = "ti,omap5430-timer";
984 reg = <0x48828000 0x80>;
985 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
986 ti,hwmods = "timer13";
989 timer14: timer@4882a000 {
990 compatible = "ti,omap5430-timer";
991 reg = <0x4882a000 0x80>;
992 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
993 ti,hwmods = "timer14";
996 timer15: timer@4882c000 {
997 compatible = "ti,omap5430-timer";
998 reg = <0x4882c000 0x80>;
999 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
1000 ti,hwmods = "timer15";
1003 timer16: timer@4882e000 {
1004 compatible = "ti,omap5430-timer";
1005 reg = <0x4882e000 0x80>;
1006 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
1007 ti,hwmods = "timer16";
1010 wdt2: wdt@4ae14000 {
1011 compatible = "ti,omap3-wdt";
1012 reg = <0x4ae14000 0x80>;
1013 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1014 ti,hwmods = "wd_timer2";
1017 hwspinlock: spinlock@4a0f6000 {
1018 compatible = "ti,omap4-hwspinlock";
1019 reg = <0x4a0f6000 0x1000>;
1020 ti,hwmods = "spinlock";
1021 #hwlock-cells = <1>;
1025 compatible = "ti,omap5-dmm";
1026 reg = <0x4e000000 0x800>;
1027 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1031 i2c1: i2c@48070000 {
1032 compatible = "ti,omap4-i2c";
1033 reg = <0x48070000 0x100>;
1034 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cells = <1>;
1038 status = "disabled";
1041 i2c2: i2c@48072000 {
1042 compatible = "ti,omap4-i2c";
1043 reg = <0x48072000 0x100>;
1044 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1045 #address-cells = <1>;
1048 status = "disabled";
1051 i2c3: i2c@48060000 {
1052 compatible = "ti,omap4-i2c";
1053 reg = <0x48060000 0x100>;
1054 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1055 #address-cells = <1>;
1058 status = "disabled";
1061 i2c4: i2c@4807a000 {
1062 compatible = "ti,omap4-i2c";
1063 reg = <0x4807a000 0x100>;
1064 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1065 #address-cells = <1>;
1068 status = "disabled";
1071 i2c5: i2c@4807c000 {
1072 compatible = "ti,omap4-i2c";
1073 reg = <0x4807c000 0x100>;
1074 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1075 #address-cells = <1>;
1078 status = "disabled";
1081 mmc1: mmc@4809c000 {
1082 compatible = "ti,omap4-hsmmc";
1083 reg = <0x4809c000 0x400>;
1084 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1087 ti,needs-special-reset;
1088 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
1089 dma-names = "tx", "rx";
1090 status = "disabled";
1091 pbias-supply = <&pbias_mmc_reg>;
1092 max-frequency = <192000000>;
1095 hdqw1w: 1w@480b2000 {
1096 compatible = "ti,omap3-1w";
1097 reg = <0x480b2000 0x1000>;
1098 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1099 ti,hwmods = "hdq1w";
1102 mmc2: mmc@480b4000 {
1103 compatible = "ti,omap4-hsmmc";
1104 reg = <0x480b4000 0x400>;
1105 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1107 ti,needs-special-reset;
1108 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
1109 dma-names = "tx", "rx";
1110 status = "disabled";
1111 max-frequency = <192000000>;
1114 mmc3: mmc@480ad000 {
1115 compatible = "ti,omap4-hsmmc";
1116 reg = <0x480ad000 0x400>;
1117 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1119 ti,needs-special-reset;
1120 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
1121 dma-names = "tx", "rx";
1122 status = "disabled";
1123 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
1124 max-frequency = <64000000>;
1127 mmc4: mmc@480d1000 {
1128 compatible = "ti,omap4-hsmmc";
1129 reg = <0x480d1000 0x400>;
1130 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1132 ti,needs-special-reset;
1133 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
1134 dma-names = "tx", "rx";
1135 status = "disabled";
1136 max-frequency = <192000000>;
1139 mmu0_dsp1: mmu@40d01000 {
1140 compatible = "ti,dra7-dsp-iommu";
1141 reg = <0x40d01000 0x100>;
1142 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1143 ti,hwmods = "mmu0_dsp1";
1145 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1146 status = "disabled";
1149 mmu1_dsp1: mmu@40d02000 {
1150 compatible = "ti,dra7-dsp-iommu";
1151 reg = <0x40d02000 0x100>;
1152 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1153 ti,hwmods = "mmu1_dsp1";
1155 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1156 status = "disabled";
1159 mmu_ipu1: mmu@58882000 {
1160 compatible = "ti,dra7-iommu";
1161 reg = <0x58882000 0x100>;
1162 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1163 ti,hwmods = "mmu_ipu1";
1165 ti,iommu-bus-err-back;
1166 status = "disabled";
1169 mmu_ipu2: mmu@55082000 {
1170 compatible = "ti,dra7-iommu";
1171 reg = <0x55082000 0x100>;
1172 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1173 ti,hwmods = "mmu_ipu2";
1175 ti,iommu-bus-err-back;
1176 status = "disabled";
1179 abb_mpu: regulator-abb-mpu {
1180 compatible = "ti,abb-v3";
1181 regulator-name = "abb_mpu";
1182 #address-cells = <0>;
1184 clocks = <&sys_clkin1>;
1185 ti,settling-time = <50>;
1186 ti,clock-cycles = <16>;
1188 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1189 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1191 reg-names = "setup-address", "control-address",
1192 "int-address", "efuse-address",
1194 ti,tranxdone-status-mask = <0x80>;
1195 /* LDOVBBMPU_FBB_MUX_CTRL */
1196 ti,ldovbb-override-mask = <0x400>;
1197 /* LDOVBBMPU_FBB_VSET_OUT */
1198 ti,ldovbb-vset-mask = <0x1F>;
1201 * NOTE: only FBB mode used but actual vset will
1202 * determine final biasing
1205 /*uV ABB efuse rbb_m fbb_m vset_m*/
1206 1060000 0 0x0 0 0x02000000 0x01F00000
1207 1160000 0 0x4 0 0x02000000 0x01F00000
1208 1210000 0 0x8 0 0x02000000 0x01F00000
1212 abb_ivahd: regulator-abb-ivahd {
1213 compatible = "ti,abb-v3";
1214 regulator-name = "abb_ivahd";
1215 #address-cells = <0>;
1217 clocks = <&sys_clkin1>;
1218 ti,settling-time = <50>;
1219 ti,clock-cycles = <16>;
1221 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1222 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1224 reg-names = "setup-address", "control-address",
1225 "int-address", "efuse-address",
1227 ti,tranxdone-status-mask = <0x40000000>;
1228 /* LDOVBBIVA_FBB_MUX_CTRL */
1229 ti,ldovbb-override-mask = <0x400>;
1230 /* LDOVBBIVA_FBB_VSET_OUT */
1231 ti,ldovbb-vset-mask = <0x1F>;
1234 * NOTE: only FBB mode used but actual vset will
1235 * determine final biasing
1238 /*uV ABB efuse rbb_m fbb_m vset_m*/
1239 1055000 0 0x0 0 0x02000000 0x01F00000
1240 1150000 0 0x4 0 0x02000000 0x01F00000
1241 1250000 0 0x8 0 0x02000000 0x01F00000
1245 abb_dspeve: regulator-abb-dspeve {
1246 compatible = "ti,abb-v3";
1247 regulator-name = "abb_dspeve";
1248 #address-cells = <0>;
1250 clocks = <&sys_clkin1>;
1251 ti,settling-time = <50>;
1252 ti,clock-cycles = <16>;
1254 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1255 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1257 reg-names = "setup-address", "control-address",
1258 "int-address", "efuse-address",
1260 ti,tranxdone-status-mask = <0x20000000>;
1261 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1262 ti,ldovbb-override-mask = <0x400>;
1263 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1264 ti,ldovbb-vset-mask = <0x1F>;
1267 * NOTE: only FBB mode used but actual vset will
1268 * determine final biasing
1271 /*uV ABB efuse rbb_m fbb_m vset_m*/
1272 1055000 0 0x0 0 0x02000000 0x01F00000
1273 1150000 0 0x4 0 0x02000000 0x01F00000
1274 1250000 0 0x8 0 0x02000000 0x01F00000
1278 abb_gpu: regulator-abb-gpu {
1279 compatible = "ti,abb-v3";
1280 regulator-name = "abb_gpu";
1281 #address-cells = <0>;
1283 clocks = <&sys_clkin1>;
1284 ti,settling-time = <50>;
1285 ti,clock-cycles = <16>;
1287 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1288 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1290 reg-names = "setup-address", "control-address",
1291 "int-address", "efuse-address",
1293 ti,tranxdone-status-mask = <0x10000000>;
1294 /* LDOVBBGPU_FBB_MUX_CTRL */
1295 ti,ldovbb-override-mask = <0x400>;
1296 /* LDOVBBGPU_FBB_VSET_OUT */
1297 ti,ldovbb-vset-mask = <0x1F>;
1300 * NOTE: only FBB mode used but actual vset will
1301 * determine final biasing
1304 /*uV ABB efuse rbb_m fbb_m vset_m*/
1305 1090000 0 0x0 0 0x02000000 0x01F00000
1306 1210000 0 0x4 0 0x02000000 0x01F00000
1307 1280000 0 0x8 0 0x02000000 0x01F00000
1311 mcspi1: spi@48098000 {
1312 compatible = "ti,omap4-mcspi";
1313 reg = <0x48098000 0x200>;
1314 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1315 #address-cells = <1>;
1317 ti,hwmods = "mcspi1";
1318 ti,spi-num-cs = <4>;
1319 dmas = <&sdma_xbar 35>,
1327 dma-names = "tx0", "rx0", "tx1", "rx1",
1328 "tx2", "rx2", "tx3", "rx3";
1329 status = "disabled";
1332 mcspi2: spi@4809a000 {
1333 compatible = "ti,omap4-mcspi";
1334 reg = <0x4809a000 0x200>;
1335 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1336 #address-cells = <1>;
1338 ti,hwmods = "mcspi2";
1339 ti,spi-num-cs = <2>;
1340 dmas = <&sdma_xbar 43>,
1344 dma-names = "tx0", "rx0", "tx1", "rx1";
1345 status = "disabled";
1348 mcspi3: spi@480b8000 {
1349 compatible = "ti,omap4-mcspi";
1350 reg = <0x480b8000 0x200>;
1351 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1352 #address-cells = <1>;
1354 ti,hwmods = "mcspi3";
1355 ti,spi-num-cs = <2>;
1356 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1357 dma-names = "tx0", "rx0";
1358 status = "disabled";
1361 mcspi4: spi@480ba000 {
1362 compatible = "ti,omap4-mcspi";
1363 reg = <0x480ba000 0x200>;
1364 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1365 #address-cells = <1>;
1367 ti,hwmods = "mcspi4";
1368 ti,spi-num-cs = <1>;
1369 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1370 dma-names = "tx0", "rx0";
1371 status = "disabled";
1374 qspi: qspi@4b300000 {
1375 compatible = "ti,dra7xxx-qspi";
1376 reg = <0x4b300000 0x100>,
1377 <0x5c000000 0x4000000>;
1378 reg-names = "qspi_base", "qspi_mmap";
1379 syscon-chipselects = <&scm_conf 0x558>;
1380 #address-cells = <1>;
1383 clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>;
1384 clock-names = "fck";
1386 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1387 status = "disabled";
1392 compatible = "ti,omap-ocp2scp";
1393 #address-cells = <1>;
1396 reg = <0x4a090000 0x20>;
1397 ti,hwmods = "ocp2scp3";
1398 sata_phy: phy@4a096000 {
1399 compatible = "ti,phy-pipe3-sata";
1400 reg = <0x4A096000 0x80>, /* phy_rx */
1401 <0x4A096400 0x64>, /* phy_tx */
1402 <0x4A096800 0x40>; /* pll_ctrl */
1403 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1404 syscon-phy-power = <&scm_conf 0x374>;
1405 clocks = <&sys_clkin1>,
1406 <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
1407 clock-names = "sysclk", "refclk";
1408 syscon-pllreset = <&scm_conf 0x3fc>;
1412 pcie1_phy: pciephy@4a094000 {
1413 compatible = "ti,phy-pipe3-pcie";
1414 reg = <0x4a094000 0x80>, /* phy_rx */
1415 <0x4a094400 0x64>; /* phy_tx */
1416 reg-names = "phy_rx", "phy_tx";
1417 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1418 syscon-pcs = <&scm_conf_pcie 0x10>;
1419 clocks = <&dpll_pcie_ref_ck>,
1420 <&dpll_pcie_ref_m2ldo_ck>,
1421 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>,
1422 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>,
1423 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>,
1424 <&optfclk_pciephy_div>,
1426 clock-names = "dpll_ref", "dpll_ref_m2",
1427 "wkupclk", "refclk",
1428 "div-clk", "phy-div", "sysclk";
1432 pcie2_phy: pciephy@4a095000 {
1433 compatible = "ti,phy-pipe3-pcie";
1434 reg = <0x4a095000 0x80>, /* phy_rx */
1435 <0x4a095400 0x64>; /* phy_tx */
1436 reg-names = "phy_rx", "phy_tx";
1437 syscon-phy-power = <&scm_conf_pcie 0x20>;
1438 syscon-pcs = <&scm_conf_pcie 0x10>;
1439 clocks = <&dpll_pcie_ref_ck>,
1440 <&dpll_pcie_ref_m2ldo_ck>,
1441 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>,
1442 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>,
1443 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>,
1444 <&optfclk_pciephy_div>,
1446 clock-names = "dpll_ref", "dpll_ref_m2",
1447 "wkupclk", "refclk",
1448 "div-clk", "phy-div", "sysclk";
1450 status = "disabled";
1454 sata: sata@4a141100 {
1455 compatible = "snps,dwc-ahci";
1456 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1457 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1459 phy-names = "sata-phy";
1460 clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
1462 ports-implemented = <0x1>;
1466 compatible = "ti,am3352-rtc";
1467 reg = <0x48838000 0x100>;
1468 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1470 ti,hwmods = "rtcss";
1471 clocks = <&sys_32k_ck>;
1476 compatible = "ti,omap-ocp2scp";
1477 #address-cells = <1>;
1480 reg = <0x4a080000 0x20>;
1481 ti,hwmods = "ocp2scp1";
1483 usb2_phy1: phy@4a084000 {
1484 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1485 reg = <0x4a084000 0x400>;
1486 syscon-phy-power = <&scm_conf 0x300>;
1487 clocks = <&usb_phy1_always_on_clk32k>,
1488 <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
1489 clock-names = "wkupclk",
1494 usb2_phy2: phy@4a085000 {
1495 compatible = "ti,dra7x-usb2-phy2",
1497 reg = <0x4a085000 0x400>;
1498 syscon-phy-power = <&scm_conf 0xe74>;
1499 clocks = <&usb_phy2_always_on_clk32k>,
1500 <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>;
1501 clock-names = "wkupclk",
1506 usb3_phy1: phy@4a084400 {
1507 compatible = "ti,omap-usb3";
1508 reg = <0x4a084400 0x80>,
1511 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1512 syscon-phy-power = <&scm_conf 0x370>;
1513 clocks = <&usb_phy3_always_on_clk32k>,
1515 <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
1516 clock-names = "wkupclk",
1523 target-module@4a0dd000 {
1524 compatible = "ti,sysc-omap4-sr";
1525 ti,hwmods = "smartreflex_core";
1526 reg = <0x4a0dd000 0x4>,
1528 reg-names = "rev", "sysc";
1529 #address-cells = <1>;
1531 ranges = <0 0x4a0dd000 0x001000>;
1533 /* SmartReflex child device marked reserved in TRM */
1536 target-module@4a0d9000 {
1537 compatible = "ti,sysc-omap4-sr";
1538 ti,hwmods = "smartreflex_mpu";
1539 reg = <0x4a0d9000 0x4>,
1541 reg-names = "rev", "sysc";
1542 #address-cells = <1>;
1544 ranges = <0 0x4a0d9000 0x001000>;
1546 /* SmartReflex child device marked reserved in TRM */
1549 omap_dwc3_1: omap_dwc3_1@48880000 {
1550 compatible = "ti,dwc3";
1551 ti,hwmods = "usb_otg_ss1";
1552 reg = <0x48880000 0x10000>;
1553 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1554 #address-cells = <1>;
1558 usb1: usb@48890000 {
1559 compatible = "snps,dwc3";
1560 reg = <0x48890000 0x17000>;
1561 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1564 interrupt-names = "peripheral",
1567 phys = <&usb2_phy1>, <&usb3_phy1>;
1568 phy-names = "usb2-phy", "usb3-phy";
1569 maximum-speed = "super-speed";
1571 snps,dis_u3_susphy_quirk;
1572 snps,dis_u2_susphy_quirk;
1573 snps,dis_metastability_quirk;
1577 omap_dwc3_2: omap_dwc3_2@488c0000 {
1578 compatible = "ti,dwc3";
1579 ti,hwmods = "usb_otg_ss2";
1580 reg = <0x488c0000 0x10000>;
1581 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1582 #address-cells = <1>;
1586 usb2: usb@488d0000 {
1587 compatible = "snps,dwc3";
1588 reg = <0x488d0000 0x17000>;
1589 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1590 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1591 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1592 interrupt-names = "peripheral",
1595 phys = <&usb2_phy2>;
1596 phy-names = "usb2-phy";
1597 maximum-speed = "high-speed";
1599 snps,dis_u3_susphy_quirk;
1600 snps,dis_u2_susphy_quirk;
1604 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1605 omap_dwc3_3: omap_dwc3_3@48900000 {
1606 compatible = "ti,dwc3";
1607 ti,hwmods = "usb_otg_ss3";
1608 reg = <0x48900000 0x10000>;
1609 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1610 #address-cells = <1>;
1614 status = "disabled";
1615 usb3: usb@48910000 {
1616 compatible = "snps,dwc3";
1617 reg = <0x48910000 0x17000>;
1618 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1619 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1620 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1621 interrupt-names = "peripheral",
1624 maximum-speed = "high-speed";
1626 snps,dis_u3_susphy_quirk;
1627 snps,dis_u2_susphy_quirk;
1632 compatible = "ti,am3352-elm";
1633 reg = <0x48078000 0xfc0>; /* device IO registers */
1634 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1636 status = "disabled";
1639 gpmc: gpmc@50000000 {
1640 compatible = "ti,am3352-gpmc";
1642 reg = <0x50000000 0x37c>; /* device IO registers */
1643 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1644 dmas = <&edma_xbar 4 0>;
1647 gpmc,num-waitpins = <2>;
1648 #address-cells = <2>;
1650 interrupt-controller;
1651 #interrupt-cells = <2>;
1654 status = "disabled";
1658 compatible = "ti,dra7-atl";
1659 reg = <0x4843c000 0x3ff>;
1661 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1662 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1663 clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
1664 clock-names = "fck";
1665 status = "disabled";
1668 mcasp1: mcasp@48460000 {
1669 compatible = "ti,dra7-mcasp-audio";
1670 ti,hwmods = "mcasp1";
1671 reg = <0x48460000 0x2000>,
1672 <0x45800000 0x1000>;
1673 reg-names = "mpu","dat";
1674 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1675 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1676 interrupt-names = "tx", "rx";
1677 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1678 dma-names = "tx", "rx";
1679 clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>,
1680 <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>;
1681 clock-names = "fck", "ahclkx", "ahclkr";
1682 status = "disabled";
1685 mcasp2: mcasp@48464000 {
1686 compatible = "ti,dra7-mcasp-audio";
1687 ti,hwmods = "mcasp2";
1688 reg = <0x48464000 0x2000>,
1689 <0x45c00000 0x1000>;
1690 reg-names = "mpu","dat";
1691 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1692 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1693 interrupt-names = "tx", "rx";
1694 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1695 dma-names = "tx", "rx";
1696 clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>,
1697 <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>,
1698 <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>;
1699 clock-names = "fck", "ahclkx", "ahclkr";
1700 status = "disabled";
1703 mcasp3: mcasp@48468000 {
1704 compatible = "ti,dra7-mcasp-audio";
1705 ti,hwmods = "mcasp3";
1706 reg = <0x48468000 0x2000>,
1707 <0x46000000 0x1000>;
1708 reg-names = "mpu","dat";
1709 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1710 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1711 interrupt-names = "tx", "rx";
1712 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1713 dma-names = "tx", "rx";
1714 clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>,
1715 <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
1716 clock-names = "fck", "ahclkx";
1717 status = "disabled";
1720 mcasp4: mcasp@4846c000 {
1721 compatible = "ti,dra7-mcasp-audio";
1722 ti,hwmods = "mcasp4";
1723 reg = <0x4846c000 0x2000>,
1724 <0x48436000 0x1000>;
1725 reg-names = "mpu","dat";
1726 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1727 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1728 interrupt-names = "tx", "rx";
1729 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1730 dma-names = "tx", "rx";
1731 clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>,
1732 <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>;
1733 clock-names = "fck", "ahclkx";
1734 status = "disabled";
1737 mcasp5: mcasp@48470000 {
1738 compatible = "ti,dra7-mcasp-audio";
1739 ti,hwmods = "mcasp5";
1740 reg = <0x48470000 0x2000>,
1741 <0x4843a000 0x1000>;
1742 reg-names = "mpu","dat";
1743 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1745 interrupt-names = "tx", "rx";
1746 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1747 dma-names = "tx", "rx";
1748 clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>,
1749 <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>;
1750 clock-names = "fck", "ahclkx";
1751 status = "disabled";
1754 mcasp6: mcasp@48474000 {
1755 compatible = "ti,dra7-mcasp-audio";
1756 ti,hwmods = "mcasp6";
1757 reg = <0x48474000 0x2000>,
1758 <0x4844c000 0x1000>;
1759 reg-names = "mpu","dat";
1760 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1762 interrupt-names = "tx", "rx";
1763 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1764 dma-names = "tx", "rx";
1765 clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>,
1766 <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>;
1767 clock-names = "fck", "ahclkx";
1768 status = "disabled";
1771 mcasp7: mcasp@48478000 {
1772 compatible = "ti,dra7-mcasp-audio";
1773 ti,hwmods = "mcasp7";
1774 reg = <0x48478000 0x2000>,
1775 <0x48450000 0x1000>;
1776 reg-names = "mpu","dat";
1777 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1778 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1779 interrupt-names = "tx", "rx";
1780 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1781 dma-names = "tx", "rx";
1782 clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>,
1783 <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>;
1784 clock-names = "fck", "ahclkx";
1785 status = "disabled";
1788 mcasp8: mcasp@4847c000 {
1789 compatible = "ti,dra7-mcasp-audio";
1790 ti,hwmods = "mcasp8";
1791 reg = <0x4847c000 0x2000>,
1792 <0x48454000 0x1000>;
1793 reg-names = "mpu","dat";
1794 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1795 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1796 interrupt-names = "tx", "rx";
1797 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1798 dma-names = "tx", "rx";
1799 clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>,
1800 <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>;
1801 clock-names = "fck", "ahclkx";
1802 status = "disabled";
1805 crossbar_mpu: crossbar@4a002a48 {
1806 compatible = "ti,irq-crossbar";
1807 reg = <0x4a002a48 0x130>;
1808 interrupt-controller;
1809 interrupt-parent = <&wakeupgen>;
1810 #interrupt-cells = <3>;
1811 ti,max-irqs = <160>;
1812 ti,max-crossbar-sources = <MAX_SOURCES>;
1814 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1815 ti,irqs-skip = <10 133 139 140>;
1816 ti,irqs-safe-map = <0>;
1819 mac: ethernet@48484000 {
1820 compatible = "ti,dra7-cpsw","ti,cpsw";
1822 clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>;
1823 clock-names = "fck", "cpts";
1824 cpdma_channels = <8>;
1825 ale_entries = <1024>;
1826 bd_ram_size = <0x2000>;
1827 mac_control = <0x20>;
1830 cpts_clock_mult = <0x784CFE14>;
1831 cpts_clock_shift = <29>;
1832 reg = <0x48484000 0x1000
1834 #address-cells = <1>;
1838 * Do not allow gating of cpsw clock as workaround
1839 * for errata i877. Keeping internal clock disabled
1840 * causes the device switching characteristics
1841 * to degrade over time and eventually fail to meet
1842 * the data manual delay time/skew specs.
1852 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1854 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1855 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1857 syscon = <&scm_conf>;
1858 status = "disabled";
1860 davinci_mdio: mdio@48485000 {
1861 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1862 #address-cells = <1>;
1864 ti,hwmods = "davinci_mdio";
1865 bus_freq = <1000000>;
1866 reg = <0x48485000 0x100>;
1869 cpsw_emac0: slave@48480200 {
1870 /* Filled in by U-Boot */
1871 mac-address = [ 00 00 00 00 00 00 ];
1874 cpsw_emac1: slave@48480300 {
1875 /* Filled in by U-Boot */
1876 mac-address = [ 00 00 00 00 00 00 ];
1879 phy_sel: cpsw-phy-sel@4a002554 {
1880 compatible = "ti,dra7xx-cpsw-phy-sel";
1881 reg= <0x4a002554 0x4>;
1882 reg-names = "gmii-sel";
1886 dcan1: can@481cc000 {
1887 compatible = "ti,dra7-d_can";
1888 ti,hwmods = "dcan1";
1889 reg = <0x4ae3c000 0x2000>;
1890 syscon-raminit = <&scm_conf 0x558 0>;
1891 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1892 clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>;
1893 status = "disabled";
1896 dcan2: can@481d0000 {
1897 compatible = "ti,dra7-d_can";
1898 ti,hwmods = "dcan2";
1899 reg = <0x48480000 0x2000>;
1900 syscon-raminit = <&scm_conf 0x558 1>;
1901 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1902 clocks = <&sys_clkin1>;
1903 status = "disabled";
1907 compatible = "ti,dra7-dss";
1908 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1909 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1910 status = "disabled";
1911 ti,hwmods = "dss_core";
1912 /* CTRL_CORE_DSS_PLL_CONTROL */
1913 syscon-pll-ctrl = <&scm_conf 0x538>;
1914 #address-cells = <1>;
1919 compatible = "ti,dra7-dispc";
1920 reg = <0x58001000 0x1000>;
1921 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1922 ti,hwmods = "dss_dispc";
1923 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
1924 clock-names = "fck";
1925 /* CTRL_CORE_SMA_SW_1 */
1926 syscon-pol = <&scm_conf 0x534>;
1929 hdmi: encoder@58060000 {
1930 compatible = "ti,dra7-hdmi";
1931 reg = <0x58040000 0x200>,
1934 <0x58060000 0x19000>;
1935 reg-names = "wp", "pll", "phy", "core";
1936 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1937 status = "disabled";
1938 ti,hwmods = "dss_hdmi";
1939 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
1940 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>;
1941 clock-names = "fck", "sys_clk";
1942 dmas = <&sdma_xbar 76>;
1943 dma-names = "audio_tx";
1947 epwmss0: epwmss@4843e000 {
1948 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1949 reg = <0x4843e000 0x30>;
1950 ti,hwmods = "epwmss0";
1951 #address-cells = <1>;
1953 status = "disabled";
1956 ehrpwm0: pwm@4843e200 {
1957 compatible = "ti,dra746-ehrpwm",
1960 reg = <0x4843e200 0x80>;
1961 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1962 clock-names = "tbclk", "fck";
1963 status = "disabled";
1966 ecap0: ecap@4843e100 {
1967 compatible = "ti,dra746-ecap",
1970 reg = <0x4843e100 0x80>;
1971 clocks = <&l4_root_clk_div>;
1972 clock-names = "fck";
1973 status = "disabled";
1977 epwmss1: epwmss@48440000 {
1978 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1979 reg = <0x48440000 0x30>;
1980 ti,hwmods = "epwmss1";
1981 #address-cells = <1>;
1983 status = "disabled";
1986 ehrpwm1: pwm@48440200 {
1987 compatible = "ti,dra746-ehrpwm",
1990 reg = <0x48440200 0x80>;
1991 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1992 clock-names = "tbclk", "fck";
1993 status = "disabled";
1996 ecap1: ecap@48440100 {
1997 compatible = "ti,dra746-ecap",
2000 reg = <0x48440100 0x80>;
2001 clocks = <&l4_root_clk_div>;
2002 clock-names = "fck";
2003 status = "disabled";
2007 epwmss2: epwmss@48442000 {
2008 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2009 reg = <0x48442000 0x30>;
2010 ti,hwmods = "epwmss2";
2011 #address-cells = <1>;
2013 status = "disabled";
2016 ehrpwm2: pwm@48442200 {
2017 compatible = "ti,dra746-ehrpwm",
2020 reg = <0x48442200 0x80>;
2021 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2022 clock-names = "tbclk", "fck";
2023 status = "disabled";
2026 ecap2: ecap@48442100 {
2027 compatible = "ti,dra746-ecap",
2030 reg = <0x48442100 0x80>;
2031 clocks = <&l4_root_clk_div>;
2032 clock-names = "fck";
2033 status = "disabled";
2037 aes1: aes@4b500000 {
2038 compatible = "ti,omap4-aes";
2040 reg = <0x4b500000 0xa0>;
2041 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
2042 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
2043 dma-names = "tx", "rx";
2044 clocks = <&l3_iclk_div>;
2045 clock-names = "fck";
2048 aes2: aes@4b700000 {
2049 compatible = "ti,omap4-aes";
2051 reg = <0x4b700000 0xa0>;
2052 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
2053 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
2054 dma-names = "tx", "rx";
2055 clocks = <&l3_iclk_div>;
2056 clock-names = "fck";
2060 compatible = "ti,omap4-des";
2062 reg = <0x480a5000 0xa0>;
2063 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2064 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
2065 dma-names = "tx", "rx";
2066 clocks = <&l3_iclk_div>;
2067 clock-names = "fck";
2070 sham: sham@53100000 {
2071 compatible = "ti,omap5-sham";
2073 reg = <0x4b101000 0x300>;
2074 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
2075 dmas = <&edma_xbar 119 0>;
2077 clocks = <&l3_iclk_div>;
2078 clock-names = "fck";
2082 compatible = "ti,omap4-rng";
2084 reg = <0x48090000 0x2000>;
2085 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2086 clocks = <&l3_iclk_div>;
2087 clock-names = "fck";
2090 opp_supply_mpu: opp-supply@4a003b20 {
2091 compatible = "ti,omap5-opp-supply";
2092 reg = <0x4a003b20 0xc>;
2093 ti,efuse-settings = <
2099 ti,absolute-max-voltage-uv = <1500000>;
2104 thermal_zones: thermal-zones {
2105 #include "omap4-cpu-thermal.dtsi"
2106 #include "omap5-gpu-thermal.dtsi"
2107 #include "omap5-core-thermal.dtsi"
2108 #include "dra7-dspeve-thermal.dtsi"
2109 #include "dra7-iva-thermal.dtsi"
2115 polling-delay = <500>; /* milliseconds */
2116 coefficients = <0 2000>;
2120 coefficients = <0 2000>;
2124 coefficients = <0 2000>;
2128 coefficients = <0 2000>;
2132 coefficients = <0 2000>;
2136 temperature = <120000>; /* milli Celsius */
2139 #include "dra7xx-clocks.dtsi"