1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
7 compatible = "aspeed,ast2500";
10 interrupt-parent = <&vic>;
40 compatible = "arm,arm1176jzf-s";
47 device_type = "memory";
52 compatible = "simple-bus";
58 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
61 compatible = "aspeed,ast2500-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
67 compatible = "jedec,spi-nor";
68 spi-max-frequency = <50000000>;
69 spi-rx-bus-width = <2>;
74 compatible = "jedec,spi-nor";
75 spi-max-frequency = <50000000>;
76 spi-rx-bus-width = <2>;
81 compatible = "jedec,spi-nor";
82 spi-max-frequency = <50000000>;
83 spi-rx-bus-width = <2>;
89 reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
92 compatible = "aspeed,ast2500-spi";
93 clocks = <&syscon ASPEED_CLK_AHB>;
97 compatible = "jedec,spi-nor";
98 spi-max-frequency = <50000000>;
99 spi-rx-bus-width = <2>;
104 compatible = "jedec,spi-nor";
105 spi-max-frequency = <50000000>;
106 spi-rx-bus-width = <2>;
112 reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
113 #address-cells = <1>;
115 compatible = "aspeed,ast2500-spi";
116 clocks = <&syscon ASPEED_CLK_AHB>;
120 compatible = "jedec,spi-nor";
121 spi-max-frequency = <50000000>;
122 spi-rx-bus-width = <2>;
127 compatible = "jedec,spi-nor";
128 spi-max-frequency = <50000000>;
129 spi-rx-bus-width = <2>;
134 vic: interrupt-controller@1e6c0080 {
135 compatible = "aspeed,ast2400-vic";
136 interrupt-controller;
137 #interrupt-cells = <1>;
138 valid-sources = <0xfefff7ff 0x0807ffff>;
139 reg = <0x1e6c0080 0x80>;
142 cvic: copro-interrupt-controller@1e6c2000 {
143 compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
144 valid-sources = <0xffffffff>;
145 copro-sw-interrupts = <1>;
146 reg = <0x1e6c2000 0x80>;
149 mac0: ethernet@1e660000 {
150 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
151 reg = <0x1e660000 0x180>;
153 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
157 mac1: ethernet@1e680000 {
158 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
159 reg = <0x1e680000 0x180>;
161 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
165 ehci0: usb@1e6a1000 {
166 compatible = "aspeed,ast2500-ehci", "generic-ehci";
167 reg = <0x1e6a1000 0x100>;
169 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_usb2ah_default>;
175 ehci1: usb@1e6a3000 {
176 compatible = "aspeed,ast2500-ehci", "generic-ehci";
177 reg = <0x1e6a3000 0x100>;
179 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_usb2bh_default>;
186 compatible = "aspeed,ast2500-uhci", "generic-uhci";
187 reg = <0x1e6b0000 0x100>;
190 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
193 * No default pinmux, it will follow EHCI, use an explicit pinmux
194 * override if you don't enable EHCI
198 vhub: usb-vhub@1e6a0000 {
199 compatible = "aspeed,ast2500-usb-vhub";
200 reg = <0x1e6a0000 0x300>;
202 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
203 aspeed,vhub-downstream-ports = <5>;
204 aspeed,vhub-generic-endpoints = <15>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_usb2ad_default>;
211 compatible = "simple-bus";
212 #address-cells = <1>;
216 edac: memory-controller@1e6e0000 {
217 compatible = "aspeed,ast2500-sdram-edac";
218 reg = <0x1e6e0000 0x174>;
223 syscon: syscon@1e6e2000 {
224 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
225 reg = <0x1e6e2000 0x1a8>;
226 #address-cells = <1>;
228 ranges = <0 0x1e6e2000 0x1000>;
232 scu_ic: interrupt-controller@18 {
233 #interrupt-cells = <1>;
234 compatible = "aspeed,ast2500-scu-ic";
237 interrupt-controller;
240 p2a: p2a-control@2c {
241 compatible = "aspeed,ast2500-p2a-ctrl";
247 compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
248 reg = <0x7c 0x4 0x150 0x8>;
251 pinctrl: pinctrl@80 {
252 compatible = "aspeed,ast2500-pinctrl";
253 reg = <0x80 0x18>, <0xa0 0x10>;
254 aspeed,external-nodes = <&gfx>, <&lhc>;
258 rng: hwrng@1e6e2078 {
259 compatible = "timeriomem_rng";
260 reg = <0x1e6e2078 0x4>;
265 gfx: display@1e6e6000 {
266 compatible = "aspeed,ast2500-gfx", "syscon";
267 reg = <0x1e6e6000 0x1000>;
269 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
270 resets = <&syscon ASPEED_RESET_CRT1>;
276 xdma: xdma@1e6e7000 {
277 compatible = "aspeed,ast2500-xdma";
278 reg = <0x1e6e7000 0x100>;
279 clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
280 resets = <&syscon ASPEED_RESET_XDMA>;
281 interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>;
282 aspeed,pcie-device = "bmc";
283 aspeed,scu = <&syscon>;
288 compatible = "aspeed,ast2500-adc";
289 reg = <0x1e6e9000 0xb0>;
290 clocks = <&syscon ASPEED_CLK_APB>;
291 resets = <&syscon ASPEED_RESET_ADC>;
292 #io-channel-cells = <1>;
296 video: video@1e700000 {
297 compatible = "aspeed,ast2500-video-engine";
298 reg = <0x1e700000 0x1000>;
299 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
300 <&syscon ASPEED_CLK_GATE_ECLK>;
301 clock-names = "vclk", "eclk";
306 sram: sram@1e720000 {
307 compatible = "mmio-sram";
308 reg = <0x1e720000 0x9000>; // 36K
311 sdmmc: sd-controller@1e740000 {
312 compatible = "aspeed,ast2500-sd-controller";
313 reg = <0x1e740000 0x100>;
314 #address-cells = <1>;
316 ranges = <0 0x1e740000 0x10000>;
317 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
321 compatible = "aspeed,ast2500-sdhci";
325 clocks = <&syscon ASPEED_CLK_SDIO>;
330 compatible = "aspeed,ast2500-sdhci";
334 clocks = <&syscon ASPEED_CLK_SDIO>;
339 gpio: gpio@1e780000 {
342 compatible = "aspeed,ast2500-gpio";
343 reg = <0x1e780000 0x200>;
345 gpio-ranges = <&pinctrl 0 0 232>;
346 clocks = <&syscon ASPEED_CLK_APB>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
351 sgpio: sgpio@1e780200 {
353 compatible = "aspeed,ast2500-sgpio";
356 reg = <0x1e780200 0x0100>;
357 clocks = <&syscon ASPEED_CLK_APB>;
358 interrupt-controller;
359 bus-frequency = <12000000>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_sgpm_default>;
366 compatible = "aspeed,ast2500-rtc";
367 reg = <0x1e781000 0x18>;
371 timer: timer@1e782000 {
372 /* This timer is a Faraday FTTMR010 derivative */
373 compatible = "aspeed,ast2400-timer";
374 reg = <0x1e782000 0x90>;
375 interrupts = <16 17 18 35 36 37 38 39>;
376 clocks = <&syscon ASPEED_CLK_APB>;
377 clock-names = "PCLK";
380 uart1: serial@1e783000 {
381 compatible = "ns16550a";
382 reg = <0x1e783000 0x20>;
385 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
386 resets = <&lpc_reset 4>;
391 uart5: serial@1e784000 {
392 compatible = "ns16550a";
393 reg = <0x1e784000 0x20>;
396 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
401 wdt1: watchdog@1e785000 {
402 compatible = "aspeed,ast2500-wdt";
403 reg = <0x1e785000 0x20>;
404 clocks = <&syscon ASPEED_CLK_APB>;
407 wdt2: watchdog@1e785020 {
408 compatible = "aspeed,ast2500-wdt";
409 reg = <0x1e785020 0x20>;
410 clocks = <&syscon ASPEED_CLK_APB>;
413 wdt3: watchdog@1e785040 {
414 compatible = "aspeed,ast2500-wdt";
415 reg = <0x1e785040 0x20>;
416 clocks = <&syscon ASPEED_CLK_APB>;
420 pwm_tacho: pwm-tacho-controller@1e786000 {
421 compatible = "aspeed,ast2500-pwm-tacho";
422 #address-cells = <1>;
424 reg = <0x1e786000 0x1000>;
425 clocks = <&syscon ASPEED_CLK_24M>;
426 resets = <&syscon ASPEED_RESET_PWM>;
430 vuart: serial@1e787000 {
431 compatible = "aspeed,ast2500-vuart";
432 reg = <0x1e787000 0x40>;
435 clocks = <&syscon ASPEED_CLK_APB>;
441 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
442 reg = <0x1e789000 0x1000>;
445 #address-cells = <1>;
447 ranges = <0x0 0x1e789000 0x1000>;
450 compatible = "aspeed,ast2500-kcs-bmc-v2";
451 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
453 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
458 compatible = "aspeed,ast2500-kcs-bmc-v2";
459 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
461 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
466 compatible = "aspeed,ast2500-kcs-bmc-v2";
467 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
469 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
474 compatible = "aspeed,ast2500-kcs-bmc-v2";
475 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
477 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
481 lpc_ctrl: lpc-ctrl@80 {
482 compatible = "aspeed,ast2500-lpc-ctrl";
484 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
488 lpc_snoop: lpc-snoop@90 {
489 compatible = "aspeed,ast2500-lpc-snoop";
492 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
496 lpc_reset: reset-controller@98 {
497 compatible = "aspeed,ast2500-lpc-reset";
502 uart_routing: uart-routing@9c {
503 compatible = "aspeed,ast2500-uart-routing";
509 compatible = "aspeed,ast2500-lhc";
510 reg = <0xa0 0x24 0xc8 0x8>;
515 compatible = "aspeed,ast2500-ibt-bmc";
518 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
523 peci0: peci-controller@1e78b000 {
524 compatible = "aspeed,ast2500-peci";
525 reg = <0x1e78b000 0x60>;
527 clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
528 resets = <&syscon ASPEED_RESET_PECI>;
529 cmd-timeout-ms = <1000>;
530 clock-frequency = <1000000>;
534 uart2: serial@1e78d000 {
535 compatible = "ns16550a";
536 reg = <0x1e78d000 0x20>;
539 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
540 resets = <&lpc_reset 5>;
545 uart3: serial@1e78e000 {
546 compatible = "ns16550a";
547 reg = <0x1e78e000 0x20>;
550 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
551 resets = <&lpc_reset 6>;
556 uart4: serial@1e78f000 {
557 compatible = "ns16550a";
558 reg = <0x1e78f000 0x20>;
561 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
562 resets = <&lpc_reset 7>;
568 compatible = "simple-bus";
569 #address-cells = <1>;
571 ranges = <0 0x1e78a000 0x1000>;
578 i2c_ic: interrupt-controller@0 {
579 #interrupt-cells = <1>;
580 compatible = "aspeed,ast2500-i2c-ic";
583 interrupt-controller;
587 #address-cells = <1>;
589 #interrupt-cells = <1>;
592 compatible = "aspeed,ast2500-i2c-bus";
593 clocks = <&syscon ASPEED_CLK_APB>;
594 resets = <&syscon ASPEED_RESET_I2C>;
595 bus-frequency = <100000>;
597 interrupt-parent = <&i2c_ic>;
599 /* Does not need pinctrl properties */
603 #address-cells = <1>;
605 #interrupt-cells = <1>;
608 compatible = "aspeed,ast2500-i2c-bus";
609 clocks = <&syscon ASPEED_CLK_APB>;
610 resets = <&syscon ASPEED_RESET_I2C>;
611 bus-frequency = <100000>;
613 interrupt-parent = <&i2c_ic>;
615 /* Does not need pinctrl properties */
619 #address-cells = <1>;
621 #interrupt-cells = <1>;
624 compatible = "aspeed,ast2500-i2c-bus";
625 clocks = <&syscon ASPEED_CLK_APB>;
626 resets = <&syscon ASPEED_RESET_I2C>;
627 bus-frequency = <100000>;
629 interrupt-parent = <&i2c_ic>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&pinctrl_i2c3_default>;
636 #address-cells = <1>;
638 #interrupt-cells = <1>;
641 compatible = "aspeed,ast2500-i2c-bus";
642 clocks = <&syscon ASPEED_CLK_APB>;
643 resets = <&syscon ASPEED_RESET_I2C>;
644 bus-frequency = <100000>;
646 interrupt-parent = <&i2c_ic>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&pinctrl_i2c4_default>;
653 #address-cells = <1>;
655 #interrupt-cells = <1>;
658 compatible = "aspeed,ast2500-i2c-bus";
659 clocks = <&syscon ASPEED_CLK_APB>;
660 resets = <&syscon ASPEED_RESET_I2C>;
661 bus-frequency = <100000>;
663 interrupt-parent = <&i2c_ic>;
664 pinctrl-names = "default";
665 pinctrl-0 = <&pinctrl_i2c5_default>;
670 #address-cells = <1>;
672 #interrupt-cells = <1>;
675 compatible = "aspeed,ast2500-i2c-bus";
676 clocks = <&syscon ASPEED_CLK_APB>;
677 resets = <&syscon ASPEED_RESET_I2C>;
678 bus-frequency = <100000>;
680 interrupt-parent = <&i2c_ic>;
681 pinctrl-names = "default";
682 pinctrl-0 = <&pinctrl_i2c6_default>;
687 #address-cells = <1>;
689 #interrupt-cells = <1>;
692 compatible = "aspeed,ast2500-i2c-bus";
693 clocks = <&syscon ASPEED_CLK_APB>;
694 resets = <&syscon ASPEED_RESET_I2C>;
695 bus-frequency = <100000>;
697 interrupt-parent = <&i2c_ic>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_i2c7_default>;
704 #address-cells = <1>;
706 #interrupt-cells = <1>;
709 compatible = "aspeed,ast2500-i2c-bus";
710 clocks = <&syscon ASPEED_CLK_APB>;
711 resets = <&syscon ASPEED_RESET_I2C>;
712 bus-frequency = <100000>;
714 interrupt-parent = <&i2c_ic>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&pinctrl_i2c8_default>;
721 #address-cells = <1>;
723 #interrupt-cells = <1>;
726 compatible = "aspeed,ast2500-i2c-bus";
727 clocks = <&syscon ASPEED_CLK_APB>;
728 resets = <&syscon ASPEED_RESET_I2C>;
729 bus-frequency = <100000>;
731 interrupt-parent = <&i2c_ic>;
732 pinctrl-names = "default";
733 pinctrl-0 = <&pinctrl_i2c9_default>;
738 #address-cells = <1>;
740 #interrupt-cells = <1>;
743 compatible = "aspeed,ast2500-i2c-bus";
744 clocks = <&syscon ASPEED_CLK_APB>;
745 resets = <&syscon ASPEED_RESET_I2C>;
746 bus-frequency = <100000>;
748 interrupt-parent = <&i2c_ic>;
749 pinctrl-names = "default";
750 pinctrl-0 = <&pinctrl_i2c10_default>;
755 #address-cells = <1>;
757 #interrupt-cells = <1>;
760 compatible = "aspeed,ast2500-i2c-bus";
761 clocks = <&syscon ASPEED_CLK_APB>;
762 resets = <&syscon ASPEED_RESET_I2C>;
763 bus-frequency = <100000>;
765 interrupt-parent = <&i2c_ic>;
766 pinctrl-names = "default";
767 pinctrl-0 = <&pinctrl_i2c11_default>;
772 #address-cells = <1>;
774 #interrupt-cells = <1>;
777 compatible = "aspeed,ast2500-i2c-bus";
778 clocks = <&syscon ASPEED_CLK_APB>;
779 resets = <&syscon ASPEED_RESET_I2C>;
780 bus-frequency = <100000>;
782 interrupt-parent = <&i2c_ic>;
783 pinctrl-names = "default";
784 pinctrl-0 = <&pinctrl_i2c12_default>;
789 #address-cells = <1>;
791 #interrupt-cells = <1>;
794 compatible = "aspeed,ast2500-i2c-bus";
795 clocks = <&syscon ASPEED_CLK_APB>;
796 resets = <&syscon ASPEED_RESET_I2C>;
797 bus-frequency = <100000>;
799 interrupt-parent = <&i2c_ic>;
800 pinctrl-names = "default";
801 pinctrl-0 = <&pinctrl_i2c13_default>;
806 #address-cells = <1>;
808 #interrupt-cells = <1>;
811 compatible = "aspeed,ast2500-i2c-bus";
812 clocks = <&syscon ASPEED_CLK_APB>;
813 resets = <&syscon ASPEED_RESET_I2C>;
814 bus-frequency = <100000>;
816 interrupt-parent = <&i2c_ic>;
817 pinctrl-names = "default";
818 pinctrl-0 = <&pinctrl_i2c14_default>;
824 pinctrl_acpi_default: acpi_default {
829 pinctrl_adc0_default: adc0_default {
834 pinctrl_adc1_default: adc1_default {
839 pinctrl_adc10_default: adc10_default {
844 pinctrl_adc11_default: adc11_default {
849 pinctrl_adc12_default: adc12_default {
854 pinctrl_adc13_default: adc13_default {
859 pinctrl_adc14_default: adc14_default {
864 pinctrl_adc15_default: adc15_default {
869 pinctrl_adc2_default: adc2_default {
874 pinctrl_adc3_default: adc3_default {
879 pinctrl_adc4_default: adc4_default {
884 pinctrl_adc5_default: adc5_default {
889 pinctrl_adc6_default: adc6_default {
894 pinctrl_adc7_default: adc7_default {
899 pinctrl_adc8_default: adc8_default {
904 pinctrl_adc9_default: adc9_default {
909 pinctrl_bmcint_default: bmcint_default {
914 pinctrl_ddcclk_default: ddcclk_default {
919 pinctrl_ddcdat_default: ddcdat_default {
924 pinctrl_espi_default: espi_default {
929 pinctrl_fwspics1_default: fwspics1_default {
930 function = "FWSPICS1";
934 pinctrl_fwspics2_default: fwspics2_default {
935 function = "FWSPICS2";
939 pinctrl_gpid0_default: gpid0_default {
944 pinctrl_gpid2_default: gpid2_default {
949 pinctrl_gpid4_default: gpid4_default {
954 pinctrl_gpid6_default: gpid6_default {
959 pinctrl_gpie0_default: gpie0_default {
964 pinctrl_gpie2_default: gpie2_default {
969 pinctrl_gpie4_default: gpie4_default {
974 pinctrl_gpie6_default: gpie6_default {
979 pinctrl_i2c10_default: i2c10_default {
984 pinctrl_i2c11_default: i2c11_default {
989 pinctrl_i2c12_default: i2c12_default {
994 pinctrl_i2c13_default: i2c13_default {
999 pinctrl_i2c14_default: i2c14_default {
1004 pinctrl_i2c3_default: i2c3_default {
1009 pinctrl_i2c4_default: i2c4_default {
1014 pinctrl_i2c5_default: i2c5_default {
1019 pinctrl_i2c6_default: i2c6_default {
1024 pinctrl_i2c7_default: i2c7_default {
1029 pinctrl_i2c8_default: i2c8_default {
1034 pinctrl_i2c9_default: i2c9_default {
1039 pinctrl_lad0_default: lad0_default {
1044 pinctrl_lad1_default: lad1_default {
1049 pinctrl_lad2_default: lad2_default {
1054 pinctrl_lad3_default: lad3_default {
1059 pinctrl_lclk_default: lclk_default {
1064 pinctrl_lframe_default: lframe_default {
1065 function = "LFRAME";
1069 pinctrl_lpchc_default: lpchc_default {
1074 pinctrl_lpcpd_default: lpcpd_default {
1079 pinctrl_lpcplus_default: lpcplus_default {
1080 function = "LPCPLUS";
1084 pinctrl_lpcpme_default: lpcpme_default {
1085 function = "LPCPME";
1089 pinctrl_lpcrst_default: lpcrst_default {
1090 function = "LPCRST";
1094 pinctrl_lpcsmi_default: lpcsmi_default {
1095 function = "LPCSMI";
1099 pinctrl_lsirq_default: lsirq_default {
1104 pinctrl_mac1link_default: mac1link_default {
1105 function = "MAC1LINK";
1106 groups = "MAC1LINK";
1109 pinctrl_mac2link_default: mac2link_default {
1110 function = "MAC2LINK";
1111 groups = "MAC2LINK";
1114 pinctrl_mdio1_default: mdio1_default {
1119 pinctrl_mdio2_default: mdio2_default {
1124 pinctrl_ncts1_default: ncts1_default {
1129 pinctrl_ncts2_default: ncts2_default {
1134 pinctrl_ncts3_default: ncts3_default {
1139 pinctrl_ncts4_default: ncts4_default {
1144 pinctrl_ndcd1_default: ndcd1_default {
1149 pinctrl_ndcd2_default: ndcd2_default {
1154 pinctrl_ndcd3_default: ndcd3_default {
1159 pinctrl_ndcd4_default: ndcd4_default {
1164 pinctrl_ndsr1_default: ndsr1_default {
1169 pinctrl_ndsr2_default: ndsr2_default {
1174 pinctrl_ndsr3_default: ndsr3_default {
1179 pinctrl_ndsr4_default: ndsr4_default {
1184 pinctrl_ndtr1_default: ndtr1_default {
1189 pinctrl_ndtr2_default: ndtr2_default {
1194 pinctrl_ndtr3_default: ndtr3_default {
1199 pinctrl_ndtr4_default: ndtr4_default {
1204 pinctrl_nri1_default: nri1_default {
1209 pinctrl_nri2_default: nri2_default {
1214 pinctrl_nri3_default: nri3_default {
1219 pinctrl_nri4_default: nri4_default {
1224 pinctrl_nrts1_default: nrts1_default {
1229 pinctrl_nrts2_default: nrts2_default {
1234 pinctrl_nrts3_default: nrts3_default {
1239 pinctrl_nrts4_default: nrts4_default {
1244 pinctrl_oscclk_default: oscclk_default {
1245 function = "OSCCLK";
1249 pinctrl_pewake_default: pewake_default {
1250 function = "PEWAKE";
1254 pinctrl_pnor_default: pnor_default {
1259 pinctrl_pwm0_default: pwm0_default {
1264 pinctrl_pwm1_default: pwm1_default {
1269 pinctrl_pwm2_default: pwm2_default {
1274 pinctrl_pwm3_default: pwm3_default {
1279 pinctrl_pwm4_default: pwm4_default {
1284 pinctrl_pwm5_default: pwm5_default {
1289 pinctrl_pwm6_default: pwm6_default {
1294 pinctrl_pwm7_default: pwm7_default {
1299 pinctrl_rgmii1_default: rgmii1_default {
1300 function = "RGMII1";
1304 pinctrl_rgmii2_default: rgmii2_default {
1305 function = "RGMII2";
1309 pinctrl_rmii1_default: rmii1_default {
1314 pinctrl_rmii2_default: rmii2_default {
1319 pinctrl_rxd1_default: rxd1_default {
1324 pinctrl_rxd2_default: rxd2_default {
1329 pinctrl_rxd3_default: rxd3_default {
1334 pinctrl_rxd4_default: rxd4_default {
1339 pinctrl_salt1_default: salt1_default {
1344 pinctrl_salt10_default: salt10_default {
1345 function = "SALT10";
1349 pinctrl_salt11_default: salt11_default {
1350 function = "SALT11";
1354 pinctrl_salt12_default: salt12_default {
1355 function = "SALT12";
1359 pinctrl_salt13_default: salt13_default {
1360 function = "SALT13";
1364 pinctrl_salt14_default: salt14_default {
1365 function = "SALT14";
1369 pinctrl_salt2_default: salt2_default {
1374 pinctrl_salt3_default: salt3_default {
1379 pinctrl_salt4_default: salt4_default {
1384 pinctrl_salt5_default: salt5_default {
1389 pinctrl_salt6_default: salt6_default {
1394 pinctrl_salt7_default: salt7_default {
1399 pinctrl_salt8_default: salt8_default {
1404 pinctrl_salt9_default: salt9_default {
1409 pinctrl_scl1_default: scl1_default {
1414 pinctrl_scl2_default: scl2_default {
1419 pinctrl_sd1_default: sd1_default {
1424 pinctrl_sd2_default: sd2_default {
1429 pinctrl_sda1_default: sda1_default {
1434 pinctrl_sda2_default: sda2_default {
1439 pinctrl_sgpm_default: sgpm_default {
1444 pinctrl_sgps1_default: sgps1_default {
1449 pinctrl_sgps2_default: sgps2_default {
1454 pinctrl_sioonctrl_default: sioonctrl_default {
1455 function = "SIOONCTRL";
1456 groups = "SIOONCTRL";
1459 pinctrl_siopbi_default: siopbi_default {
1460 function = "SIOPBI";
1464 pinctrl_siopbo_default: siopbo_default {
1465 function = "SIOPBO";
1469 pinctrl_siopwreq_default: siopwreq_default {
1470 function = "SIOPWREQ";
1471 groups = "SIOPWREQ";
1474 pinctrl_siopwrgd_default: siopwrgd_default {
1475 function = "SIOPWRGD";
1476 groups = "SIOPWRGD";
1479 pinctrl_sios3_default: sios3_default {
1484 pinctrl_sios5_default: sios5_default {
1489 pinctrl_siosci_default: siosci_default {
1490 function = "SIOSCI";
1494 pinctrl_spi1_default: spi1_default {
1499 pinctrl_spi1cs1_default: spi1cs1_default {
1500 function = "SPI1CS1";
1504 pinctrl_spi1debug_default: spi1debug_default {
1505 function = "SPI1DEBUG";
1506 groups = "SPI1DEBUG";
1509 pinctrl_spi1passthru_default: spi1passthru_default {
1510 function = "SPI1PASSTHRU";
1511 groups = "SPI1PASSTHRU";
1514 pinctrl_spi2ck_default: spi2ck_default {
1515 function = "SPI2CK";
1519 pinctrl_spi2cs0_default: spi2cs0_default {
1520 function = "SPI2CS0";
1524 pinctrl_spi2cs1_default: spi2cs1_default {
1525 function = "SPI2CS1";
1529 pinctrl_spi2miso_default: spi2miso_default {
1530 function = "SPI2MISO";
1531 groups = "SPI2MISO";
1534 pinctrl_spi2mosi_default: spi2mosi_default {
1535 function = "SPI2MOSI";
1536 groups = "SPI2MOSI";
1539 pinctrl_timer3_default: timer3_default {
1540 function = "TIMER3";
1544 pinctrl_timer4_default: timer4_default {
1545 function = "TIMER4";
1549 pinctrl_timer5_default: timer5_default {
1550 function = "TIMER5";
1554 pinctrl_timer6_default: timer6_default {
1555 function = "TIMER6";
1559 pinctrl_timer7_default: timer7_default {
1560 function = "TIMER7";
1564 pinctrl_timer8_default: timer8_default {
1565 function = "TIMER8";
1569 pinctrl_txd1_default: txd1_default {
1574 pinctrl_txd2_default: txd2_default {
1579 pinctrl_txd3_default: txd3_default {
1584 pinctrl_txd4_default: txd4_default {
1589 pinctrl_uart6_default: uart6_default {
1594 pinctrl_usbcki_default: usbcki_default {
1595 function = "USBCKI";
1599 pinctrl_usb2ah_default: usb2ah_default {
1600 function = "USB2AH";
1604 pinctrl_usb2ad_default: usb2ad_default {
1605 function = "USB2AD";
1609 pinctrl_usb11bhid_default: usb11bhid_default {
1610 function = "USB11BHID";
1611 groups = "USB11BHID";
1614 pinctrl_usb2bh_default: usb2bh_default {
1615 function = "USB2BH";
1619 pinctrl_vgabiosrom_default: vgabiosrom_default {
1620 function = "VGABIOSROM";
1621 groups = "VGABIOSROM";
1624 pinctrl_vgahs_default: vgahs_default {
1629 pinctrl_vgavs_default: vgavs_default {
1634 pinctrl_vpi24_default: vpi24_default {
1639 pinctrl_vpo_default: vpo_default {
1644 pinctrl_wdtrst1_default: wdtrst1_default {
1645 function = "WDTRST1";
1649 pinctrl_wdtrst2_default: wdtrst2_default {
1650 function = "WDTRST2";