arch/arm/boot/dts/aspeed-g4.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 #include <dt-bindings/clock/aspeed-clock.h>
   3
   4 / {
   5         model = "Aspeed BMC";
   6         compatible = "aspeed,ast2400";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 i2c0 = &i2c0;
  13                 i2c1 = &i2c1;
  14                 i2c2 = &i2c2;
  15                 i2c3 = &i2c3;
  16                 i2c4 = &i2c4;
  17                 i2c5 = &i2c5;
  18                 i2c6 = &i2c6;
  19                 i2c7 = &i2c7;
  20                 i2c8 = &i2c8;
  21                 i2c9 = &i2c9;
  22                 i2c10 = &i2c10;
  23                 i2c11 = &i2c11;
  24                 i2c12 = &i2c12;
  25                 i2c13 = &i2c13;
  26                 serial0 = &uart1;
  27                 serial1 = &uart2;
  28                 serial2 = &uart3;
  29                 serial3 = &uart4;
  30                 serial4 = &uart5;
  31                 serial5 = &vuart;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         compatible = "arm,arm926ej-s";
  40                         device_type = "cpu";
  41                         reg = <0>;
  42                 };
  43         };
  44
  45         memory@40000000 {
  46                 device_type = "memory";
  47                 reg = <0x40000000 0>;
  48         };
  49
  50         ahb {
  51                 compatible = "simple-bus";
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges;
  55
  56                 fmc: spi@1e620000 {
  57                         reg = < 0x1e620000 0x94
  58                                 0x20000000 0x10000000 >;
  59                         #address-cells = <1>;
  60                         #size-cells = <0>;
  61                         compatible = "aspeed,ast2400-fmc";
  62                         clocks = <&syscon ASPEED_CLK_AHB>;
  63                         status = "disabled";
  64                         interrupts = <19>;
  65                         flash@0 {
  66                                 reg = < 0 >;
  67                                 compatible = "jedec,spi-nor";
  68                                 status = "disabled";
  69                         };
  70                 };
  71
  72                 spi: spi@1e630000 {
  73                         reg = < 0x1e630000 0x18
  74                                 0x30000000 0x10000000 >;
  75                         #address-cells = <1>;
  76                         #size-cells = <0>;
  77                         compatible = "aspeed,ast2400-spi";
  78                         clocks = <&syscon ASPEED_CLK_AHB>;
  79                         status = "disabled";
  80                         flash@0 {
  81                                 reg = < 0 >;
  82                                 compatible = "jedec,spi-nor";
  83                                 status = "disabled";
  84                         };
  85                 };
  86
  87                 vic: interrupt-controller@1e6c0080 {
  88                         compatible = "aspeed,ast2400-vic";
  89                         interrupt-controller;
  90                         #interrupt-cells = <1>;
  91                         valid-sources = <0xffffffff 0x0007ffff>;
  92                         reg = <0x1e6c0080 0x80>;
  93                 };
  94
  95                 cvic: copro-interrupt-controller@1e6c2000 {
  96                         compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
  97                         valid-sources = <0x7fffffff>;
  98                         reg = <0x1e6c2000 0x80>;
  99                 };
 100
 101                 mac0: ethernet@1e660000 {
 102                         compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
 103                         reg = <0x1e660000 0x180>;
 104                         interrupts = <2>;
 105                         clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
 106                         status = "disabled";
 107                 };
 108
 109                 mac1: ethernet@1e680000 {
 110                         compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
 111                         reg = <0x1e680000 0x180>;
 112                         interrupts = <3>;
 113                         clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
 114                         status = "disabled";
 115                 };
 116
 117                 ehci0: usb@1e6a1000 {
 118                         compatible = "aspeed,ast2400-ehci", "generic-ehci";
 119                         reg = <0x1e6a1000 0x100>;
 120                         interrupts = <5>;
 121                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 122                         pinctrl-names = "default";
 123                         pinctrl-0 = <&pinctrl_usb2h_default>;
 124                         status = "disabled";
 125                 };
 126
 127                 uhci: usb@1e6b0000 {
 128                         compatible = "aspeed,ast2400-uhci", "generic-uhci";
 129                         reg = <0x1e6b0000 0x100>;
 130                         interrupts = <14>;
 131                         #ports = <3>;
 132                         clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
 133                         status = "disabled";
 134                         /*
 135                          * No default pinmux, it will follow EHCI, use an explicit pinmux
 136                          * override if you don't enable EHCI
 137                          */
 138                 };
 139
 140                 vhub: usb-vhub@1e6a0000 {
 141                         compatible = "aspeed,ast2400-usb-vhub";
 142                         reg = <0x1e6a0000 0x300>;
 143                         interrupts = <5>;
 144                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 145                         pinctrl-names = "default";
 146                         pinctrl-0 = <&pinctrl_usb2d_default>;
 147                         status = "disabled";
 148                 };
 149
 150                 apb {
 151                         compatible = "simple-bus";
 152                         #address-cells = <1>;
 153                         #size-cells = <1>;
 154                         ranges;
 155
 156                         syscon: syscon@1e6e2000 {
 157                                 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
 158                                 reg = <0x1e6e2000 0x1a8>;
 159                                 #address-cells = <1>;
 160                                 #size-cells = <0>;
 161                                 #clock-cells = <1>;
 162                                 #reset-cells = <1>;
 163
 164                                 pinctrl: pinctrl {
 165                                         compatible = "aspeed,g4-pinctrl";
 166                                 };
 167
 168                                 p2a: p2a-control {
 169                                         compatible = "aspeed,ast2400-p2a-ctrl";
 170                                         status = "disabled";
 171                                 };
 172                         };
 173
 174                         rng: hwrng@1e6e2078 {
 175                                 compatible = "timeriomem_rng";
 176                                 reg = <0x1e6e2078 0x4>;
 177                                 period = <1>;
 178                                 quality = <100>;
 179                         };
 180
 181                         adc: adc@1e6e9000 {
 182                                 compatible = "aspeed,ast2400-adc";
 183                                 reg = <0x1e6e9000 0xb0>;
 184                                 clocks = <&syscon ASPEED_CLK_APB>;
 185                                 resets = <&syscon ASPEED_RESET_ADC>;
 186                                 #io-channel-cells = <1>;
 187                                 status = "disabled";
 188                         };
 189
 190                         sram: sram@1e720000 {
 191                                 compatible = "mmio-sram";
 192                                 reg = <0x1e720000 0x8000>;      // 32K
 193                         };
 194
 195                         sdmmc: sd-controller@1e740000 {
 196                                 compatible = "aspeed,ast2400-sd-controller";
 197                                 reg = <0x1e740000 0x100>;
 198                                 #address-cells = <1>;
 199                                 #size-cells = <1>;
 200                                 ranges = <0 0x1e740000 0x10000>;
 201                                 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
 202                                 status = "disabled";
 203
 204                                 sdhci0: sdhci@100 {
 205                                         compatible = "aspeed,ast2400-sdhci";
 206                                         reg = <0x100 0x100>;
 207                                         interrupts = <26>;
 208                                         sdhci,auto-cmd12;
 209                                         clocks = <&syscon ASPEED_CLK_SDIO>;
 210                                         status = "disabled";
 211                                 };
 212
 213                                 sdhci1: sdhci@200 {
 214                                         compatible = "aspeed,ast2400-sdhci";
 215                                         reg = <0x200 0x100>;
 216                                         interrupts = <26>;
 217                                         sdhci,auto-cmd12;
 218                                         clocks = <&syscon ASPEED_CLK_SDIO>;
 219                                         status = "disabled";
 220                                 };
 221                         };
 222
 223                         gpio: gpio@1e780000 {
 224                                 #gpio-cells = <2>;
 225                                 gpio-controller;
 226                                 compatible = "aspeed,ast2400-gpio";
 227                                 reg = <0x1e780000 0x1000>;
 228                                 interrupts = <20>;
 229                                 gpio-ranges = <&pinctrl 0 0 220>;
 230                                 clocks = <&syscon ASPEED_CLK_APB>;
 231                                 interrupt-controller;
 232                                 #interrupt-cells = <2>;
 233                         };
 234
 235                         timer: timer@1e782000 {
 236                                 /* This timer is a Faraday FTTMR010 derivative */
 237                                 compatible = "aspeed,ast2400-timer";
 238                                 reg = <0x1e782000 0x90>;
 239                                 interrupts = <16 17 18 35 36 37 38 39>;
 240                                 clocks = <&syscon ASPEED_CLK_APB>;
 241                                 clock-names = "PCLK";
 242                         };
 243
 244                         rtc: rtc@1e781000 {
 245                                 compatible = "aspeed,ast2400-rtc";
 246                                 reg = <0x1e781000 0x18>;
 247                                 status = "disabled";
 248                         };
 249
 250                         uart1: serial@1e783000 {
 251                                 compatible = "ns16550a";
 252                                 reg = <0x1e783000 0x20>;
 253                                 reg-shift = <2>;
 254                                 interrupts = <9>;
 255                                 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
 256                                 resets = <&lpc_reset 4>;
 257                                 no-loopback-test;
 258                                 status = "disabled";
 259                         };
 260
 261                         uart5: serial@1e784000 {
 262                                 compatible = "ns16550a";
 263                                 reg = <0x1e784000 0x20>;
 264                                 reg-shift = <2>;
 265                                 interrupts = <10>;
 266                                 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
 267                                 no-loopback-test;
 268                                 status = "disabled";
 269                         };
 270
 271                         wdt1: watchdog@1e785000 {
 272                                 compatible = "aspeed,ast2400-wdt";
 273                                 reg = <0x1e785000 0x1c>;
 274                                 clocks = <&syscon ASPEED_CLK_APB>;
 275                         };
 276
 277                         wdt2: watchdog@1e785020 {
 278                                 compatible = "aspeed,ast2400-wdt";
 279                                 reg = <0x1e785020 0x1c>;
 280                                 clocks = <&syscon ASPEED_CLK_APB>;
 281                         };
 282
 283                         pwm_tacho: pwm-tacho-controller@1e786000 {
 284                                 compatible = "aspeed,ast2400-pwm-tacho";
 285                                 #address-cells = <1>;
 286                                 #size-cells = <0>;
 287                                 reg = <0x1e786000 0x1000>;
 288                                 clocks = <&syscon ASPEED_CLK_24M>;
 289                                 resets = <&syscon ASPEED_RESET_PWM>;
 290                                 status = "disabled";
 291                         };
 292
 293                         vuart: serial@1e787000 {
 294                                 compatible = "aspeed,ast2400-vuart";
 295                                 reg = <0x1e787000 0x40>;
 296                                 reg-shift = <2>;
 297                                 interrupts = <8>;
 298                                 clocks = <&syscon ASPEED_CLK_APB>;
 299                                 no-loopback-test;
 300                                 status = "disabled";
 301                         };
 302
 303                         lpc: lpc@1e789000 {
 304                                 compatible = "aspeed,ast2400-lpc", "simple-mfd";
 305                                 reg = <0x1e789000 0x1000>;
 306
 307                                 #address-cells = <1>;
 308                                 #size-cells = <1>;
 309                                 ranges = <0x0 0x1e789000 0x1000>;
 310
 311                                 lpc_bmc: lpc-bmc@0 {
 312                                         compatible = "aspeed,ast2400-lpc-bmc";
 313                                         reg = <0x0 0x80>;
 314                                 };
 315
 316                                 lpc_host: lpc-host@80 {
 317                                         compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
 318                                         reg = <0x80 0x1e0>;
 319                                         reg-io-width = <4>;
 320
 321                                         #address-cells = <1>;
 322                                         #size-cells = <1>;
 323                                         ranges = <0x0 0x80 0x1e0>;
 324
 325                                         lpc_ctrl: lpc-ctrl@0 {
 326                                                 compatible = "aspeed,ast2400-lpc-ctrl";
 327                                                 reg = <0x0 0x80>;
 328                                                 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
 329                                                 status = "disabled";
 330                                         };
 331
 332                                         lpc_snoop: lpc-snoop@0 {
 333                                                 compatible = "aspeed,ast2400-lpc-snoop";
 334                                                 reg = <0x0 0x80>;
 335                                                 interrupts = <8>;
 336                                                 status = "disabled";
 337                                         };
 338
 339                                         lhc: lhc@20 {
 340                                                 compatible = "aspeed,ast2400-lhc";
 341                                                 reg = <0x20 0x24 0x48 0x8>;
 342                                         };
 343
 344                                         lpc_reset: reset-controller@18 {
 345                                                 compatible = "aspeed,ast2400-lpc-reset";
 346                                                 reg = <0x18 0x4>;
 347                                                 #reset-cells = <1>;
 348                                         };
 349
 350                                         ibt: ibt@c0  {
 351                                                 compatible = "aspeed,ast2400-ibt-bmc";
 352                                                 reg = <0xc0 0x18>;
 353                                                 interrupts = <8>;
 354                                                 status = "disabled";
 355                                         };
 356                                 };
 357                         };
 358
 359                         uart2: serial@1e78d000 {
 360                                 compatible = "ns16550a";
 361                                 reg = <0x1e78d000 0x20>;
 362                                 reg-shift = <2>;
 363                                 interrupts = <32>;
 364                                 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
 365                                 resets = <&lpc_reset 5>;
 366                                 no-loopback-test;
 367                                 status = "disabled";
 368                         };
 369
 370                         uart3: serial@1e78e000 {
 371                                 compatible = "ns16550a";
 372                                 reg = <0x1e78e000 0x20>;
 373                                 reg-shift = <2>;
 374                                 interrupts = <33>;
 375                                 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
 376                                 resets = <&lpc_reset 6>;
 377                                 no-loopback-test;
 378                                 status = "disabled";
 379                         };
 380
 381                         uart4: serial@1e78f000 {
 382                                 compatible = "ns16550a";
 383                                 reg = <0x1e78f000 0x20>;
 384                                 reg-shift = <2>;
 385                                 interrupts = <34>;
 386                                 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
 387                                 resets = <&lpc_reset 7>;
 388                                 no-loopback-test;
 389                                 status = "disabled";
 390                         };
 391
 392                         i2c: bus@1e78a000 {
 393                                 compatible = "simple-bus";
 394                                 #address-cells = <1>;
 395                                 #size-cells = <1>;
 396                                 ranges = <0 0x1e78a000 0x1000>;
 397                         };
 398                 };
 399         };
 400 };
 401
 402 &i2c {
 403         i2c_ic: interrupt-controller@0 {
 404                 #interrupt-cells = <1>;
 405                 compatible = "aspeed,ast2400-i2c-ic";
 406                 reg = <0x0 0x40>;
 407                 interrupts = <12>;
 408                 interrupt-controller;
 409         };
 410
 411         i2c0: i2c-bus@40 {
 412                 #address-cells = <1>;
 413                 #size-cells = <0>;
 414                 #interrupt-cells = <1>;
 415
 416                 reg = <0x40 0x40>;
 417                 compatible = "aspeed,ast2400-i2c-bus";
 418                 clocks = <&syscon ASPEED_CLK_APB>;
 419                 resets = <&syscon ASPEED_RESET_I2C>;
 420                 bus-frequency = <100000>;
 421                 interrupts = <0>;
 422                 interrupt-parent = <&i2c_ic>;
 423                 status = "disabled";
 424                 /* Does not need pinctrl properties */
 425         };
 426
 427         i2c1: i2c-bus@80 {
 428                 #address-cells = <1>;
 429                 #size-cells = <0>;
 430                 #interrupt-cells = <1>;
 431
 432                 reg = <0x80 0x40>;
 433                 compatible = "aspeed,ast2400-i2c-bus";
 434                 clocks = <&syscon ASPEED_CLK_APB>;
 435                 resets = <&syscon ASPEED_RESET_I2C>;
 436                 bus-frequency = <100000>;
 437                 interrupts = <1>;
 438                 interrupt-parent = <&i2c_ic>;
 439                 status = "disabled";
 440                 /* Does not need pinctrl properties */
 441         };
 442
 443         i2c2: i2c-bus@c0 {
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 #interrupt-cells = <1>;
 447
 448                 reg = <0xc0 0x40>;
 449                 compatible = "aspeed,ast2400-i2c-bus";
 450                 clocks = <&syscon ASPEED_CLK_APB>;
 451                 resets = <&syscon ASPEED_RESET_I2C>;
 452                 bus-frequency = <100000>;
 453                 interrupts = <2>;
 454                 interrupt-parent = <&i2c_ic>;
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&pinctrl_i2c3_default>;
 457                 status = "disabled";
 458         };
 459
 460         i2c3: i2c-bus@100 {
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 #interrupt-cells = <1>;
 464
 465                 reg = <0x100 0x40>;
 466                 compatible = "aspeed,ast2400-i2c-bus";
 467                 clocks = <&syscon ASPEED_CLK_APB>;
 468                 resets = <&syscon ASPEED_RESET_I2C>;
 469                 bus-frequency = <100000>;
 470                 interrupts = <3>;
 471                 interrupt-parent = <&i2c_ic>;
 472                 pinctrl-names = "default";
 473                 pinctrl-0 = <&pinctrl_i2c4_default>;
 474                 status = "disabled";
 475         };
 476
 477         i2c4: i2c-bus@140 {
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 #interrupt-cells = <1>;
 481
 482                 reg = <0x140 0x40>;
 483                 compatible = "aspeed,ast2400-i2c-bus";
 484                 clocks = <&syscon ASPEED_CLK_APB>;
 485                 resets = <&syscon ASPEED_RESET_I2C>;
 486                 bus-frequency = <100000>;
 487                 interrupts = <4>;
 488                 interrupt-parent = <&i2c_ic>;
 489                 pinctrl-names = "default";
 490                 pinctrl-0 = <&pinctrl_i2c5_default>;
 491                 status = "disabled";
 492         };
 493
 494         i2c5: i2c-bus@180 {
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 #interrupt-cells = <1>;
 498
 499                 reg = <0x180 0x40>;
 500                 compatible = "aspeed,ast2400-i2c-bus";
 501                 clocks = <&syscon ASPEED_CLK_APB>;
 502                 resets = <&syscon ASPEED_RESET_I2C>;
 503                 bus-frequency = <100000>;
 504                 interrupts = <5>;
 505                 interrupt-parent = <&i2c_ic>;
 506                 pinctrl-names = "default";
 507                 pinctrl-0 = <&pinctrl_i2c6_default>;
 508                 status = "disabled";
 509         };
 510
 511         i2c6: i2c-bus@1c0 {
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514                 #interrupt-cells = <1>;
 515
 516                 reg = <0x1c0 0x40>;
 517                 compatible = "aspeed,ast2400-i2c-bus";
 518                 clocks = <&syscon ASPEED_CLK_APB>;
 519                 resets = <&syscon ASPEED_RESET_I2C>;
 520                 bus-frequency = <100000>;
 521                 interrupts = <6>;
 522                 interrupt-parent = <&i2c_ic>;
 523                 pinctrl-names = "default";
 524                 pinctrl-0 = <&pinctrl_i2c7_default>;
 525                 status = "disabled";
 526         };
 527
 528         i2c7: i2c-bus@300 {
 529                 #address-cells = <1>;
 530                 #size-cells = <0>;
 531                 #interrupt-cells = <1>;
 532
 533                 reg = <0x300 0x40>;
 534                 compatible = "aspeed,ast2400-i2c-bus";
 535                 clocks = <&syscon ASPEED_CLK_APB>;
 536                 resets = <&syscon ASPEED_RESET_I2C>;
 537                 bus-frequency = <100000>;
 538                 interrupts = <7>;
 539                 interrupt-parent = <&i2c_ic>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&pinctrl_i2c8_default>;
 542                 status = "disabled";
 543         };
 544
 545         i2c8: i2c-bus@340 {
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 #interrupt-cells = <1>;
 549
 550                 reg = <0x340 0x40>;
 551                 compatible = "aspeed,ast2400-i2c-bus";
 552                 clocks = <&syscon ASPEED_CLK_APB>;
 553                 resets = <&syscon ASPEED_RESET_I2C>;
 554                 bus-frequency = <100000>;
 555                 interrupts = <8>;
 556                 interrupt-parent = <&i2c_ic>;
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&pinctrl_i2c9_default>;
 559                 status = "disabled";
 560         };
 561
 562         i2c9: i2c-bus@380 {
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 #interrupt-cells = <1>;
 566
 567                 reg = <0x380 0x40>;
 568                 compatible = "aspeed,ast2400-i2c-bus";
 569                 clocks = <&syscon ASPEED_CLK_APB>;
 570                 resets = <&syscon ASPEED_RESET_I2C>;
 571                 bus-frequency = <100000>;
 572                 interrupts = <9>;
 573                 interrupt-parent = <&i2c_ic>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&pinctrl_i2c10_default>;
 576                 status = "disabled";
 577         };
 578
 579         i2c10: i2c-bus@3c0 {
 580                 #address-cells = <1>;
 581                 #size-cells = <0>;
 582                 #interrupt-cells = <1>;
 583
 584                 reg = <0x3c0 0x40>;
 585                 compatible = "aspeed,ast2400-i2c-bus";
 586                 clocks = <&syscon ASPEED_CLK_APB>;
 587                 resets = <&syscon ASPEED_RESET_I2C>;
 588                 bus-frequency = <100000>;
 589                 interrupts = <10>;
 590                 interrupt-parent = <&i2c_ic>;
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&pinctrl_i2c11_default>;
 593                 status = "disabled";
 594         };
 595
 596         i2c11: i2c-bus@400 {
 597                 #address-cells = <1>;
 598                 #size-cells = <0>;
 599                 #interrupt-cells = <1>;
 600
 601                 reg = <0x400 0x40>;
 602                 compatible = "aspeed,ast2400-i2c-bus";
 603                 clocks = <&syscon ASPEED_CLK_APB>;
 604                 resets = <&syscon ASPEED_RESET_I2C>;
 605                 bus-frequency = <100000>;
 606                 interrupts = <11>;
 607                 interrupt-parent = <&i2c_ic>;
 608                 pinctrl-names = "default";
 609                 pinctrl-0 = <&pinctrl_i2c12_default>;
 610                 status = "disabled";
 611         };
 612
 613         i2c12: i2c-bus@440 {
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616                 #interrupt-cells = <1>;
 617
 618                 reg = <0x440 0x40>;
 619                 compatible = "aspeed,ast2400-i2c-bus";
 620                 clocks = <&syscon ASPEED_CLK_APB>;
 621                 resets = <&syscon ASPEED_RESET_I2C>;
 622                 bus-frequency = <100000>;
 623                 interrupts = <12>;
 624                 interrupt-parent = <&i2c_ic>;
 625                 pinctrl-names = "default";
 626                 pinctrl-0 = <&pinctrl_i2c13_default>;
 627                 status = "disabled";
 628         };
 629
 630         i2c13: i2c-bus@480 {
 631                 #address-cells = <1>;
 632                 #size-cells = <0>;
 633                 #interrupt-cells = <1>;
 634
 635                 reg = <0x480 0x40>;
 636                 compatible = "aspeed,ast2400-i2c-bus";
 637                 clocks = <&syscon ASPEED_CLK_APB>;
 638                 resets = <&syscon ASPEED_RESET_I2C>;
 639                 bus-frequency = <100000>;
 640                 interrupts = <13>;
 641                 interrupt-parent = <&i2c_ic>;
 642                 pinctrl-names = "default";
 643                 pinctrl-0 = <&pinctrl_i2c14_default>;
 644                 status = "disabled";
 645         };
 646 };
 647
 648 &pinctrl {
 649         pinctrl_acpi_default: acpi_default {
 650                 function = "ACPI";
 651                 groups = "ACPI";
 652         };
 653
 654         pinctrl_adc0_default: adc0_default {
 655                 function = "ADC0";
 656                 groups = "ADC0";
 657         };
 658
 659         pinctrl_adc1_default: adc1_default {
 660                 function = "ADC1";
 661                 groups = "ADC1";
 662         };
 663
 664         pinctrl_adc10_default: adc10_default {
 665                 function = "ADC10";
 666                 groups = "ADC10";
 667         };
 668
 669         pinctrl_adc11_default: adc11_default {
 670                 function = "ADC11";
 671                 groups = "ADC11";
 672         };
 673
 674         pinctrl_adc12_default: adc12_default {
 675                 function = "ADC12";
 676                 groups = "ADC12";
 677         };
 678
 679         pinctrl_adc13_default: adc13_default {
 680                 function = "ADC13";
 681                 groups = "ADC13";
 682         };
 683
 684         pinctrl_adc14_default: adc14_default {
 685                 function = "ADC14";
 686                 groups = "ADC14";
 687         };
 688
 689         pinctrl_adc15_default: adc15_default {
 690                 function = "ADC15";
 691                 groups = "ADC15";
 692         };
 693
 694         pinctrl_adc2_default: adc2_default {
 695                 function = "ADC2";
 696                 groups = "ADC2";
 697         };
 698
 699         pinctrl_adc3_default: adc3_default {
 700                 function = "ADC3";
 701                 groups = "ADC3";
 702         };
 703
 704         pinctrl_adc4_default: adc4_default {
 705                 function = "ADC4";
 706                 groups = "ADC4";
 707         };
 708
 709         pinctrl_adc5_default: adc5_default {
 710                 function = "ADC5";
 711                 groups = "ADC5";
 712         };
 713
 714         pinctrl_adc6_default: adc6_default {
 715                 function = "ADC6";
 716                 groups = "ADC6";
 717         };
 718
 719         pinctrl_adc7_default: adc7_default {
 720                 function = "ADC7";
 721                 groups = "ADC7";
 722         };
 723
 724         pinctrl_adc8_default: adc8_default {
 725                 function = "ADC8";
 726                 groups = "ADC8";
 727         };
 728
 729         pinctrl_adc9_default: adc9_default {
 730                 function = "ADC9";
 731                 groups = "ADC9";
 732         };
 733
 734         pinctrl_bmcint_default: bmcint_default {
 735                 function = "BMCINT";
 736                 groups = "BMCINT";
 737         };
 738
 739         pinctrl_ddcclk_default: ddcclk_default {
 740                 function = "DDCCLK";
 741                 groups = "DDCCLK";
 742         };
 743
 744         pinctrl_ddcdat_default: ddcdat_default {
 745                 function = "DDCDAT";
 746                 groups = "DDCDAT";
 747         };
 748
 749         pinctrl_extrst_default: extrst_default {
 750                 function = "EXTRST";
 751                 groups = "EXTRST";
 752         };
 753
 754         pinctrl_flack_default: flack_default {
 755                 function = "FLACK";
 756                 groups = "FLACK";
 757         };
 758
 759         pinctrl_flbusy_default: flbusy_default {
 760                 function = "FLBUSY";
 761                 groups = "FLBUSY";
 762         };
 763
 764         pinctrl_flwp_default: flwp_default {
 765                 function = "FLWP";
 766                 groups = "FLWP";
 767         };
 768
 769         pinctrl_gpid_default: gpid_default {
 770                 function = "GPID";
 771                 groups = "GPID";
 772         };
 773
 774         pinctrl_gpid0_default: gpid0_default {
 775                 function = "GPID0";
 776                 groups = "GPID0";
 777         };
 778
 779         pinctrl_gpid2_default: gpid2_default {
 780                 function = "GPID2";
 781                 groups = "GPID2";
 782         };
 783
 784         pinctrl_gpid4_default: gpid4_default {
 785                 function = "GPID4";
 786                 groups = "GPID4";
 787         };
 788
 789         pinctrl_gpid6_default: gpid6_default {
 790                 function = "GPID6";
 791                 groups = "GPID6";
 792         };
 793
 794         pinctrl_gpie0_default: gpie0_default {
 795                 function = "GPIE0";
 796                 groups = "GPIE0";
 797         };
 798
 799         pinctrl_gpie2_default: gpie2_default {
 800                 function = "GPIE2";
 801                 groups = "GPIE2";
 802         };
 803
 804         pinctrl_gpie4_default: gpie4_default {
 805                 function = "GPIE4";
 806                 groups = "GPIE4";
 807         };
 808
 809         pinctrl_gpie6_default: gpie6_default {
 810                 function = "GPIE6";
 811                 groups = "GPIE6";
 812         };
 813
 814         pinctrl_i2c10_default: i2c10_default {
 815                 function = "I2C10";
 816                 groups = "I2C10";
 817         };
 818
 819         pinctrl_i2c11_default: i2c11_default {
 820                 function = "I2C11";
 821                 groups = "I2C11";
 822         };
 823
 824         pinctrl_i2c12_default: i2c12_default {
 825                 function = "I2C12";
 826                 groups = "I2C12";
 827         };
 828
 829         pinctrl_i2c13_default: i2c13_default {
 830                 function = "I2C13";
 831                 groups = "I2C13";
 832         };
 833
 834         pinctrl_i2c14_default: i2c14_default {
 835                 function = "I2C14";
 836                 groups = "I2C14";
 837         };
 838
 839         pinctrl_i2c3_default: i2c3_default {
 840                 function = "I2C3";
 841                 groups = "I2C3";
 842         };
 843
 844         pinctrl_i2c4_default: i2c4_default {
 845                 function = "I2C4";
 846                 groups = "I2C4";
 847         };
 848
 849         pinctrl_i2c5_default: i2c5_default {
 850                 function = "I2C5";
 851                 groups = "I2C5";
 852         };
 853
 854         pinctrl_i2c6_default: i2c6_default {
 855                 function = "I2C6";
 856                 groups = "I2C6";
 857         };
 858
 859         pinctrl_i2c7_default: i2c7_default {
 860                 function = "I2C7";
 861                 groups = "I2C7";
 862         };
 863
 864         pinctrl_i2c8_default: i2c8_default {
 865                 function = "I2C8";
 866                 groups = "I2C8";
 867         };
 868
 869         pinctrl_i2c9_default: i2c9_default {
 870                 function = "I2C9";
 871                 groups = "I2C9";
 872         };
 873
 874         pinctrl_lpcpd_default: lpcpd_default {
 875                 function = "LPCPD";
 876                 groups = "LPCPD";
 877         };
 878
 879         pinctrl_lpcpme_default: lpcpme_default {
 880                 function = "LPCPME";
 881                 groups = "LPCPME";
 882         };
 883
 884         pinctrl_lpcrst_default: lpcrst_default {
 885                 function = "LPCRST";
 886                 groups = "LPCRST";
 887         };
 888
 889         pinctrl_lpcsmi_default: lpcsmi_default {
 890                 function = "LPCSMI";
 891                 groups = "LPCSMI";
 892         };
 893
 894         pinctrl_mac1link_default: mac1link_default {
 895                 function = "MAC1LINK";
 896                 groups = "MAC1LINK";
 897         };
 898
 899         pinctrl_mac2link_default: mac2link_default {
 900                 function = "MAC2LINK";
 901                 groups = "MAC2LINK";
 902         };
 903
 904         pinctrl_mdio1_default: mdio1_default {
 905                 function = "MDIO1";
 906                 groups = "MDIO1";
 907         };
 908
 909         pinctrl_mdio2_default: mdio2_default {
 910                 function = "MDIO2";
 911                 groups = "MDIO2";
 912         };
 913
 914         pinctrl_ncts1_default: ncts1_default {
 915                 function = "NCTS1";
 916                 groups = "NCTS1";
 917         };
 918
 919         pinctrl_ncts2_default: ncts2_default {
 920                 function = "NCTS2";
 921                 groups = "NCTS2";
 922         };
 923
 924         pinctrl_ncts3_default: ncts3_default {
 925                 function = "NCTS3";
 926                 groups = "NCTS3";
 927         };
 928
 929         pinctrl_ncts4_default: ncts4_default {
 930                 function = "NCTS4";
 931                 groups = "NCTS4";
 932         };
 933
 934         pinctrl_ndcd1_default: ndcd1_default {
 935                 function = "NDCD1";
 936                 groups = "NDCD1";
 937         };
 938
 939         pinctrl_ndcd2_default: ndcd2_default {
 940                 function = "NDCD2";
 941                 groups = "NDCD2";
 942         };
 943
 944         pinctrl_ndcd3_default: ndcd3_default {
 945                 function = "NDCD3";
 946                 groups = "NDCD3";
 947         };
 948
 949         pinctrl_ndcd4_default: ndcd4_default {
 950                 function = "NDCD4";
 951                 groups = "NDCD4";
 952         };
 953
 954         pinctrl_ndsr1_default: ndsr1_default {
 955                 function = "NDSR1";
 956                 groups = "NDSR1";
 957         };
 958
 959         pinctrl_ndsr2_default: ndsr2_default {
 960                 function = "NDSR2";
 961                 groups = "NDSR2";
 962         };
 963
 964         pinctrl_ndsr3_default: ndsr3_default {
 965                 function = "NDSR3";
 966                 groups = "NDSR3";
 967         };
 968
 969         pinctrl_ndsr4_default: ndsr4_default {
 970                 function = "NDSR4";
 971                 groups = "NDSR4";
 972         };
 973
 974         pinctrl_ndtr1_default: ndtr1_default {
 975                 function = "NDTR1";
 976                 groups = "NDTR1";
 977         };
 978
 979         pinctrl_ndtr2_default: ndtr2_default {
 980                 function = "NDTR2";
 981                 groups = "NDTR2";
 982         };
 983
 984         pinctrl_ndtr3_default: ndtr3_default {
 985                 function = "NDTR3";
 986                 groups = "NDTR3";
 987         };
 988
 989         pinctrl_ndtr4_default: ndtr4_default {
 990                 function = "NDTR4";
 991                 groups = "NDTR4";
 992         };
 993
 994         pinctrl_ndts4_default: ndts4_default {
 995                 function = "NDTS4";
 996                 groups = "NDTS4";
 997         };
 998
 999         pinctrl_nri1_default: nri1_default {
1000                 function = "NRI1";
1001                 groups = "NRI1";
1002         };
1003
1004         pinctrl_nri2_default: nri2_default {
1005                 function = "NRI2";
1006                 groups = "NRI2";
1007         };
1008
1009         pinctrl_nri3_default: nri3_default {
1010                 function = "NRI3";
1011                 groups = "NRI3";
1012         };
1013
1014         pinctrl_nri4_default: nri4_default {
1015                 function = "NRI4";
1016                 groups = "NRI4";
1017         };
1018
1019         pinctrl_nrts1_default: nrts1_default {
1020                 function = "NRTS1";
1021                 groups = "NRTS1";
1022         };
1023
1024         pinctrl_nrts2_default: nrts2_default {
1025                 function = "NRTS2";
1026                 groups = "NRTS2";
1027         };
1028
1029         pinctrl_nrts3_default: nrts3_default {
1030                 function = "NRTS3";
1031                 groups = "NRTS3";
1032         };
1033
1034         pinctrl_oscclk_default: oscclk_default {
1035                 function = "OSCCLK";
1036                 groups = "OSCCLK";
1037         };
1038
1039         pinctrl_pwm0_default: pwm0_default {
1040                 function = "PWM0";
1041                 groups = "PWM0";
1042         };
1043
1044         pinctrl_pwm1_default: pwm1_default {
1045                 function = "PWM1";
1046                 groups = "PWM1";
1047         };
1048
1049         pinctrl_pwm2_default: pwm2_default {
1050                 function = "PWM2";
1051                 groups = "PWM2";
1052         };
1053
1054         pinctrl_pwm3_default: pwm3_default {
1055                 function = "PWM3";
1056                 groups = "PWM3";
1057         };
1058
1059         pinctrl_pwm4_default: pwm4_default {
1060                 function = "PWM4";
1061                 groups = "PWM4";
1062         };
1063
1064         pinctrl_pwm5_default: pwm5_default {
1065                 function = "PWM5";
1066                 groups = "PWM5";
1067         };
1068
1069         pinctrl_pwm6_default: pwm6_default {
1070                 function = "PWM6";
1071                 groups = "PWM6";
1072         };
1073
1074         pinctrl_pwm7_default: pwm7_default {
1075                 function = "PWM7";
1076                 groups = "PWM7";
1077         };
1078
1079         pinctrl_rgmii1_default: rgmii1_default {
1080                 function = "RGMII1";
1081                 groups = "RGMII1";
1082         };
1083
1084         pinctrl_rgmii2_default: rgmii2_default {
1085                 function = "RGMII2";
1086                 groups = "RGMII2";
1087         };
1088
1089         pinctrl_rmii1_default: rmii1_default {
1090                 function = "RMII1";
1091                 groups = "RMII1";
1092         };
1093
1094         pinctrl_rmii2_default: rmii2_default {
1095                 function = "RMII2";
1096                 groups = "RMII2";
1097         };
1098
1099         pinctrl_rom16_default: rom16_default {
1100                 function = "ROM16";
1101                 groups = "ROM16";
1102         };
1103
1104         pinctrl_rom8_default: rom8_default {
1105                 function = "ROM8";
1106                 groups = "ROM8";
1107         };
1108
1109         pinctrl_romcs1_default: romcs1_default {
1110                 function = "ROMCS1";
1111                 groups = "ROMCS1";
1112         };
1113
1114         pinctrl_romcs2_default: romcs2_default {
1115                 function = "ROMCS2";
1116                 groups = "ROMCS2";
1117         };
1118
1119         pinctrl_romcs3_default: romcs3_default {
1120                 function = "ROMCS3";
1121                 groups = "ROMCS3";
1122         };
1123
1124         pinctrl_romcs4_default: romcs4_default {
1125                 function = "ROMCS4";
1126                 groups = "ROMCS4";
1127         };
1128
1129         pinctrl_rxd1_default: rxd1_default {
1130                 function = "RXD1";
1131                 groups = "RXD1";
1132         };
1133
1134         pinctrl_rxd2_default: rxd2_default {
1135                 function = "RXD2";
1136                 groups = "RXD2";
1137         };
1138
1139         pinctrl_rxd3_default: rxd3_default {
1140                 function = "RXD3";
1141                 groups = "RXD3";
1142         };
1143
1144         pinctrl_rxd4_default: rxd4_default {
1145                 function = "RXD4";
1146                 groups = "RXD4";
1147         };
1148
1149         pinctrl_salt1_default: salt1_default {
1150                 function = "SALT1";
1151                 groups = "SALT1";
1152         };
1153
1154         pinctrl_salt2_default: salt2_default {
1155                 function = "SALT2";
1156                 groups = "SALT2";
1157         };
1158
1159         pinctrl_salt3_default: salt3_default {
1160                 function = "SALT3";
1161                 groups = "SALT3";
1162         };
1163
1164         pinctrl_salt4_default: salt4_default {
1165                 function = "SALT4";
1166                 groups = "SALT4";
1167         };
1168
1169         pinctrl_sd1_default: sd1_default {
1170                 function = "SD1";
1171                 groups = "SD1";
1172         };
1173
1174         pinctrl_sd2_default: sd2_default {
1175                 function = "SD2";
1176                 groups = "SD2";
1177         };
1178
1179         pinctrl_sgpmck_default: sgpmck_default {
1180                 function = "SGPMCK";
1181                 groups = "SGPMCK";
1182         };
1183
1184         pinctrl_sgpmi_default: sgpmi_default {
1185                 function = "SGPMI";
1186                 groups = "SGPMI";
1187         };
1188
1189         pinctrl_sgpmld_default: sgpmld_default {
1190                 function = "SGPMLD";
1191                 groups = "SGPMLD";
1192         };
1193
1194         pinctrl_sgpmo_default: sgpmo_default {
1195                 function = "SGPMO";
1196                 groups = "SGPMO";
1197         };
1198
1199         pinctrl_sgpsck_default: sgpsck_default {
1200                 function = "SGPSCK";
1201                 groups = "SGPSCK";
1202         };
1203
1204         pinctrl_sgpsi0_default: sgpsi0_default {
1205                 function = "SGPSI0";
1206                 groups = "SGPSI0";
1207         };
1208
1209         pinctrl_sgpsi1_default: sgpsi1_default {
1210                 function = "SGPSI1";
1211                 groups = "SGPSI1";
1212         };
1213
1214         pinctrl_sgpsld_default: sgpsld_default {
1215                 function = "SGPSLD";
1216                 groups = "SGPSLD";
1217         };
1218
1219         pinctrl_sioonctrl_default: sioonctrl_default {
1220                 function = "SIOONCTRL";
1221                 groups = "SIOONCTRL";
1222         };
1223
1224         pinctrl_siopbi_default: siopbi_default {
1225                 function = "SIOPBI";
1226                 groups = "SIOPBI";
1227         };
1228
1229         pinctrl_siopbo_default: siopbo_default {
1230                 function = "SIOPBO";
1231                 groups = "SIOPBO";
1232         };
1233
1234         pinctrl_siopwreq_default: siopwreq_default {
1235                 function = "SIOPWREQ";
1236                 groups = "SIOPWREQ";
1237         };
1238
1239         pinctrl_siopwrgd_default: siopwrgd_default {
1240                 function = "SIOPWRGD";
1241                 groups = "SIOPWRGD";
1242         };
1243
1244         pinctrl_sios3_default: sios3_default {
1245                 function = "SIOS3";
1246                 groups = "SIOS3";
1247         };
1248
1249         pinctrl_sios5_default: sios5_default {
1250                 function = "SIOS5";
1251                 groups = "SIOS5";
1252         };
1253
1254         pinctrl_siosci_default: siosci_default {
1255                 function = "SIOSCI";
1256                 groups = "SIOSCI";
1257         };
1258
1259         pinctrl_spi1_default: spi1_default {
1260                 function = "SPI1";
1261                 groups = "SPI1";
1262         };
1263
1264         pinctrl_spi1debug_default: spi1debug_default {
1265                 function = "SPI1DEBUG";
1266                 groups = "SPI1DEBUG";
1267         };
1268
1269         pinctrl_spi1passthru_default: spi1passthru_default {
1270                 function = "SPI1PASSTHRU";
1271                 groups = "SPI1PASSTHRU";
1272         };
1273
1274         pinctrl_spics1_default: spics1_default {
1275                 function = "SPICS1";
1276                 groups = "SPICS1";
1277         };
1278
1279         pinctrl_timer3_default: timer3_default {
1280                 function = "TIMER3";
1281                 groups = "TIMER3";
1282         };
1283
1284         pinctrl_timer4_default: timer4_default {
1285                 function = "TIMER4";
1286                 groups = "TIMER4";
1287         };
1288
1289         pinctrl_timer5_default: timer5_default {
1290                 function = "TIMER5";
1291                 groups = "TIMER5";
1292         };
1293
1294         pinctrl_timer6_default: timer6_default {
1295                 function = "TIMER6";
1296                 groups = "TIMER6";
1297         };
1298
1299         pinctrl_timer7_default: timer7_default {
1300                 function = "TIMER7";
1301                 groups = "TIMER7";
1302         };
1303
1304         pinctrl_timer8_default: timer8_default {
1305                 function = "TIMER8";
1306                 groups = "TIMER8";
1307         };
1308
1309         pinctrl_txd1_default: txd1_default {
1310                 function = "TXD1";
1311                 groups = "TXD1";
1312         };
1313
1314         pinctrl_txd2_default: txd2_default {
1315                 function = "TXD2";
1316                 groups = "TXD2";
1317         };
1318
1319         pinctrl_txd3_default: txd3_default {
1320                 function = "TXD3";
1321                 groups = "TXD3";
1322         };
1323
1324         pinctrl_txd4_default: txd4_default {
1325                 function = "TXD4";
1326                 groups = "TXD4";
1327         };
1328
1329         pinctrl_uart6_default: uart6_default {
1330                 function = "UART6";
1331                 groups = "UART6";
1332         };
1333
1334         pinctrl_usbcki_default: usbcki_default {
1335                 function = "USBCKI";
1336                 groups = "USBCKI";
1337         };
1338
1339         pinctrl_usb2h_default: usb2h_default {
1340                 function = "USB2H1";
1341                 groups = "USB2H1";
1342         };
1343
1344         pinctrl_usb2d_default: usb2d_default {
1345                 function = "USB2D1";
1346                 groups = "USB2D1";
1347         };
1348
1349         pinctrl_vgabios_rom_default: vgabios_rom_default {
1350                 function = "VGABIOS_ROM";
1351                 groups = "VGABIOS_ROM";
1352         };
1353
1354         pinctrl_vgahs_default: vgahs_default {
1355                 function = "VGAHS";
1356                 groups = "VGAHS";
1357         };
1358
1359         pinctrl_vgavs_default: vgavs_default {
1360                 function = "VGAVS";
1361                 groups = "VGAVS";
1362         };
1363
1364         pinctrl_vpi18_default: vpi18_default {
1365                 function = "VPI18";
1366                 groups = "VPI18";
1367         };
1368
1369         pinctrl_vpi24_default: vpi24_default {
1370                 function = "VPI24";
1371                 groups = "VPI24";
1372         };
1373
1374         pinctrl_vpi30_default: vpi30_default {
1375                 function = "VPI30";
1376                 groups = "VPI30";
1377         };
1378
1379         pinctrl_vpo12_default: vpo12_default {
1380                 function = "VPO12";
1381                 groups = "VPO12";
1382         };
1383
1384         pinctrl_vpo24_default: vpo24_default {
1385                 function = "VPO24";
1386                 groups = "VPO24";
1387         };
1388
1389         pinctrl_wdtrst1_default: wdtrst1_default {
1390                 function = "WDTRST1";
1391                 groups = "WDTRST1";
1392         };
1393
1394         pinctrl_wdtrst2_default: wdtrst2_default {
1395                 function = "WDTRST2";
1396                 groups = "WDTRST2";
1397         };
1398 };