2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 * Contains definitions specific to the Armada XP MV78230 SoC that are not
13 * common to all Armada XP SoCs.
16 #include "armada-xp.dtsi"
19 model = "Marvell Armada XP MV78230 SoC";
20 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
33 compatible = "marvell,sheeva-v7";
40 compatible = "marvell,sheeva-v7";
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
49 * configured as x4 or quad x1 lanes. One unit is
53 compatible = "marvell,armada-xp-pcie";
61 bus-range = <0x00 0xff>;
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
69 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
70 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
71 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
72 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
73 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
74 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
75 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
76 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
77 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
78 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
82 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
83 reg = <0x0800 0 0 0 0>;
86 #interrupt-cells = <1>;
87 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
88 0x81000000 0 0 0x81000000 0x1 0 1 0>;
89 interrupt-map-mask = <0 0 0 0>;
90 interrupt-map = <0 0 0 0 &mpic 58>;
91 marvell,pcie-port = <0>;
92 marvell,pcie-lane = <0>;
93 clocks = <&gateclk 5>;
99 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
100 reg = <0x1000 0 0 0 0>;
101 #address-cells = <3>;
103 #interrupt-cells = <1>;
104 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
105 0x81000000 0 0 0x81000000 0x2 0 1 0>;
106 interrupt-map-mask = <0 0 0 0>;
107 interrupt-map = <0 0 0 0 &mpic 59>;
108 marvell,pcie-port = <0>;
109 marvell,pcie-lane = <1>;
110 clocks = <&gateclk 6>;
116 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
117 reg = <0x1800 0 0 0 0>;
118 #address-cells = <3>;
120 #interrupt-cells = <1>;
121 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
122 0x81000000 0 0 0x81000000 0x3 0 1 0>;
123 interrupt-map-mask = <0 0 0 0>;
124 interrupt-map = <0 0 0 0 &mpic 60>;
125 marvell,pcie-port = <0>;
126 marvell,pcie-lane = <2>;
127 clocks = <&gateclk 7>;
133 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
134 reg = <0x2000 0 0 0 0>;
135 #address-cells = <3>;
137 #interrupt-cells = <1>;
138 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
139 0x81000000 0 0 0x81000000 0x4 0 1 0>;
140 interrupt-map-mask = <0 0 0 0>;
141 interrupt-map = <0 0 0 0 &mpic 61>;
142 marvell,pcie-port = <0>;
143 marvell,pcie-lane = <3>;
144 clocks = <&gateclk 8>;
150 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
151 reg = <0x2800 0 0 0 0>;
152 #address-cells = <3>;
154 #interrupt-cells = <1>;
155 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
156 0x81000000 0 0 0x81000000 0x5 0 1 0>;
157 interrupt-map-mask = <0 0 0 0>;
158 interrupt-map = <0 0 0 0 &mpic 62>;
159 marvell,pcie-port = <1>;
160 marvell,pcie-lane = <0>;
161 clocks = <&gateclk 9>;
168 compatible = "marvell,mv78230-pinctrl";
169 reg = <0x18000 0x38>;
171 sdio_pins: sdio-pins {
172 marvell,pins = "mpp30", "mpp31", "mpp32",
173 "mpp33", "mpp34", "mpp35";
174 marvell,function = "sd0";
179 compatible = "marvell,orion-gpio";
180 reg = <0x18100 0x40>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
186 interrupts = <82>, <83>, <84>, <85>;
190 compatible = "marvell,orion-gpio";
191 reg = <0x18140 0x40>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 interrupts = <87>, <88>, <89>;