arch/arm/boot/dts/armada-xp-gp.dts

   1 /*
   2  * Device Tree file for Marvell Armada XP development board
   3  * (DB-MV784MP-GP)
   4  *
   5  * Copyright (C) 2013-2014 Marvell
   6  *
   7  * Lior Amsalem <alior@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  *
  15  * Note: this Device Tree assumes that the bootloader has remapped the
  16  * internal registers to 0xf1000000 (instead of the default
  17  * 0xd0000000). The 0xf1000000 is the default used by the recent,
  18  * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
  19  * boards were delivered with an older version of the bootloader that
  20  * left internal registers mapped at 0xd0000000. If you are in this
  21  * situation, you should either update your bootloader (preferred
  22  * solution) or the below Device Tree should be adjusted.
  23  */
  24
  25 /dts-v1/;
  26 #include "armada-xp-mv78460.dtsi"
  27
  28 / {
  29         model = "Marvell Armada XP Development Board DB-MV784MP-GP";
  30         compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  31
  32         chosen {
  33                 bootargs = "console=ttyS0,115200 earlyprintk";
  34         };
  35
  36         memory {
  37                 device_type = "memory";
  38                 /*
  39                  * 8 GB of plug-in RAM modules by default.The amount
  40                  * of memory available can be changed by the
  41                  * bootloader according the size of the module
  42                  * actually plugged. However, memory between
  43                  * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
  44                  * the address range used for I/O (internal registers,
  45                  * MBus windows).
  46                  */
  47                 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
  48                       <0x00000001 0x00000000 0x00000001 0x00000000>;
  49         };
  50
  51         soc {
  52                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  53                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
  54                           MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
  55
  56                 devbus-bootcs {
  57                         status = "okay";
  58
  59                         /* Device Bus parameters are required */
  60
  61                         /* Read parameters */
  62                         devbus,bus-width    = <16>;
  63                         devbus,turn-off-ps  = <60000>;
  64                         devbus,badr-skew-ps = <0>;
  65                         devbus,acc-first-ps = <124000>;
  66                         devbus,acc-next-ps  = <248000>;
  67                         devbus,rd-setup-ps  = <0>;
  68                         devbus,rd-hold-ps   = <0>;
  69
  70                         /* Write parameters */
  71                         devbus,sync-enable = <0>;
  72                         devbus,wr-high-ps  = <60000>;
  73                         devbus,wr-low-ps   = <60000>;
  74                         devbus,ale-wr-ps   = <60000>;
  75
  76                         /* NOR 16 MiB */
  77                         nor@0 {
  78                                 compatible = "cfi-flash";
  79                                 reg = <0 0x1000000>;
  80                                 bank-width = <2>;
  81                         };
  82                 };
  83
  84                 pcie-controller {
  85                         status = "okay";
  86
  87                         /*
  88                          * The 3 slots are physically present as
  89                          * standard PCIe slots on the board.
  90                          */
  91                         pcie@1,0 {
  92                                 /* Port 0, Lane 0 */
  93                                 status = "okay";
  94                         };
  95                         pcie@9,0 {
  96                                 /* Port 2, Lane 0 */
  97                                 status = "okay";
  98                         };
  99                         pcie@10,0 {
 100                                 /* Port 3, Lane 0 */
 101                                 status = "okay";
 102                         };
 103                 };
 104
 105                 internal-regs {
 106                         serial@12000 {
 107                                 status = "okay";
 108                         };
 109                         serial@12100 {
 110                                 status = "okay";
 111                         };
 112                         serial@12200 {
 113                                 status = "okay";
 114                         };
 115                         serial@12300 {
 116                                 status = "okay";
 117                         };
 118
 119                         sata@a0000 {
 120                                 nr-ports = <2>;
 121                                 status = "okay";
 122                         };
 123
 124                         mdio {
 125                                 phy0: ethernet-phy@0 {
 126                                         reg = <16>;
 127                                 };
 128
 129                                 phy1: ethernet-phy@1 {
 130                                         reg = <17>;
 131                                 };
 132
 133                                 phy2: ethernet-phy@2 {
 134                                         reg = <18>;
 135                                 };
 136
 137                                 phy3: ethernet-phy@3 {
 138                                         reg = <19>;
 139                                 };
 140                         };
 141
 142                         ethernet@70000 {
 143                                 status = "okay";
 144                                 phy = <&phy0>;
 145                                 phy-mode = "qsgmii";
 146                         };
 147                         ethernet@74000 {
 148                                 status = "okay";
 149                                 phy = <&phy1>;
 150                                 phy-mode = "qsgmii";
 151                         };
 152                         ethernet@30000 {
 153                                 status = "okay";
 154                                 phy = <&phy2>;
 155                                 phy-mode = "qsgmii";
 156                         };
 157                         ethernet@34000 {
 158                                 status = "okay";
 159                                 phy = <&phy3>;
 160                                 phy-mode = "qsgmii";
 161                         };
 162
 163                         /* Front-side USB slot */
 164                         usb@50000 {
 165                                 status = "okay";
 166                         };
 167
 168                         /* Back-side USB slot */
 169                         usb@51000 {
 170                                 status = "okay";
 171                         };
 172
 173                         spi0: spi@10600 {
 174                                 status = "okay";
 175
 176                                 spi-flash@0 {
 177                                         #address-cells = <1>;
 178                                         #size-cells = <1>;
 179                                         compatible = "n25q128a13";
 180                                         reg = <0>; /* Chip select 0 */
 181                                         spi-max-frequency = <108000000>;
 182                                 };
 183                         };
 184
 185                         nand@d0000 {
 186                                 status = "okay";
 187                                 num-cs = <1>;
 188                                 marvell,nand-keep-config;
 189                                 marvell,nand-enable-arbiter;
 190                                 nand-on-flash-bbt;
 191                         };
 192                 };
 193         };
 194 };