1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree include file for SolidRun Clearfog 88F6828 based boards
5 * Copyright (C) 2015 Russell King
7 * This board is in development; the contents of this file work with
8 * the A1 rev 2.0 of the board, which does not represent final
9 * production board. Things will change, don't expect this file to
10 * remain compatible info the future.
13 #include "armada-388.dtsi"
14 #include "armada-38x-solidrun-microsom.dtsi"
18 /* So that mvebu u-boot can update the MAC addresses */
25 stdout-path = "serial0:115200n8";
28 reg_3p3v: regulator-3p3v {
29 compatible = "regulator-fixed";
30 regulator-name = "3P3V";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
50 cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
52 pinctrl-0 = <µsom_sdhci_pins
53 &clearfog_sdhci_cd_pins>;
54 pinctrl-names = "default";
61 /* CON3, nearest power. */
74 * The two PCIe units are accessible through
75 * the mini-PCIe connectors on the board.
78 /* Port 1, Lane 0. CON3, nearest power. */
79 reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
86 compatible = "sff,sfp";
88 los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
89 mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
90 tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
91 tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
92 maximum-power-milliwatt = <2000>;
100 buffer-manager = <&bm>;
109 buffer-manager = <&bm>;
110 managed = "in-band-status";
117 clock-frequency = <400000>;
118 pinctrl-0 = <&i2c0_pins>;
119 pinctrl-names = "default";
123 * PCA9655 GPIO expander, up to 1MHz clock.
141 expander0: gpio-expander@20 {
143 * This is how it should be:
144 * compatible = "onnn,pca9655", "nxp,pca9555";
145 * but you can't do this because of the way I2C works.
147 compatible = "nxp,pca9555";
154 gpios = <0 GPIO_ACTIVE_LOW>;
156 line-name = "pcie1.0-clkreq";
160 gpios = <3 GPIO_ACTIVE_LOW>;
162 line-name = "pcie1.0-w-disable";
166 gpios = <5 GPIO_ACTIVE_LOW>;
168 line-name = "usb3-current-limit";
172 gpios = <6 GPIO_ACTIVE_HIGH>;
174 line-name = "usb3-power";
178 gpios = <11 GPIO_ACTIVE_HIGH>;
180 line-name = "m.2 devslp";
184 /* The MCP3021 supports standard and fast modes */
185 mikrobus_adc: mcp3021@4c {
186 compatible = "microchip,mcp3021";
193 * Routed to SFP, mikrobus, and PCIe.
194 * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
195 * address pins tied low, which takes addresses 0x50 and 0x51.
196 * Mikrobus doesn't specify beyond an I2C bus being present.
197 * PCIe uses ARP to assign addresses, or 0x63-0x64.
199 clock-frequency = <100000>;
200 pinctrl-0 = <&clearfog_i2c1_pins>;
201 pinctrl-names = "default";
206 clearfog_i2c1_pins: i2c1-pins {
207 /* SFP, PCIe, mSATA, mikrobus */
208 marvell,pins = "mpp26", "mpp27";
209 marvell,function = "i2c1";
211 clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
212 marvell,pins = "mpp20";
213 marvell,function = "gpio";
215 mikro_pins: mikro-pins {
216 /* int: mpp22 rst: mpp29 */
217 marvell,pins = "mpp22", "mpp29";
218 marvell,function = "gpio";
220 mikro_spi_pins: mikro-spi-pins {
221 marvell,pins = "mpp43";
222 marvell,function = "spi1";
224 mikro_uart_pins: mikro-uart-pins {
225 marvell,pins = "mpp24", "mpp25";
226 marvell,function = "ua1";
232 * Add SPI CS pins for clearfog:
233 * CS0: W25Q32 (not populated on uSOM)
234 * CS1: PIC microcontroller (Pro models)
237 pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
238 pinctrl-names = "default";
244 pinctrl-0 = <&mikro_uart_pins>;
245 pinctrl-names = "default";