1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Marvell Armada 375 evaluation board
6 * Copyright (C) 2014 Marvell
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include <dt-bindings/gpio/gpio.h>
14 #include "armada-375.dtsi"
17 model = "Marvell Armada 375 Development Board";
18 compatible = "marvell,a375-db", "marvell,armada375";
21 stdout-path = "serial0:115200n8";
25 device_type = "memory";
26 reg = <0x00000000 0x40000000>; /* 1 GB */
30 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
31 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
32 MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
33 MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
42 * The two PCIe units are accessible through
43 * standard PCIe slots on the board.
57 pinctrl-0 = <&spi0_pins>;
58 pinctrl-names = "default";
61 * SPI conflicts with NAND, so we disable it here, and
62 * select NAND as the enabled device by default.
70 compatible = "n25q128a13", "jedec,spi-nor";
71 reg = <0>; /* Chip select 0 */
72 spi-max-frequency = <108000000>;
78 clock-frequency = <100000>;
79 pinctrl-0 = <&i2c0_pins>;
80 pinctrl-names = "default";
85 clock-frequency = <100000>;
86 pinctrl-0 = <&i2c1_pins>;
87 pinctrl-names = "default";
95 sdio_st_pins: sdio-st-pins {
96 marvell,pins = "mpp44", "mpp45";
97 marvell,function = "gpio";
107 pinctrl-0 = <&nand_pins>;
108 pinctrl-names = "default";
111 marvell,nand-keep-config;
112 marvell,nand-enable-arbiter;
114 nand-ecc-strength = <4>;
115 nand-ecc-step-size = <512>;
123 reg = <0x800000 0x800000>;
126 label = "Filesystem";
127 reg = <0x1000000 0x3f000000>;
140 pinctrl-0 = <&sdio_pins &sdio_st_pins>;
141 pinctrl-names = "default";
143 cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
144 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
148 phy0: ethernet-phy@0 {
152 phy3: ethernet-phy@3 {
165 phy-mode = "rgmii-id";