4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
18 select GENERIC_ALLOCATOR
19 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
20 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
21 select GENERIC_IDLE_POLL_SETUP
22 select GENERIC_IRQ_PROBE
23 select GENERIC_IRQ_SHOW
24 select GENERIC_IRQ_SHOW_LEVEL
25 select GENERIC_PCI_IOMAP
26 select GENERIC_SCHED_CLOCK
27 select GENERIC_SMP_IDLE_THREAD
28 select GENERIC_STRNCPY_FROM_USER
29 select GENERIC_STRNLEN_USER
30 select HANDLE_DOMAIN_IRQ
31 select HARDIRQS_SW_RESEND
32 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
33 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
34 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
36 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_TRACEHOOK
39 select HAVE_CC_STACKPROTECTOR
40 select HAVE_CONTEXT_TRACKING
41 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK
43 select HAVE_DMA_API_DEBUG
45 select HAVE_DMA_CONTIGUOUS if MMU
46 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
47 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
48 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
49 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
50 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
51 select HAVE_GENERIC_DMA_COHERENT
52 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
53 select HAVE_IDE if PCI || ISA || PCMCIA
54 select HAVE_IRQ_TIME_ACCOUNTING
55 select HAVE_KERNEL_GZIP
56 select HAVE_KERNEL_LZ4
57 select HAVE_KERNEL_LZMA
58 select HAVE_KERNEL_LZO
60 select HAVE_KPROBES if !XIP_KERNEL
61 select HAVE_KRETPROBES if (HAVE_KPROBES)
63 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
64 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
65 select HAVE_OPTPROBES if !THUMB2_KERNEL
66 select HAVE_PERF_EVENTS
68 select HAVE_PERF_USER_STACK_DUMP
69 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
70 select HAVE_REGS_AND_STACK_ACCESS_API
71 select HAVE_SYSCALL_TRACEPOINTS
73 select HAVE_VIRT_CPU_ACCOUNTING_GEN
74 select IRQ_FORCED_THREADING
75 select MODULES_USE_ELF_REL
78 select OLD_SIGSUSPEND3
79 select PERF_USE_VMALLOC
81 select SYS_SUPPORTS_APM_EMULATION
82 # Above selects are sorted alphabetically; please add new ones
83 # according to that. Thanks.
85 The ARM series is a line of low-power-consumption RISC chip designs
86 licensed by ARM Ltd and targeted at embedded applications and
87 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
88 manufactured, but legacy ARM-based PC hardware remains popular in
89 Europe. There is an ARM Linux project with a web page at
90 <http://www.arm.linux.org.uk/>.
92 config ARM_HAS_SG_CHAIN
93 select ARCH_HAS_SG_CHAIN
96 config NEED_SG_DMA_LENGTH
99 config ARM_DMA_USE_IOMMU
101 select ARM_HAS_SG_CHAIN
102 select NEED_SG_DMA_LENGTH
106 config ARM_DMA_IOMMU_ALIGNMENT
107 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
111 DMA mapping framework by default aligns all buffers to the smallest
112 PAGE_SIZE order which is greater than or equal to the requested buffer
113 size. This works well for buffers up to a few hundreds kilobytes, but
114 for larger buffers it just a waste of address space. Drivers which has
115 relatively small addressing window (like 64Mib) might run out of
116 virtual space with just a few allocations.
118 With this parameter you can specify the maximum PAGE_SIZE order for
119 DMA IOMMU buffers. Larger buffers will be aligned only to this
120 specified order. The order is expressed as a power of two multiplied
125 config MIGHT_HAVE_PCI
128 config SYS_SUPPORTS_APM_EMULATION
133 select GENERIC_ALLOCATOR
144 The Extended Industry Standard Architecture (EISA) bus was
145 developed as an open alternative to the IBM MicroChannel bus.
147 The EISA bus provided some of the features of the IBM MicroChannel
148 bus while maintaining backward compatibility with cards made for
149 the older ISA bus. The EISA bus saw limited use between 1988 and
150 1995 when it was made obsolete by the PCI bus.
152 Say Y here if you are building a kernel for an EISA-based machine.
159 config STACKTRACE_SUPPORT
163 config HAVE_LATENCYTOP_SUPPORT
168 config LOCKDEP_SUPPORT
172 config TRACE_IRQFLAGS_SUPPORT
176 config RWSEM_XCHGADD_ALGORITHM
180 config ARCH_HAS_ILOG2_U32
183 config ARCH_HAS_ILOG2_U64
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_SUPPORTS_UPROBES
209 config ARCH_HAS_DMA_SET_COHERENT_MASK
212 config GENERIC_ISA_DMA
218 config NEED_RET_TO_USER
226 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
227 default DRAM_BASE if REMAP_VECTORS_TO_RAM
230 The base address of exception vectors. This must be two pages
233 config ARM_PATCH_PHYS_VIRT
234 bool "Patch physical to virtual translations at runtime" if EMBEDDED
236 depends on !XIP_KERNEL && MMU
237 depends on !ARCH_REALVIEW || !SPARSEMEM
239 Patch phys-to-virt and virt-to-phys translation functions at
240 boot and module load time according to the position of the
241 kernel in system memory.
243 This can only be used with non-XIP MMU kernels where the base
244 of physical memory is at a 16MB boundary.
246 Only disable this option if you know that you do not require
247 this feature (eg, building a kernel for a single machine) and
248 you need to shrink the kernel to the minimal size.
250 config NEED_MACH_IO_H
253 Select this when mach/io.h is required to provide special
254 definitions for this platform. The need for mach/io.h should
255 be avoided when possible.
257 config NEED_MACH_MEMORY_H
260 Select this when mach/memory.h is required to provide special
261 definitions for this platform. The need for mach/memory.h should
262 be avoided when possible.
265 hex "Physical address of main memory" if MMU
266 depends on !ARM_PATCH_PHYS_VIRT
267 default DRAM_BASE if !MMU
268 default 0x00000000 if ARCH_EBSA110 || \
269 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
274 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
275 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
276 default 0x20000000 if ARCH_S5PV210
277 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
278 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
279 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
280 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
281 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
283 Please provide the physical address corresponding to the
284 location of main memory in your system.
290 config PGTABLE_LEVELS
292 default 3 if ARM_LPAE
295 source "init/Kconfig"
297 source "kernel/Kconfig.freezer"
302 bool "MMU-based Paged Memory Management Support"
305 Select if you want MMU-based virtualised addressing space
306 support by paged memory management. If unsure, say 'Y'.
309 # The "ARM system type" choice list is ordered alphabetically by option
310 # text. Please add new entries in the option alphabetic order.
313 prompt "ARM system type"
314 default ARCH_VERSATILE if !MMU
315 default ARCH_MULTIPLATFORM if MMU
317 config ARCH_MULTIPLATFORM
318 bool "Allow multiple platforms to be selected"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_HAS_SG_CHAIN
322 select ARM_PATCH_PHYS_VIRT
326 select GENERIC_CLOCKEVENTS
327 select MIGHT_HAVE_PCI
328 select MULTI_IRQ_HANDLER
333 bool "ARM Ltd. RealView family"
334 select ARCH_WANT_OPTIONAL_GPIOLIB
336 select ARM_TIMER_SP804
338 select COMMON_CLK_VERSATILE
339 select GENERIC_CLOCKEVENTS
340 select GPIO_PL061 if GPIOLIB
342 select NEED_MACH_MEMORY_H
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_SCHED_CLOCK
346 This enables support for ARM Ltd RealView boards.
348 config ARCH_VERSATILE
349 bool "ARM Ltd. Versatile family"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
352 select ARM_TIMER_SP804
355 select GENERIC_CLOCKEVENTS
356 select HAVE_MACH_CLKDEV
358 select PLAT_VERSATILE
359 select PLAT_VERSATILE_CLOCK
360 select PLAT_VERSATILE_SCHED_CLOCK
361 select VERSATILE_FPGA_IRQ
363 This enables support for ARM Ltd Versatile board.
367 select ARCH_REQUIRE_GPIOLIB
375 This enables support for systems based on Atmel
376 AT91RM9200, AT91SAM9 and SAMA5 processors.
379 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
380 select ARCH_REQUIRE_GPIOLIB
385 select GENERIC_CLOCKEVENTS
389 Support for Cirrus Logic 711x/721x/731x based boards.
392 bool "Cortina Systems Gemini"
393 select ARCH_REQUIRE_GPIOLIB
396 select GENERIC_CLOCKEVENTS
398 Support for the Cortina Systems Gemini family SoCs
402 select ARCH_USES_GETTIMEOFFSET
405 select NEED_MACH_IO_H
406 select NEED_MACH_MEMORY_H
409 This is an evaluation board for the StrongARM processor available
410 from Digital. It has limited hardware on-board, including an
411 Ethernet interface, two PCMCIA sockets, two serial ports and a
415 bool "Energy Micro efm32"
417 select ARCH_REQUIRE_GPIOLIB
423 select GENERIC_CLOCKEVENTS
429 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
434 select ARCH_HAS_HOLES_MEMORYMODEL
435 select ARCH_REQUIRE_GPIOLIB
436 select ARCH_USES_GETTIMEOFFSET
442 This enables support for the Cirrus EP93xx series of CPUs.
444 config ARCH_FOOTBRIDGE
448 select GENERIC_CLOCKEVENTS
450 select NEED_MACH_IO_H if !MMU
451 select NEED_MACH_MEMORY_H
453 Support for systems based on the DC21285 companion chip
454 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
457 bool "Hilscher NetX based"
461 select GENERIC_CLOCKEVENTS
463 This enables support for systems based on the Hilscher NetX Soc
469 select NEED_MACH_MEMORY_H
470 select NEED_RET_TO_USER
476 Support for Intel's IOP13XX (XScale) family of processors.
481 select ARCH_REQUIRE_GPIOLIB
484 select NEED_RET_TO_USER
488 Support for Intel's 80219 and IOP32X (XScale) family of
494 select ARCH_REQUIRE_GPIOLIB
497 select NEED_RET_TO_USER
501 Support for Intel's IOP33X (XScale) family of processors.
506 select ARCH_HAS_DMA_SET_COHERENT_MASK
507 select ARCH_REQUIRE_GPIOLIB
508 select ARCH_SUPPORTS_BIG_ENDIAN
511 select DMABOUNCE if PCI
512 select GENERIC_CLOCKEVENTS
513 select MIGHT_HAVE_PCI
514 select NEED_MACH_IO_H
515 select USB_EHCI_BIG_ENDIAN_DESC
516 select USB_EHCI_BIG_ENDIAN_MMIO
518 Support for Intel's IXP4XX (XScale) family of processors.
522 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
525 select MIGHT_HAVE_PCI
529 select PLAT_ORION_LEGACY
531 Support for the Marvell Dove SoC 88AP510
534 bool "Marvell MV78xx0"
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
540 select PLAT_ORION_LEGACY
542 Support for the following Marvell MV78xx0 series SoCs:
548 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
553 select PLAT_ORION_LEGACY
555 Support for the following Marvell Orion 5x series SoCs:
556 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
557 Orion-2 (5281), Orion-1-90 (6183).
560 bool "Marvell PXA168/910/MMP2"
562 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_ALLOCATOR
565 select GENERIC_CLOCKEVENTS
568 select MULTI_IRQ_HANDLER
573 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
576 bool "Micrel/Kendin KS8695"
577 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
581 select NEED_MACH_MEMORY_H
583 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
584 System-on-Chip devices.
587 bool "Nuvoton W90X900 CPU"
588 select ARCH_REQUIRE_GPIOLIB
592 select GENERIC_CLOCKEVENTS
594 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
595 At present, the w90x900 has been renamed nuc900, regarding
596 the ARM series product line, you can login the following
597 link address to know more.
599 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
600 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
604 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
613 Support for the NXP LPC32XX family of processors
616 bool "PXA2xx/PXA3xx-based"
619 select ARCH_REQUIRE_GPIOLIB
620 select ARM_CPU_SUSPEND if PM
625 select GENERIC_CLOCKEVENTS
629 select MULTI_IRQ_HANDLER
633 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
635 config ARCH_SHMOBILE_LEGACY
636 bool "Renesas ARM SoCs (non-multiplatform)"
638 select ARM_PATCH_PHYS_VIRT if MMU
641 select GENERIC_CLOCKEVENTS
642 select HAVE_ARM_SCU if SMP
643 select HAVE_ARM_TWD if SMP
644 select HAVE_MACH_CLKDEV
646 select MIGHT_HAVE_CACHE_L2X0
647 select MULTI_IRQ_HANDLER
650 select PM_GENERIC_DOMAINS if PM
654 Support for Renesas ARM SoC platforms using a non-multiplatform
655 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
661 select ARCH_MAY_HAVE_PC_FDC
662 select ARCH_SPARSEMEM_ENABLE
663 select ARCH_USES_GETTIMEOFFSET
667 select HAVE_PATA_PLATFORM
669 select NEED_MACH_IO_H
670 select NEED_MACH_MEMORY_H
674 On the Acorn Risc-PC, Linux can support the internal IDE disk and
675 CD-ROM interface, serial and parallel port, and the floppy drive.
680 select ARCH_REQUIRE_GPIOLIB
681 select ARCH_SPARSEMEM_ENABLE
686 select GENERIC_CLOCKEVENTS
690 select MULTI_IRQ_HANDLER
691 select NEED_MACH_MEMORY_H
694 Support for StrongARM 11x0 based boards.
697 bool "Samsung S3C24XX SoCs"
698 select ARCH_REQUIRE_GPIOLIB
701 select CLKSRC_SAMSUNG_PWM
702 select GENERIC_CLOCKEVENTS
704 select HAVE_S3C2410_I2C if I2C
705 select HAVE_S3C2410_WATCHDOG if WATCHDOG
706 select HAVE_S3C_RTC if RTC_CLASS
707 select MULTI_IRQ_HANDLER
708 select NEED_MACH_IO_H
711 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
712 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
713 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
714 Samsung SMDK2410 development board (and derivatives).
717 bool "Samsung S3C64XX"
718 select ARCH_REQUIRE_GPIOLIB
723 select CLKSRC_SAMSUNG_PWM
724 select COMMON_CLK_SAMSUNG
726 select GENERIC_CLOCKEVENTS
728 select HAVE_S3C2410_I2C if I2C
729 select HAVE_S3C2410_WATCHDOG if WATCHDOG
733 select PM_GENERIC_DOMAINS if PM
735 select S3C_GPIO_TRACK
737 select SAMSUNG_WAKEMASK
738 select SAMSUNG_WDT_RESET
740 Samsung S3C64XX series based systems
744 select ARCH_HAS_HOLES_MEMORYMODEL
745 select ARCH_REQUIRE_GPIOLIB
747 select GENERIC_ALLOCATOR
748 select GENERIC_CLOCKEVENTS
749 select GENERIC_IRQ_CHIP
755 Support for TI's DaVinci platform.
760 select ARCH_HAS_HOLES_MEMORYMODEL
762 select ARCH_REQUIRE_GPIOLIB
765 select GENERIC_CLOCKEVENTS
766 select GENERIC_IRQ_CHIP
769 select NEED_MACH_IO_H if PCCARD
770 select NEED_MACH_MEMORY_H
772 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
776 menu "Multiple platform selection"
777 depends on ARCH_MULTIPLATFORM
779 comment "CPU Core family selection"
782 bool "ARMv4 based platforms (FA526)"
783 depends on !ARCH_MULTI_V6_V7
784 select ARCH_MULTI_V4_V5
787 config ARCH_MULTI_V4T
788 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
789 depends on !ARCH_MULTI_V6_V7
790 select ARCH_MULTI_V4_V5
791 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
792 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
793 CPU_ARM925T || CPU_ARM940T)
796 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
797 depends on !ARCH_MULTI_V6_V7
798 select ARCH_MULTI_V4_V5
799 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
800 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
801 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
803 config ARCH_MULTI_V4_V5
807 bool "ARMv6 based platforms (ARM11)"
808 select ARCH_MULTI_V6_V7
812 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
814 select ARCH_MULTI_V6_V7
818 config ARCH_MULTI_V6_V7
820 select MIGHT_HAVE_CACHE_L2X0
822 config ARCH_MULTI_CPU_AUTO
823 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
829 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
833 select HAVE_ARM_ARCH_TIMER
836 # This is sorted alphabetically by mach-* pathname. However, plat-*
837 # Kconfigs may be included either alphabetically (according to the
838 # plat- suffix) or along side the corresponding mach-* source.
840 source "arch/arm/mach-mvebu/Kconfig"
842 source "arch/arm/mach-asm9260/Kconfig"
844 source "arch/arm/mach-at91/Kconfig"
846 source "arch/arm/mach-axxia/Kconfig"
848 source "arch/arm/mach-bcm/Kconfig"
850 source "arch/arm/mach-berlin/Kconfig"
852 source "arch/arm/mach-clps711x/Kconfig"
854 source "arch/arm/mach-cns3xxx/Kconfig"
856 source "arch/arm/mach-davinci/Kconfig"
858 source "arch/arm/mach-digicolor/Kconfig"
860 source "arch/arm/mach-dove/Kconfig"
862 source "arch/arm/mach-ep93xx/Kconfig"
864 source "arch/arm/mach-footbridge/Kconfig"
866 source "arch/arm/mach-gemini/Kconfig"
868 source "arch/arm/mach-highbank/Kconfig"
870 source "arch/arm/mach-hisi/Kconfig"
872 source "arch/arm/mach-integrator/Kconfig"
874 source "arch/arm/mach-iop32x/Kconfig"
876 source "arch/arm/mach-iop33x/Kconfig"
878 source "arch/arm/mach-iop13xx/Kconfig"
880 source "arch/arm/mach-ixp4xx/Kconfig"
882 source "arch/arm/mach-keystone/Kconfig"
884 source "arch/arm/mach-ks8695/Kconfig"
886 source "arch/arm/mach-meson/Kconfig"
888 source "arch/arm/mach-moxart/Kconfig"
890 source "arch/arm/mach-mv78xx0/Kconfig"
892 source "arch/arm/mach-imx/Kconfig"
894 source "arch/arm/mach-mediatek/Kconfig"
896 source "arch/arm/mach-mxs/Kconfig"
898 source "arch/arm/mach-netx/Kconfig"
900 source "arch/arm/mach-nomadik/Kconfig"
902 source "arch/arm/mach-nspire/Kconfig"
904 source "arch/arm/plat-omap/Kconfig"
906 source "arch/arm/mach-omap1/Kconfig"
908 source "arch/arm/mach-omap2/Kconfig"
910 source "arch/arm/mach-orion5x/Kconfig"
912 source "arch/arm/mach-picoxcell/Kconfig"
914 source "arch/arm/mach-pxa/Kconfig"
915 source "arch/arm/plat-pxa/Kconfig"
917 source "arch/arm/mach-mmp/Kconfig"
919 source "arch/arm/mach-qcom/Kconfig"
921 source "arch/arm/mach-realview/Kconfig"
923 source "arch/arm/mach-rockchip/Kconfig"
925 source "arch/arm/mach-sa1100/Kconfig"
927 source "arch/arm/mach-socfpga/Kconfig"
929 source "arch/arm/mach-spear/Kconfig"
931 source "arch/arm/mach-sti/Kconfig"
933 source "arch/arm/mach-s3c24xx/Kconfig"
935 source "arch/arm/mach-s3c64xx/Kconfig"
937 source "arch/arm/mach-s5pv210/Kconfig"
939 source "arch/arm/mach-exynos/Kconfig"
940 source "arch/arm/plat-samsung/Kconfig"
942 source "arch/arm/mach-shmobile/Kconfig"
944 source "arch/arm/mach-sunxi/Kconfig"
946 source "arch/arm/mach-prima2/Kconfig"
948 source "arch/arm/mach-tegra/Kconfig"
950 source "arch/arm/mach-u300/Kconfig"
952 source "arch/arm/mach-ux500/Kconfig"
954 source "arch/arm/mach-versatile/Kconfig"
956 source "arch/arm/mach-vexpress/Kconfig"
957 source "arch/arm/plat-versatile/Kconfig"
959 source "arch/arm/mach-vt8500/Kconfig"
961 source "arch/arm/mach-w90x900/Kconfig"
963 source "arch/arm/mach-zynq/Kconfig"
965 # Definitions to make life easier
971 select GENERIC_CLOCKEVENTS
977 select GENERIC_IRQ_CHIP
980 config PLAT_ORION_LEGACY
987 config PLAT_VERSATILE
990 config ARM_TIMER_SP804
993 select CLKSRC_OF if OF
995 source "arch/arm/firmware/Kconfig"
997 source arch/arm/mm/Kconfig
1000 bool "Enable iWMMXt support"
1001 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1002 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1004 Enable support for iWMMXt context switching at run time if
1005 running on a CPU that supports it.
1007 config MULTI_IRQ_HANDLER
1010 Allow each machine to specify it's own IRQ handler at run time.
1013 source "arch/arm/Kconfig-nommu"
1016 config PJ4B_ERRATA_4742
1017 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1018 depends on CPU_PJ4B && MACH_ARMADA_370
1021 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1022 Event (WFE) IDLE states, a specific timing sensitivity exists between
1023 the retiring WFI/WFE instructions and the newly issued subsequent
1024 instructions. This sensitivity can result in a CPU hang scenario.
1026 The software must insert either a Data Synchronization Barrier (DSB)
1027 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1030 config ARM_ERRATA_326103
1031 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1034 Executing a SWP instruction to read-only memory does not set bit 11
1035 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1036 treat the access as a read, preventing a COW from occurring and
1037 causing the faulting task to livelock.
1039 config ARM_ERRATA_411920
1040 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1041 depends on CPU_V6 || CPU_V6K
1043 Invalidation of the Instruction Cache operation can
1044 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1045 It does not affect the MPCore. This option enables the ARM Ltd.
1046 recommended workaround.
1048 config ARM_ERRATA_430973
1049 bool "ARM errata: Stale prediction on replaced interworking branch"
1052 This option enables the workaround for the 430973 Cortex-A8
1053 r1p* erratum. If a code sequence containing an ARM/Thumb
1054 interworking branch is replaced with another code sequence at the
1055 same virtual address, whether due to self-modifying code or virtual
1056 to physical address re-mapping, Cortex-A8 does not recover from the
1057 stale interworking branch prediction. This results in Cortex-A8
1058 executing the new code sequence in the incorrect ARM or Thumb state.
1059 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1060 and also flushes the branch target cache at every context switch.
1061 Note that setting specific bits in the ACTLR register may not be
1062 available in non-secure mode.
1064 config ARM_ERRATA_458693
1065 bool "ARM errata: Processor deadlock when a false hazard is created"
1067 depends on !ARCH_MULTIPLATFORM
1069 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1070 erratum. For very specific sequences of memory operations, it is
1071 possible for a hazard condition intended for a cache line to instead
1072 be incorrectly associated with a different cache line. This false
1073 hazard might then cause a processor deadlock. The workaround enables
1074 the L1 caching of the NEON accesses and disables the PLD instruction
1075 in the ACTLR register. Note that setting specific bits in the ACTLR
1076 register may not be available in non-secure mode.
1078 config ARM_ERRATA_460075
1079 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1081 depends on !ARCH_MULTIPLATFORM
1083 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1084 erratum. Any asynchronous access to the L2 cache may encounter a
1085 situation in which recent store transactions to the L2 cache are lost
1086 and overwritten with stale memory contents from external memory. The
1087 workaround disables the write-allocate mode for the L2 cache via the
1088 ACTLR register. Note that setting specific bits in the ACTLR register
1089 may not be available in non-secure mode.
1091 config ARM_ERRATA_742230
1092 bool "ARM errata: DMB operation may be faulty"
1093 depends on CPU_V7 && SMP
1094 depends on !ARCH_MULTIPLATFORM
1096 This option enables the workaround for the 742230 Cortex-A9
1097 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1098 between two write operations may not ensure the correct visibility
1099 ordering of the two writes. This workaround sets a specific bit in
1100 the diagnostic register of the Cortex-A9 which causes the DMB
1101 instruction to behave as a DSB, ensuring the correct behaviour of
1104 config ARM_ERRATA_742231
1105 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1106 depends on CPU_V7 && SMP
1107 depends on !ARCH_MULTIPLATFORM
1109 This option enables the workaround for the 742231 Cortex-A9
1110 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1111 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1112 accessing some data located in the same cache line, may get corrupted
1113 data due to bad handling of the address hazard when the line gets
1114 replaced from one of the CPUs at the same time as another CPU is
1115 accessing it. This workaround sets specific bits in the diagnostic
1116 register of the Cortex-A9 which reduces the linefill issuing
1117 capabilities of the processor.
1119 config ARM_ERRATA_643719
1120 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1121 depends on CPU_V7 && SMP
1124 This option enables the workaround for the 643719 Cortex-A9 (prior to
1125 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1126 register returns zero when it should return one. The workaround
1127 corrects this value, ensuring cache maintenance operations which use
1128 it behave as intended and avoiding data corruption.
1130 config ARM_ERRATA_720789
1131 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1134 This option enables the workaround for the 720789 Cortex-A9 (prior to
1135 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1136 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1137 As a consequence of this erratum, some TLB entries which should be
1138 invalidated are not, resulting in an incoherency in the system page
1139 tables. The workaround changes the TLB flushing routines to invalidate
1140 entries regardless of the ASID.
1142 config ARM_ERRATA_743622
1143 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1145 depends on !ARCH_MULTIPLATFORM
1147 This option enables the workaround for the 743622 Cortex-A9
1148 (r2p*) erratum. Under very rare conditions, a faulty
1149 optimisation in the Cortex-A9 Store Buffer may lead to data
1150 corruption. This workaround sets a specific bit in the diagnostic
1151 register of the Cortex-A9 which disables the Store Buffer
1152 optimisation, preventing the defect from occurring. This has no
1153 visible impact on the overall performance or power consumption of the
1156 config ARM_ERRATA_751472
1157 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1159 depends on !ARCH_MULTIPLATFORM
1161 This option enables the workaround for the 751472 Cortex-A9 (prior
1162 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1163 completion of a following broadcasted operation if the second
1164 operation is received by a CPU before the ICIALLUIS has completed,
1165 potentially leading to corrupted entries in the cache or TLB.
1167 config ARM_ERRATA_754322
1168 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1171 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1172 r3p*) erratum. A speculative memory access may cause a page table walk
1173 which starts prior to an ASID switch but completes afterwards. This
1174 can populate the micro-TLB with a stale entry which may be hit with
1175 the new ASID. This workaround places two dsb instructions in the mm
1176 switching code so that no page table walks can cross the ASID switch.
1178 config ARM_ERRATA_754327
1179 bool "ARM errata: no automatic Store Buffer drain"
1180 depends on CPU_V7 && SMP
1182 This option enables the workaround for the 754327 Cortex-A9 (prior to
1183 r2p0) erratum. The Store Buffer does not have any automatic draining
1184 mechanism and therefore a livelock may occur if an external agent
1185 continuously polls a memory location waiting to observe an update.
1186 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1187 written polling loops from denying visibility of updates to memory.
1189 config ARM_ERRATA_364296
1190 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1193 This options enables the workaround for the 364296 ARM1136
1194 r0p2 erratum (possible cache data corruption with
1195 hit-under-miss enabled). It sets the undocumented bit 31 in
1196 the auxiliary control register and the FI bit in the control
1197 register, thus disabling hit-under-miss without putting the
1198 processor into full low interrupt latency mode. ARM11MPCore
1201 config ARM_ERRATA_764369
1202 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1203 depends on CPU_V7 && SMP
1205 This option enables the workaround for erratum 764369
1206 affecting Cortex-A9 MPCore with two or more processors (all
1207 current revisions). Under certain timing circumstances, a data
1208 cache line maintenance operation by MVA targeting an Inner
1209 Shareable memory region may fail to proceed up to either the
1210 Point of Coherency or to the Point of Unification of the
1211 system. This workaround adds a DSB instruction before the
1212 relevant cache maintenance functions and sets a specific bit
1213 in the diagnostic control register of the SCU.
1215 config ARM_ERRATA_775420
1216 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1219 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1220 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1221 operation aborts with MMU exception, it might cause the processor
1222 to deadlock. This workaround puts DSB before executing ISB if
1223 an abort may occur on cache maintenance.
1225 config ARM_ERRATA_798181
1226 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1227 depends on CPU_V7 && SMP
1229 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1230 adequately shooting down all use of the old entries. This
1231 option enables the Linux kernel workaround for this erratum
1232 which sends an IPI to the CPUs that are running the same ASID
1233 as the one being invalidated.
1235 config ARM_ERRATA_773022
1236 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1239 This option enables the workaround for the 773022 Cortex-A15
1240 (up to r0p4) erratum. In certain rare sequences of code, the
1241 loop buffer may deliver incorrect instructions. This
1242 workaround disables the loop buffer to avoid the erratum.
1246 source "arch/arm/common/Kconfig"
1253 Find out whether you have ISA slots on your motherboard. ISA is the
1254 name of a bus system, i.e. the way the CPU talks to the other stuff
1255 inside your box. Other bus systems are PCI, EISA, MicroChannel
1256 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1257 newer boards don't support it. If you have ISA, say Y, otherwise N.
1259 # Select ISA DMA controller support
1264 # Select ISA DMA interface
1269 bool "PCI support" if MIGHT_HAVE_PCI
1271 Find out whether you have a PCI motherboard. PCI is the name of a
1272 bus system, i.e. the way the CPU talks to the other stuff inside
1273 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1274 VESA. If you have PCI, say Y, otherwise N.
1280 config PCI_DOMAINS_GENERIC
1281 def_bool PCI_DOMAINS
1283 config PCI_NANOENGINE
1284 bool "BSE nanoEngine PCI support"
1285 depends on SA1100_NANOENGINE
1287 Enable PCI on the BSE nanoEngine board.
1292 config PCI_HOST_ITE8152
1294 depends on PCI && MACH_ARMCORE
1298 source "drivers/pci/Kconfig"
1299 source "drivers/pci/pcie/Kconfig"
1301 source "drivers/pcmcia/Kconfig"
1305 menu "Kernel Features"
1310 This option should be selected by machines which have an SMP-
1313 The only effect of this option is to make the SMP-related
1314 options available to the user for configuration.
1317 bool "Symmetric Multi-Processing"
1318 depends on CPU_V6K || CPU_V7
1319 depends on GENERIC_CLOCKEVENTS
1321 depends on MMU || ARM_MPU
1323 This enables support for systems with more than one CPU. If you have
1324 a system with only one CPU, say N. If you have a system with more
1325 than one CPU, say Y.
1327 If you say N here, the kernel will run on uni- and multiprocessor
1328 machines, but will use only one CPU of a multiprocessor machine. If
1329 you say Y here, the kernel will run on many, but not all,
1330 uniprocessor machines. On a uniprocessor machine, the kernel
1331 will run faster if you say N here.
1333 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1334 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1335 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1337 If you don't know what to do here, say N.
1340 bool "Allow booting SMP kernel on uniprocessor systems"
1341 depends on SMP && !XIP_KERNEL && MMU
1344 SMP kernels contain instructions which fail on non-SMP processors.
1345 Enabling this option allows the kernel to modify itself to make
1346 these instructions safe. Disabling it allows about 1K of space
1349 If you don't know what to do here, say Y.
1351 config ARM_CPU_TOPOLOGY
1352 bool "Support cpu topology definition"
1353 depends on SMP && CPU_V7
1356 Support ARM cpu topology definition. The MPIDR register defines
1357 affinity between processors which is then used to describe the cpu
1358 topology of an ARM System.
1361 bool "Multi-core scheduler support"
1362 depends on ARM_CPU_TOPOLOGY
1364 Multi-core scheduler support improves the CPU scheduler's decision
1365 making when dealing with multi-core CPU chips at a cost of slightly
1366 increased overhead in some places. If unsure say N here.
1369 bool "SMT scheduler support"
1370 depends on ARM_CPU_TOPOLOGY
1372 Improves the CPU scheduler's decision making when dealing with
1373 MultiThreading at a cost of slightly increased overhead in some
1374 places. If unsure say N here.
1379 This option enables support for the ARM system coherency unit
1381 config HAVE_ARM_ARCH_TIMER
1382 bool "Architected timer support"
1384 select ARM_ARCH_TIMER
1385 select GENERIC_CLOCKEVENTS
1387 This option enables support for the ARM architected timer
1392 select CLKSRC_OF if OF
1394 This options enables support for the ARM timer and watchdog unit
1397 bool "Multi-Cluster Power Management"
1398 depends on CPU_V7 && SMP
1400 This option provides the common power management infrastructure
1401 for (multi-)cluster based systems, such as big.LITTLE based
1404 config MCPM_QUAD_CLUSTER
1408 To avoid wasting resources unnecessarily, MCPM only supports up
1409 to 2 clusters by default.
1410 Platforms with 3 or 4 clusters that use MCPM must select this
1411 option to allow the additional clusters to be managed.
1414 bool "big.LITTLE support (Experimental)"
1415 depends on CPU_V7 && SMP
1418 This option enables support selections for the big.LITTLE
1419 system architecture.
1422 bool "big.LITTLE switcher support"
1423 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1424 select ARM_CPU_SUSPEND
1427 The big.LITTLE "switcher" provides the core functionality to
1428 transparently handle transition between a cluster of A15's
1429 and a cluster of A7's in a big.LITTLE system.
1431 config BL_SWITCHER_DUMMY_IF
1432 tristate "Simple big.LITTLE switcher user interface"
1433 depends on BL_SWITCHER && DEBUG_KERNEL
1435 This is a simple and dummy char dev interface to control
1436 the big.LITTLE switcher core code. It is meant for
1437 debugging purposes only.
1440 prompt "Memory split"
1444 Select the desired split between kernel and user memory.
1446 If you are not absolutely sure what you are doing, leave this
1450 bool "3G/1G user/kernel split"
1452 bool "2G/2G user/kernel split"
1454 bool "1G/3G user/kernel split"
1459 default PHYS_OFFSET if !MMU
1460 default 0x40000000 if VMSPLIT_1G
1461 default 0x80000000 if VMSPLIT_2G
1465 int "Maximum number of CPUs (2-32)"
1471 bool "Support for hot-pluggable CPUs"
1474 Say Y here to experiment with turning CPUs off and on. CPUs
1475 can be controlled through /sys/devices/system/cpu.
1478 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1481 Say Y here if you want Linux to communicate with system firmware
1482 implementing the PSCI specification for CPU-centric power
1483 management operations described in ARM document number ARM DEN
1484 0022A ("Power State Coordination Interface System Software on
1487 # The GPIO number here must be sorted by descending number. In case of
1488 # a multiplatform kernel, we just want the highest value required by the
1489 # selected platforms.
1492 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1493 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1494 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1495 default 416 if ARCH_SUNXI
1496 default 392 if ARCH_U8500
1497 default 352 if ARCH_VT8500
1498 default 288 if ARCH_ROCKCHIP
1499 default 264 if MACH_H4700
1502 Maximum number of GPIOs in the system.
1504 If unsure, leave the default value.
1506 source kernel/Kconfig.preempt
1510 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1511 ARCH_S5PV210 || ARCH_EXYNOS4
1512 default AT91_TIMER_HZ if ARCH_AT91
1513 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1517 depends on HZ_FIXED = 0
1518 prompt "Timer frequency"
1542 default HZ_FIXED if HZ_FIXED != 0
1543 default 100 if HZ_100
1544 default 200 if HZ_200
1545 default 250 if HZ_250
1546 default 300 if HZ_300
1547 default 500 if HZ_500
1551 def_bool HIGH_RES_TIMERS
1553 config THUMB2_KERNEL
1554 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1555 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1556 default y if CPU_THUMBONLY
1558 select ARM_ASM_UNIFIED
1561 By enabling this option, the kernel will be compiled in
1562 Thumb-2 mode. A compiler/assembler that understand the unified
1563 ARM-Thumb syntax is needed.
1567 config THUMB2_AVOID_R_ARM_THM_JUMP11
1568 bool "Work around buggy Thumb-2 short branch relocations in gas"
1569 depends on THUMB2_KERNEL && MODULES
1572 Various binutils versions can resolve Thumb-2 branches to
1573 locally-defined, preemptible global symbols as short-range "b.n"
1574 branch instructions.
1576 This is a problem, because there's no guarantee the final
1577 destination of the symbol, or any candidate locations for a
1578 trampoline, are within range of the branch. For this reason, the
1579 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1580 relocation in modules at all, and it makes little sense to add
1583 The symptom is that the kernel fails with an "unsupported
1584 relocation" error when loading some modules.
1586 Until fixed tools are available, passing
1587 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1588 code which hits this problem, at the cost of a bit of extra runtime
1589 stack usage in some cases.
1591 The problem is described in more detail at:
1592 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1594 Only Thumb-2 kernels are affected.
1596 Unless you are sure your tools don't have this problem, say Y.
1598 config ARM_ASM_UNIFIED
1602 bool "Use the ARM EABI to compile the kernel"
1604 This option allows for the kernel to be compiled using the latest
1605 ARM ABI (aka EABI). This is only useful if you are using a user
1606 space environment that is also compiled with EABI.
1608 Since there are major incompatibilities between the legacy ABI and
1609 EABI, especially with regard to structure member alignment, this
1610 option also changes the kernel syscall calling convention to
1611 disambiguate both ABIs and allow for backward compatibility support
1612 (selected with CONFIG_OABI_COMPAT).
1614 To use this you need GCC version 4.0.0 or later.
1617 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1618 depends on AEABI && !THUMB2_KERNEL
1620 This option preserves the old syscall interface along with the
1621 new (ARM EABI) one. It also provides a compatibility layer to
1622 intercept syscalls that have structure arguments which layout
1623 in memory differs between the legacy ABI and the new ARM EABI
1624 (only for non "thumb" binaries). This option adds a tiny
1625 overhead to all syscalls and produces a slightly larger kernel.
1627 The seccomp filter system will not be available when this is
1628 selected, since there is no way yet to sensibly distinguish
1629 between calling conventions during filtering.
1631 If you know you'll be using only pure EABI user space then you
1632 can say N here. If this option is not selected and you attempt
1633 to execute a legacy ABI binary then the result will be
1634 UNPREDICTABLE (in fact it can be predicted that it won't work
1635 at all). If in doubt say N.
1637 config ARCH_HAS_HOLES_MEMORYMODEL
1640 config ARCH_SPARSEMEM_ENABLE
1643 config ARCH_SPARSEMEM_DEFAULT
1644 def_bool ARCH_SPARSEMEM_ENABLE
1646 config ARCH_SELECT_MEMORY_MODEL
1647 def_bool ARCH_SPARSEMEM_ENABLE
1649 config HAVE_ARCH_PFN_VALID
1650 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1652 config HAVE_GENERIC_RCU_GUP
1657 bool "High Memory Support"
1660 The address space of ARM processors is only 4 Gigabytes large
1661 and it has to accommodate user address space, kernel address
1662 space as well as some memory mapped IO. That means that, if you
1663 have a large amount of physical memory and/or IO, not all of the
1664 memory can be "permanently mapped" by the kernel. The physical
1665 memory that is not permanently mapped is called "high memory".
1667 Depending on the selected kernel/user memory split, minimum
1668 vmalloc space and actual amount of RAM, you may not need this
1669 option which should result in a slightly faster kernel.
1674 bool "Allocate 2nd-level pagetables from highmem"
1677 config HW_PERF_EVENTS
1678 bool "Enable hardware performance counter support for perf events"
1679 depends on PERF_EVENTS
1682 Enable hardware performance counter support for perf events. If
1683 disabled, perf events will use software events only.
1685 config SYS_SUPPORTS_HUGETLBFS
1689 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1693 config ARCH_WANT_GENERAL_HUGETLB
1698 config FORCE_MAX_ZONEORDER
1699 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1700 range 11 64 if ARCH_SHMOBILE_LEGACY
1701 default "12" if SOC_AM33XX
1702 default "9" if SA1111 || ARCH_EFM32
1705 The kernel memory allocator divides physically contiguous memory
1706 blocks into "zones", where each zone is a power of two number of
1707 pages. This option selects the largest power of two that the kernel
1708 keeps in the memory allocator. If you need to allocate very large
1709 blocks of physically contiguous memory, then you may need to
1710 increase this value.
1712 This config option is actually maximum order plus one. For example,
1713 a value of 11 means that the largest free memory block is 2^10 pages.
1715 config ALIGNMENT_TRAP
1717 depends on CPU_CP15_MMU
1718 default y if !ARCH_EBSA110
1719 select HAVE_PROC_CPU if PROC_FS
1721 ARM processors cannot fetch/store information which is not
1722 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1723 address divisible by 4. On 32-bit ARM processors, these non-aligned
1724 fetch/store instructions will be emulated in software if you say
1725 here, which has a severe performance impact. This is necessary for
1726 correct operation of some network protocols. With an IP-only
1727 configuration it is safe to say N, otherwise say Y.
1729 config UACCESS_WITH_MEMCPY
1730 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1732 default y if CPU_FEROCEON
1734 Implement faster copy_to_user and clear_user methods for CPU
1735 cores where a 8-word STM instruction give significantly higher
1736 memory write throughput than a sequence of individual 32bit stores.
1738 A possible side effect is a slight increase in scheduling latency
1739 between threads sharing the same address space if they invoke
1740 such copy operations with large buffers.
1742 However, if the CPU data cache is using a write-allocate mode,
1743 this option is unlikely to provide any performance gain.
1747 prompt "Enable seccomp to safely compute untrusted bytecode"
1749 This kernel feature is useful for number crunching applications
1750 that may need to compute untrusted bytecode during their
1751 execution. By using pipes or other transports made available to
1752 the process as file descriptors supporting the read/write
1753 syscalls, it's possible to isolate those applications in
1754 their own address space using seccomp. Once seccomp is
1755 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1756 and the task is only allowed to execute a few safe syscalls
1757 defined by each seccomp mode.
1770 bool "Xen guest support on ARM"
1771 depends on ARM && AEABI && OF
1772 depends on CPU_V7 && !CPU_V6
1773 depends on !GENERIC_ATOMIC64
1775 select ARCH_DMA_ADDR_T_64BIT
1779 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1786 bool "Flattened Device Tree support"
1789 select OF_EARLY_FLATTREE
1790 select OF_RESERVED_MEM
1792 Include support for flattened device tree machine descriptions.
1795 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1798 This is the traditional way of passing data to the kernel at boot
1799 time. If you are solely relying on the flattened device tree (or
1800 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1801 to remove ATAGS support from your kernel binary. If unsure,
1804 config DEPRECATED_PARAM_STRUCT
1805 bool "Provide old way to pass kernel parameters"
1808 This was deprecated in 2001 and announced to live on for 5 years.
1809 Some old boot loaders still use this way.
1811 # Compressed boot loader in ROM. Yes, we really want to ask about
1812 # TEXT and BSS so we preserve their values in the config files.
1813 config ZBOOT_ROM_TEXT
1814 hex "Compressed ROM boot loader base address"
1817 The physical address at which the ROM-able zImage is to be
1818 placed in the target. Platforms which normally make use of
1819 ROM-able zImage formats normally set this to a suitable
1820 value in their defconfig file.
1822 If ZBOOT_ROM is not enabled, this has no effect.
1824 config ZBOOT_ROM_BSS
1825 hex "Compressed ROM boot loader BSS address"
1828 The base address of an area of read/write memory in the target
1829 for the ROM-able zImage which must be available while the
1830 decompressor is running. It must be large enough to hold the
1831 entire decompressed kernel plus an additional 128 KiB.
1832 Platforms which normally make use of ROM-able zImage formats
1833 normally set this to a suitable value in their defconfig file.
1835 If ZBOOT_ROM is not enabled, this has no effect.
1838 bool "Compressed boot loader in ROM/flash"
1839 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1840 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1842 Say Y here if you intend to execute your compressed kernel image
1843 (zImage) directly from ROM or flash. If unsure, say N.
1846 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1847 depends on ZBOOT_ROM && ARCH_SH7372
1848 default ZBOOT_ROM_NONE
1850 Include experimental SD/MMC loading code in the ROM-able zImage.
1851 With this enabled it is possible to write the ROM-able zImage
1852 kernel image to an MMC or SD card and boot the kernel straight
1853 from the reset vector. At reset the processor Mask ROM will load
1854 the first part of the ROM-able zImage which in turn loads the
1855 rest the kernel image to RAM.
1857 config ZBOOT_ROM_NONE
1858 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1860 Do not load image from SD or MMC
1862 config ZBOOT_ROM_MMCIF
1863 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1865 Load image from MMCIF hardware block.
1867 config ZBOOT_ROM_SH_MOBILE_SDHI
1868 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1870 Load image from SDHI hardware block
1874 config ARM_APPENDED_DTB
1875 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1878 With this option, the boot code will look for a device tree binary
1879 (DTB) appended to zImage
1880 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1882 This is meant as a backward compatibility convenience for those
1883 systems with a bootloader that can't be upgraded to accommodate
1884 the documented boot protocol using a device tree.
1886 Beware that there is very little in terms of protection against
1887 this option being confused by leftover garbage in memory that might
1888 look like a DTB header after a reboot if no actual DTB is appended
1889 to zImage. Do not leave this option active in a production kernel
1890 if you don't intend to always append a DTB. Proper passing of the
1891 location into r2 of a bootloader provided DTB is always preferable
1894 config ARM_ATAG_DTB_COMPAT
1895 bool "Supplement the appended DTB with traditional ATAG information"
1896 depends on ARM_APPENDED_DTB
1898 Some old bootloaders can't be updated to a DTB capable one, yet
1899 they provide ATAGs with memory configuration, the ramdisk address,
1900 the kernel cmdline string, etc. Such information is dynamically
1901 provided by the bootloader and can't always be stored in a static
1902 DTB. To allow a device tree enabled kernel to be used with such
1903 bootloaders, this option allows zImage to extract the information
1904 from the ATAG list and store it at run time into the appended DTB.
1907 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1908 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1910 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1911 bool "Use bootloader kernel arguments if available"
1913 Uses the command-line options passed by the boot loader instead of
1914 the device tree bootargs property. If the boot loader doesn't provide
1915 any, the device tree bootargs property will be used.
1917 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1918 bool "Extend with bootloader kernel arguments"
1920 The command-line arguments provided by the boot loader will be
1921 appended to the the device tree bootargs property.
1926 string "Default kernel command string"
1929 On some architectures (EBSA110 and CATS), there is currently no way
1930 for the boot loader to pass arguments to the kernel. For these
1931 architectures, you should supply some command-line options at build
1932 time by entering them here. As a minimum, you should specify the
1933 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1936 prompt "Kernel command line type" if CMDLINE != ""
1937 default CMDLINE_FROM_BOOTLOADER
1940 config CMDLINE_FROM_BOOTLOADER
1941 bool "Use bootloader kernel arguments if available"
1943 Uses the command-line options passed by the boot loader. If
1944 the boot loader doesn't provide any, the default kernel command
1945 string provided in CMDLINE will be used.
1947 config CMDLINE_EXTEND
1948 bool "Extend bootloader kernel arguments"
1950 The command-line arguments provided by the boot loader will be
1951 appended to the default kernel command string.
1953 config CMDLINE_FORCE
1954 bool "Always use the default kernel command string"
1956 Always use the default kernel command string, even if the boot
1957 loader passes other arguments to the kernel.
1958 This is useful if you cannot or don't want to change the
1959 command-line options your boot loader passes to the kernel.
1963 bool "Kernel Execute-In-Place from ROM"
1964 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1966 Execute-In-Place allows the kernel to run from non-volatile storage
1967 directly addressable by the CPU, such as NOR flash. This saves RAM
1968 space since the text section of the kernel is not loaded from flash
1969 to RAM. Read-write sections, such as the data section and stack,
1970 are still copied to RAM. The XIP kernel is not compressed since
1971 it has to run directly from flash, so it will take more space to
1972 store it. The flash address used to link the kernel object files,
1973 and for storing it, is configuration dependent. Therefore, if you
1974 say Y here, you must know the proper physical address where to
1975 store the kernel image depending on your own flash memory usage.
1977 Also note that the make target becomes "make xipImage" rather than
1978 "make zImage" or "make Image". The final kernel binary to put in
1979 ROM memory will be arch/arm/boot/xipImage.
1983 config XIP_PHYS_ADDR
1984 hex "XIP Kernel Physical Location"
1985 depends on XIP_KERNEL
1986 default "0x00080000"
1988 This is the physical address in your flash memory the kernel will
1989 be linked for and stored to. This address is dependent on your
1993 bool "Kexec system call (EXPERIMENTAL)"
1994 depends on (!SMP || PM_SLEEP_SMP)
1996 kexec is a system call that implements the ability to shutdown your
1997 current kernel, and to start another kernel. It is like a reboot
1998 but it is independent of the system firmware. And like a reboot
1999 you can start any kernel with it, not just Linux.
2001 It is an ongoing process to be certain the hardware in a machine
2002 is properly shutdown, so do not be surprised if this code does not
2003 initially work for you.
2006 bool "Export atags in procfs"
2007 depends on ATAGS && KEXEC
2010 Should the atags used to boot the kernel be exported in an "atags"
2011 file in procfs. Useful with kexec.
2014 bool "Build kdump crash kernel (EXPERIMENTAL)"
2016 Generate crash dump after being started by kexec. This should
2017 be normally only set in special crash dump kernels which are
2018 loaded in the main kernel with kexec-tools into a specially
2019 reserved region and then later executed after a crash by
2020 kdump/kexec. The crash dump kernel must be compiled to a
2021 memory address not used by the main kernel
2023 For more details see Documentation/kdump/kdump.txt
2025 config AUTO_ZRELADDR
2026 bool "Auto calculation of the decompressed kernel image address"
2028 ZRELADDR is the physical address where the decompressed kernel
2029 image will be placed. If AUTO_ZRELADDR is selected, the address
2030 will be determined at run-time by masking the current IP with
2031 0xf8000000. This assumes the zImage being placed in the first 128MB
2032 from start of memory.
2036 menu "CPU Power Management"
2038 source "drivers/cpufreq/Kconfig"
2040 source "drivers/cpuidle/Kconfig"
2044 menu "Floating point emulation"
2046 comment "At least one emulation must be selected"
2049 bool "NWFPE math emulation"
2050 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2052 Say Y to include the NWFPE floating point emulator in the kernel.
2053 This is necessary to run most binaries. Linux does not currently
2054 support floating point hardware so you need to say Y here even if
2055 your machine has an FPA or floating point co-processor podule.
2057 You may say N here if you are going to load the Acorn FPEmulator
2058 early in the bootup.
2061 bool "Support extended precision"
2062 depends on FPE_NWFPE
2064 Say Y to include 80-bit support in the kernel floating-point
2065 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2066 Note that gcc does not generate 80-bit operations by default,
2067 so in most cases this option only enlarges the size of the
2068 floating point emulator without any good reason.
2070 You almost surely want to say N here.
2073 bool "FastFPE math emulation (EXPERIMENTAL)"
2074 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2076 Say Y here to include the FAST floating point emulator in the kernel.
2077 This is an experimental much faster emulator which now also has full
2078 precision for the mantissa. It does not support any exceptions.
2079 It is very simple, and approximately 3-6 times faster than NWFPE.
2081 It should be sufficient for most programs. It may be not suitable
2082 for scientific calculations, but you have to check this for yourself.
2083 If you do not feel you need a faster FP emulation you should better
2087 bool "VFP-format floating point maths"
2088 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2090 Say Y to include VFP support code in the kernel. This is needed
2091 if your hardware includes a VFP unit.
2093 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2094 release notes and additional status information.
2096 Say N if your target does not have VFP hardware.
2104 bool "Advanced SIMD (NEON) Extension support"
2105 depends on VFPv3 && CPU_V7
2107 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2110 config KERNEL_MODE_NEON
2111 bool "Support for NEON in kernel mode"
2112 depends on NEON && AEABI
2114 Say Y to include support for NEON in kernel mode.
2118 menu "Userspace binary formats"
2120 source "fs/Kconfig.binfmt"
2124 menu "Power management options"
2126 source "kernel/power/Kconfig"
2128 config ARCH_SUSPEND_POSSIBLE
2129 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2130 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2133 config ARM_CPU_SUSPEND
2136 config ARCH_HIBERNATION_POSSIBLE
2139 default y if ARCH_SUSPEND_POSSIBLE
2143 source "net/Kconfig"
2145 source "drivers/Kconfig"
2149 source "arch/arm/Kconfig.debug"
2151 source "security/Kconfig"
2153 source "crypto/Kconfig"
2155 source "arch/arm/crypto/Kconfig"
2158 source "lib/Kconfig"
2160 source "arch/arm/kvm/Kconfig"