4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if MMU
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_SYSCALL_TRACEPOINTS
20 select HAVE_KPROBES if !XIP_KERNEL
21 select HAVE_KRETPROBES if (HAVE_KPROBES)
22 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
23 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
24 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
25 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
26 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
27 select HAVE_GENERIC_DMA_COHERENT
28 select HAVE_KERNEL_GZIP
29 select HAVE_KERNEL_LZO
30 select HAVE_KERNEL_LZMA
33 select HAVE_PERF_EVENTS
34 select PERF_USE_VMALLOC
35 select HAVE_REGS_AND_STACK_ACCESS_API
36 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
37 select HAVE_C_RECORDMCOUNT
38 select HAVE_GENERIC_HARDIRQS
39 select HARDIRQS_SW_RESEND
40 select GENERIC_IRQ_PROBE
41 select GENERIC_IRQ_SHOW
42 select ARCH_WANT_IPC_PARSE_VERSION
43 select HARDIRQS_SW_RESEND
44 select CPU_PM if (SUSPEND || CPU_IDLE)
45 select GENERIC_PCI_IOMAP
47 select GENERIC_SMP_IDLE_THREAD
49 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
50 select GENERIC_STRNCPY_FROM_USER
51 select GENERIC_STRNLEN_USER
52 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
54 The ARM series is a line of low-power-consumption RISC chip designs
55 licensed by ARM Ltd and targeted at embedded applications and
56 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
57 manufactured, but legacy ARM-based PC hardware remains popular in
58 Europe. There is an ARM Linux project with a web page at
59 <http://www.arm.linux.org.uk/>.
61 config ARM_HAS_SG_CHAIN
64 config NEED_SG_DMA_LENGTH
67 config ARM_DMA_USE_IOMMU
68 select NEED_SG_DMA_LENGTH
69 select ARM_HAS_SG_CHAIN
78 config SYS_SUPPORTS_APM_EMULATION
86 select GENERIC_ALLOCATOR
97 The Extended Industry Standard Architecture (EISA) bus was
98 developed as an open alternative to the IBM MicroChannel bus.
100 The EISA bus provided some of the features of the IBM MicroChannel
101 bus while maintaining backward compatibility with cards made for
102 the older ISA bus. The EISA bus saw limited use between 1988 and
103 1995 when it was made obsolete by the PCI bus.
105 Say Y here if you are building a kernel for an EISA-based machine.
112 config STACKTRACE_SUPPORT
116 config HAVE_LATENCYTOP_SUPPORT
121 config LOCKDEP_SUPPORT
125 config TRACE_IRQFLAGS_SUPPORT
129 config RWSEM_GENERIC_SPINLOCK
133 config RWSEM_XCHGADD_ALGORITHM
136 config ARCH_HAS_ILOG2_U32
139 config ARCH_HAS_ILOG2_U64
142 config ARCH_HAS_CPUFREQ
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
169 config GENERIC_ISA_DMA
175 config NEED_RET_TO_USER
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_GPIO_H
209 Select this when mach/gpio.h is required to provide special
210 definitions for this platform. The need for mach/gpio.h should
211 be avoided when possible.
213 config NEED_MACH_IO_H
216 Select this when mach/io.h is required to provide special
217 definitions for this platform. The need for mach/io.h should
218 be avoided when possible.
220 config NEED_MACH_MEMORY_H
223 Select this when mach/memory.h is required to provide special
224 definitions for this platform. The need for mach/memory.h should
225 be avoided when possible.
228 hex "Physical address of main memory" if MMU
229 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
230 default DRAM_BASE if !MMU
232 Please provide the physical address corresponding to the
233 location of main memory in your system.
239 source "init/Kconfig"
241 source "kernel/Kconfig.freezer"
246 bool "MMU-based Paged Memory Management Support"
249 Select if you want MMU-based virtualised addressing space
250 support by paged memory management. If unsure, say 'Y'.
253 # The "ARM system type" choice list is ordered alphabetically by option
254 # text. Please add new entries in the option alphabetic order.
257 prompt "ARM system type"
258 default ARCH_MULTIPLATFORM
260 config ARCH_MULTIPLATFORM
261 bool "Allow multiple platforms to be selected"
262 select ARM_PATCH_PHYS_VIRT
265 select MULTI_IRQ_HANDLER
270 config ARCH_INTEGRATOR
271 bool "ARM Ltd. Integrator family"
273 select ARCH_HAS_CPUFREQ
275 select COMMON_CLK_VERSATILE
278 select GENERIC_CLOCKEVENTS
279 select PLAT_VERSATILE
280 select PLAT_VERSATILE_FPGA_IRQ
281 select NEED_MACH_MEMORY_H
283 select MULTI_IRQ_HANDLER
285 Support for ARM's Integrator platform.
288 bool "ARM Ltd. RealView family"
291 select COMMON_CLK_VERSATILE
293 select GENERIC_CLOCKEVENTS
294 select ARCH_WANT_OPTIONAL_GPIOLIB
295 select PLAT_VERSATILE
296 select PLAT_VERSATILE_CLCD
297 select ARM_TIMER_SP804
298 select GPIO_PL061 if GPIOLIB
299 select NEED_MACH_MEMORY_H
301 This enables support for ARM Ltd RealView boards.
303 config ARCH_VERSATILE
304 bool "ARM Ltd. Versatile family"
308 select HAVE_MACH_CLKDEV
310 select GENERIC_CLOCKEVENTS
311 select ARCH_WANT_OPTIONAL_GPIOLIB
312 select PLAT_VERSATILE
313 select PLAT_VERSATILE_CLOCK
314 select PLAT_VERSATILE_CLCD
315 select PLAT_VERSATILE_FPGA_IRQ
316 select ARM_TIMER_SP804
318 This enables support for ARM Ltd Versatile board.
322 select ARCH_REQUIRE_GPIOLIB
326 select NEED_MACH_GPIO_H
327 select NEED_MACH_IO_H if PCCARD
329 This enables support for systems based on Atmel
330 AT91RM9200 and AT91SAM9* processors.
333 bool "Broadcom BCM2835 family"
334 select ARCH_WANT_OPTIONAL_GPIOLIB
336 select ARM_ERRATA_411920
337 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
342 select MULTI_IRQ_HANDLER
346 This enables support for the Broadcom BCM2835 SoC. This SoC is
347 use in the Raspberry Pi, and Roku 2 devices.
350 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
352 select ARCH_USES_GETTIMEOFFSET
355 select NEED_MACH_MEMORY_H
357 Support for Cirrus Logic 711x/721x/731x based boards.
360 bool "Cavium Networks CNS3XXX family"
362 select GENERIC_CLOCKEVENTS
364 select MIGHT_HAVE_CACHE_L2X0
365 select MIGHT_HAVE_PCI
366 select PCI_DOMAINS if PCI
368 Support for Cavium Networks CNS3XXX platform.
371 bool "Cortina Systems Gemini"
373 select ARCH_REQUIRE_GPIOLIB
374 select ARCH_USES_GETTIMEOFFSET
376 Support for the Cortina Systems Gemini family SoCs
381 select ARCH_REQUIRE_GPIOLIB
382 select GENERIC_CLOCKEVENTS
384 select GENERIC_IRQ_CHIP
385 select MIGHT_HAVE_CACHE_L2X0
390 Support for CSR SiRFprimaII/Marco/Polo platforms
397 select ARCH_USES_GETTIMEOFFSET
398 select NEED_MACH_IO_H
399 select NEED_MACH_MEMORY_H
401 This is an evaluation board for the StrongARM processor available
402 from Digital. It has limited hardware on-board, including an
403 Ethernet interface, two PCMCIA sockets, two serial ports and a
412 select ARCH_REQUIRE_GPIOLIB
413 select ARCH_HAS_HOLES_MEMORYMODEL
414 select ARCH_USES_GETTIMEOFFSET
415 select NEED_MACH_MEMORY_H
417 This enables support for the Cirrus EP93xx series of CPUs.
419 config ARCH_FOOTBRIDGE
423 select GENERIC_CLOCKEVENTS
425 select NEED_MACH_IO_H if !MMU
426 select NEED_MACH_MEMORY_H
428 Support for systems based on the DC21285 companion chip
429 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
432 bool "Freescale MXC/iMX-based"
433 select GENERIC_CLOCKEVENTS
434 select ARCH_REQUIRE_GPIOLIB
437 select GENERIC_IRQ_CHIP
438 select MULTI_IRQ_HANDLER
442 Support for Freescale MXC/iMX-based family of processors
445 bool "Freescale MXS-based"
446 select GENERIC_CLOCKEVENTS
447 select ARCH_REQUIRE_GPIOLIB
451 select HAVE_CLK_PREPARE
452 select MULTI_IRQ_HANDLER
457 Support for Freescale MXS-based family of processors
460 bool "Hilscher NetX based"
464 select GENERIC_CLOCKEVENTS
466 This enables support for systems based on the Hilscher NetX Soc
469 bool "Hynix HMS720x-based"
472 select ARCH_USES_GETTIMEOFFSET
474 This enables support for systems based on the Hynix HMS720x
482 select ARCH_SUPPORTS_MSI
484 select NEED_MACH_MEMORY_H
485 select NEED_RET_TO_USER
487 Support for Intel's IOP13XX (XScale) family of processors.
493 select NEED_MACH_GPIO_H
494 select NEED_RET_TO_USER
497 select ARCH_REQUIRE_GPIOLIB
499 Support for Intel's 80219 and IOP32X (XScale) family of
506 select NEED_MACH_GPIO_H
507 select NEED_RET_TO_USER
510 select ARCH_REQUIRE_GPIOLIB
512 Support for Intel's IOP33X (XScale) family of processors.
517 select ARCH_HAS_DMA_SET_COHERENT_MASK
520 select ARCH_REQUIRE_GPIOLIB
521 select GENERIC_CLOCKEVENTS
522 select MIGHT_HAVE_PCI
523 select NEED_MACH_IO_H
524 select DMABOUNCE if PCI
526 Support for Intel's IXP4XX (XScale) family of processors.
531 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
533 select MIGHT_HAVE_PCI
534 select PLAT_ORION_LEGACY
535 select USB_ARCH_HAS_EHCI
537 Support for the Marvell Dove SoC 88AP510
540 bool "Marvell Kirkwood"
543 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
545 select PLAT_ORION_LEGACY
547 Support for the following Marvell Kirkwood series SoCs:
548 88F6180, 88F6192 and 88F6281.
554 select ARCH_REQUIRE_GPIOLIB
557 select USB_ARCH_HAS_OHCI
559 select GENERIC_CLOCKEVENTS
563 Support for the NXP LPC32XX family of processors
566 bool "Marvell MV78xx0"
569 select ARCH_REQUIRE_GPIOLIB
570 select GENERIC_CLOCKEVENTS
571 select PLAT_ORION_LEGACY
573 Support for the following Marvell MV78xx0 series SoCs:
581 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
583 select PLAT_ORION_LEGACY
585 Support for the following Marvell Orion 5x series SoCs:
586 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
587 Orion-2 (5281), Orion-1-90 (6183).
590 bool "Marvell PXA168/910/MMP2"
592 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
599 select GENERIC_ALLOCATOR
600 select NEED_MACH_GPIO_H
602 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
605 bool "Micrel/Kendin KS8695"
607 select ARCH_REQUIRE_GPIOLIB
608 select NEED_MACH_MEMORY_H
610 select GENERIC_CLOCKEVENTS
612 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
613 System-on-Chip devices.
616 bool "Nuvoton W90X900 CPU"
618 select ARCH_REQUIRE_GPIOLIB
621 select GENERIC_CLOCKEVENTS
623 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
624 At present, the w90x900 has been renamed nuc900, regarding
625 the ARM series product line, you can login the following
626 link address to know more.
628 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
629 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
635 select GENERIC_CLOCKEVENTS
639 select MIGHT_HAVE_CACHE_L2X0
640 select ARCH_HAS_CPUFREQ
644 This enables support for NVIDIA Tegra based systems (Tegra APX,
645 Tegra 6xx and Tegra 2 series).
648 bool "PXA2xx/PXA3xx-based"
651 select ARCH_HAS_CPUFREQ
654 select ARCH_REQUIRE_GPIOLIB
655 select GENERIC_CLOCKEVENTS
660 select MULTI_IRQ_HANDLER
661 select ARM_CPU_SUSPEND if PM
663 select NEED_MACH_GPIO_H
665 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
670 select GENERIC_CLOCKEVENTS
671 select ARCH_REQUIRE_GPIOLIB
674 Support for Qualcomm MSM/QSD based systems. This runs on the
675 apps processor of the MSM/QSD and depends on a shared memory
676 interface to the modem processor which runs the baseband
677 stack and controls some vital subsystems
678 (clock and power control, etc).
681 bool "Renesas SH-Mobile / R-Mobile"
684 select HAVE_MACH_CLKDEV
686 select GENERIC_CLOCKEVENTS
687 select MIGHT_HAVE_CACHE_L2X0
690 select MULTI_IRQ_HANDLER
691 select PM_GENERIC_DOMAINS if PM
692 select NEED_MACH_MEMORY_H
694 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
700 select ARCH_MAY_HAVE_PC_FDC
701 select HAVE_PATA_PLATFORM
704 select ARCH_SPARSEMEM_ENABLE
705 select ARCH_USES_GETTIMEOFFSET
707 select NEED_MACH_IO_H
708 select NEED_MACH_MEMORY_H
710 On the Acorn Risc-PC, Linux can support the internal IDE disk and
711 CD-ROM interface, serial and parallel port, and the floppy drive.
718 select ARCH_SPARSEMEM_ENABLE
720 select ARCH_HAS_CPUFREQ
722 select GENERIC_CLOCKEVENTS
724 select ARCH_REQUIRE_GPIOLIB
726 select NEED_MACH_GPIO_H
727 select NEED_MACH_MEMORY_H
730 Support for StrongARM 11x0 based boards.
733 bool "Samsung S3C24XX SoCs"
735 select ARCH_HAS_CPUFREQ
738 select ARCH_USES_GETTIMEOFFSET
739 select HAVE_S3C2410_I2C if I2C
740 select HAVE_S3C_RTC if RTC_CLASS
741 select HAVE_S3C2410_WATCHDOG if WATCHDOG
742 select NEED_MACH_GPIO_H
743 select NEED_MACH_IO_H
745 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
746 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
747 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
748 Samsung SMDK2410 development board (and derivatives).
751 bool "Samsung S3C64XX"
759 select ARCH_USES_GETTIMEOFFSET
760 select ARCH_HAS_CPUFREQ
761 select ARCH_REQUIRE_GPIOLIB
762 select SAMSUNG_CLKSRC
763 select SAMSUNG_IRQ_VIC_TIMER
764 select S3C_GPIO_TRACK
766 select USB_ARCH_HAS_OHCI
767 select SAMSUNG_GPIOLIB_4BIT
768 select HAVE_S3C2410_I2C if I2C
769 select HAVE_S3C2410_WATCHDOG if WATCHDOG
770 select NEED_MACH_GPIO_H
772 Samsung S3C64XX series based systems
775 bool "Samsung S5P6440 S5P6450"
781 select HAVE_S3C2410_WATCHDOG if WATCHDOG
782 select GENERIC_CLOCKEVENTS
783 select HAVE_S3C2410_I2C if I2C
784 select HAVE_S3C_RTC if RTC_CLASS
785 select NEED_MACH_GPIO_H
787 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
791 bool "Samsung S5PC100"
796 select ARCH_USES_GETTIMEOFFSET
797 select HAVE_S3C2410_I2C if I2C
798 select HAVE_S3C_RTC if RTC_CLASS
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
800 select NEED_MACH_GPIO_H
802 Samsung S5PC100 series based systems
805 bool "Samsung S5PV210/S5PC110"
807 select ARCH_SPARSEMEM_ENABLE
808 select ARCH_HAS_HOLES_MEMORYMODEL
813 select ARCH_HAS_CPUFREQ
814 select GENERIC_CLOCKEVENTS
815 select HAVE_S3C2410_I2C if I2C
816 select HAVE_S3C_RTC if RTC_CLASS
817 select HAVE_S3C2410_WATCHDOG if WATCHDOG
818 select NEED_MACH_GPIO_H
819 select NEED_MACH_MEMORY_H
821 Samsung S5PV210/S5PC110 series based systems
824 bool "SAMSUNG EXYNOS"
826 select ARCH_SPARSEMEM_ENABLE
827 select ARCH_HAS_HOLES_MEMORYMODEL
831 select ARCH_HAS_CPUFREQ
832 select GENERIC_CLOCKEVENTS
833 select HAVE_S3C_RTC if RTC_CLASS
834 select HAVE_S3C2410_I2C if I2C
835 select HAVE_S3C2410_WATCHDOG if WATCHDOG
836 select NEED_MACH_GPIO_H
837 select NEED_MACH_MEMORY_H
839 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
848 select ARCH_USES_GETTIMEOFFSET
849 select NEED_MACH_MEMORY_H
851 Support for the StrongARM based Digital DNARD machine, also known
852 as "Shark" (<http://www.shark-linux.de/shark.html>).
855 bool "ST-Ericsson U300 Series"
861 select ARM_PATCH_PHYS_VIRT
863 select GENERIC_CLOCKEVENTS
867 select ARCH_REQUIRE_GPIOLIB
870 Support for ST-Ericsson U300 series mobile platforms.
873 bool "ST-Ericsson U8500 Series"
877 select GENERIC_CLOCKEVENTS
879 select ARCH_REQUIRE_GPIOLIB
880 select ARCH_HAS_CPUFREQ
882 select MIGHT_HAVE_CACHE_L2X0
884 Support for ST-Ericsson's Ux500 architecture
887 bool "STMicroelectronics Nomadik"
892 select GENERIC_CLOCKEVENTS
894 select PINCTRL_STN8815
895 select MIGHT_HAVE_CACHE_L2X0
896 select ARCH_REQUIRE_GPIOLIB
898 Support for the Nomadik platform by ST-Ericsson
902 select GENERIC_CLOCKEVENTS
903 select ARCH_REQUIRE_GPIOLIB
907 select GENERIC_ALLOCATOR
908 select GENERIC_IRQ_CHIP
909 select ARCH_HAS_HOLES_MEMORYMODEL
910 select NEED_MACH_GPIO_H
912 Support for TI's DaVinci platform.
918 select ARCH_REQUIRE_GPIOLIB
919 select ARCH_HAS_CPUFREQ
921 select GENERIC_CLOCKEVENTS
922 select ARCH_HAS_HOLES_MEMORYMODEL
923 select NEED_MACH_GPIO_H
925 Support for TI's OMAP platform (OMAP1/2/3/4).
930 select ARCH_REQUIRE_GPIOLIB
934 select GENERIC_CLOCKEVENTS
937 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
940 bool "VIA/WonderMedia 85xx"
943 select ARCH_HAS_CPUFREQ
944 select GENERIC_CLOCKEVENTS
945 select ARCH_REQUIRE_GPIOLIB
951 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
954 bool "Xilinx Zynq ARM Cortex A9 Platform"
956 select GENERIC_CLOCKEVENTS
961 select MIGHT_HAVE_CACHE_L2X0
964 Support for Xilinx Zynq ARM Cortex A9 Platform
967 menu "Multiple platform selection"
968 depends on ARCH_MULTIPLATFORM
970 comment "CPU Core family selection"
973 bool "ARMv4 based platforms (FA526, StrongARM)"
974 select ARCH_MULTI_V4_V5
975 depends on !ARCH_MULTI_V6_V7
977 config ARCH_MULTI_V4T
978 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
979 select ARCH_MULTI_V4_V5
980 depends on !ARCH_MULTI_V6_V7
983 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
984 select ARCH_MULTI_V4_V5
985 depends on !ARCH_MULTI_V6_V7
987 config ARCH_MULTI_V4_V5
991 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
993 select ARCH_MULTI_V6_V7
996 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1000 select ARCH_MULTI_V6_V7
1002 config ARCH_MULTI_V6_V7
1005 config ARCH_MULTI_CPU_AUTO
1006 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1007 select ARCH_MULTI_V5
1012 # This is sorted alphabetically by mach-* pathname. However, plat-*
1013 # Kconfigs may be included either alphabetically (according to the
1014 # plat- suffix) or along side the corresponding mach-* source.
1016 source "arch/arm/mach-mvebu/Kconfig"
1018 source "arch/arm/mach-at91/Kconfig"
1020 source "arch/arm/mach-clps711x/Kconfig"
1022 source "arch/arm/mach-cns3xxx/Kconfig"
1024 source "arch/arm/mach-davinci/Kconfig"
1026 source "arch/arm/mach-dove/Kconfig"
1028 source "arch/arm/mach-ep93xx/Kconfig"
1030 source "arch/arm/mach-footbridge/Kconfig"
1032 source "arch/arm/mach-gemini/Kconfig"
1034 source "arch/arm/mach-h720x/Kconfig"
1036 source "arch/arm/mach-highbank/Kconfig"
1038 source "arch/arm/mach-integrator/Kconfig"
1040 source "arch/arm/mach-iop32x/Kconfig"
1042 source "arch/arm/mach-iop33x/Kconfig"
1044 source "arch/arm/mach-iop13xx/Kconfig"
1046 source "arch/arm/mach-ixp4xx/Kconfig"
1048 source "arch/arm/mach-kirkwood/Kconfig"
1050 source "arch/arm/mach-ks8695/Kconfig"
1052 source "arch/arm/mach-msm/Kconfig"
1054 source "arch/arm/mach-mv78xx0/Kconfig"
1056 source "arch/arm/plat-mxc/Kconfig"
1058 source "arch/arm/mach-mxs/Kconfig"
1060 source "arch/arm/mach-netx/Kconfig"
1062 source "arch/arm/mach-nomadik/Kconfig"
1063 source "arch/arm/plat-nomadik/Kconfig"
1065 source "arch/arm/plat-omap/Kconfig"
1067 source "arch/arm/mach-omap1/Kconfig"
1069 source "arch/arm/mach-omap2/Kconfig"
1071 source "arch/arm/mach-orion5x/Kconfig"
1073 source "arch/arm/mach-picoxcell/Kconfig"
1075 source "arch/arm/mach-pxa/Kconfig"
1076 source "arch/arm/plat-pxa/Kconfig"
1078 source "arch/arm/mach-mmp/Kconfig"
1080 source "arch/arm/mach-realview/Kconfig"
1082 source "arch/arm/mach-sa1100/Kconfig"
1084 source "arch/arm/plat-samsung/Kconfig"
1085 source "arch/arm/plat-s3c24xx/Kconfig"
1087 source "arch/arm/mach-socfpga/Kconfig"
1089 source "arch/arm/plat-spear/Kconfig"
1091 source "arch/arm/mach-s3c24xx/Kconfig"
1093 source "arch/arm/mach-s3c2412/Kconfig"
1094 source "arch/arm/mach-s3c2440/Kconfig"
1098 source "arch/arm/mach-s3c64xx/Kconfig"
1101 source "arch/arm/mach-s5p64x0/Kconfig"
1103 source "arch/arm/mach-s5pc100/Kconfig"
1105 source "arch/arm/mach-s5pv210/Kconfig"
1107 source "arch/arm/mach-exynos/Kconfig"
1109 source "arch/arm/mach-shmobile/Kconfig"
1111 source "arch/arm/mach-prima2/Kconfig"
1113 source "arch/arm/mach-tegra/Kconfig"
1115 source "arch/arm/mach-u300/Kconfig"
1117 source "arch/arm/mach-ux500/Kconfig"
1119 source "arch/arm/mach-versatile/Kconfig"
1121 source "arch/arm/mach-vexpress/Kconfig"
1122 source "arch/arm/plat-versatile/Kconfig"
1124 source "arch/arm/mach-w90x900/Kconfig"
1126 # Definitions to make life easier
1132 select GENERIC_CLOCKEVENTS
1137 select GENERIC_IRQ_CHIP
1141 config PLAT_ORION_LEGACY
1148 config PLAT_VERSATILE
1151 config ARM_TIMER_SP804
1154 select HAVE_SCHED_CLOCK
1156 source arch/arm/mm/Kconfig
1160 default 16 if ARCH_EP93XX
1164 bool "Enable iWMMXt support"
1165 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1166 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1168 Enable support for iWMMXt context switching at run time if
1169 running on a CPU that supports it.
1173 depends on CPU_XSCALE
1176 config MULTI_IRQ_HANDLER
1179 Allow each machine to specify it's own IRQ handler at run time.
1182 source "arch/arm/Kconfig-nommu"
1185 config ARM_ERRATA_326103
1186 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1189 Executing a SWP instruction to read-only memory does not set bit 11
1190 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1191 treat the access as a read, preventing a COW from occurring and
1192 causing the faulting task to livelock.
1194 config ARM_ERRATA_411920
1195 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1196 depends on CPU_V6 || CPU_V6K
1198 Invalidation of the Instruction Cache operation can
1199 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1200 It does not affect the MPCore. This option enables the ARM Ltd.
1201 recommended workaround.
1203 config ARM_ERRATA_430973
1204 bool "ARM errata: Stale prediction on replaced interworking branch"
1207 This option enables the workaround for the 430973 Cortex-A8
1208 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1209 interworking branch is replaced with another code sequence at the
1210 same virtual address, whether due to self-modifying code or virtual
1211 to physical address re-mapping, Cortex-A8 does not recover from the
1212 stale interworking branch prediction. This results in Cortex-A8
1213 executing the new code sequence in the incorrect ARM or Thumb state.
1214 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1215 and also flushes the branch target cache at every context switch.
1216 Note that setting specific bits in the ACTLR register may not be
1217 available in non-secure mode.
1219 config ARM_ERRATA_458693
1220 bool "ARM errata: Processor deadlock when a false hazard is created"
1223 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1224 erratum. For very specific sequences of memory operations, it is
1225 possible for a hazard condition intended for a cache line to instead
1226 be incorrectly associated with a different cache line. This false
1227 hazard might then cause a processor deadlock. The workaround enables
1228 the L1 caching of the NEON accesses and disables the PLD instruction
1229 in the ACTLR register. Note that setting specific bits in the ACTLR
1230 register may not be available in non-secure mode.
1232 config ARM_ERRATA_460075
1233 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1236 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1237 erratum. Any asynchronous access to the L2 cache may encounter a
1238 situation in which recent store transactions to the L2 cache are lost
1239 and overwritten with stale memory contents from external memory. The
1240 workaround disables the write-allocate mode for the L2 cache via the
1241 ACTLR register. Note that setting specific bits in the ACTLR register
1242 may not be available in non-secure mode.
1244 config ARM_ERRATA_742230
1245 bool "ARM errata: DMB operation may be faulty"
1246 depends on CPU_V7 && SMP
1248 This option enables the workaround for the 742230 Cortex-A9
1249 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1250 between two write operations may not ensure the correct visibility
1251 ordering of the two writes. This workaround sets a specific bit in
1252 the diagnostic register of the Cortex-A9 which causes the DMB
1253 instruction to behave as a DSB, ensuring the correct behaviour of
1256 config ARM_ERRATA_742231
1257 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1258 depends on CPU_V7 && SMP
1260 This option enables the workaround for the 742231 Cortex-A9
1261 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1262 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1263 accessing some data located in the same cache line, may get corrupted
1264 data due to bad handling of the address hazard when the line gets
1265 replaced from one of the CPUs at the same time as another CPU is
1266 accessing it. This workaround sets specific bits in the diagnostic
1267 register of the Cortex-A9 which reduces the linefill issuing
1268 capabilities of the processor.
1270 config PL310_ERRATA_588369
1271 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1272 depends on CACHE_L2X0
1274 The PL310 L2 cache controller implements three types of Clean &
1275 Invalidate maintenance operations: by Physical Address
1276 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1277 They are architecturally defined to behave as the execution of a
1278 clean operation followed immediately by an invalidate operation,
1279 both performing to the same memory location. This functionality
1280 is not correctly implemented in PL310 as clean lines are not
1281 invalidated as a result of these operations.
1283 config ARM_ERRATA_720789
1284 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1287 This option enables the workaround for the 720789 Cortex-A9 (prior to
1288 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1289 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1290 As a consequence of this erratum, some TLB entries which should be
1291 invalidated are not, resulting in an incoherency in the system page
1292 tables. The workaround changes the TLB flushing routines to invalidate
1293 entries regardless of the ASID.
1295 config PL310_ERRATA_727915
1296 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1297 depends on CACHE_L2X0
1299 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1300 operation (offset 0x7FC). This operation runs in background so that
1301 PL310 can handle normal accesses while it is in progress. Under very
1302 rare circumstances, due to this erratum, write data can be lost when
1303 PL310 treats a cacheable write transaction during a Clean &
1304 Invalidate by Way operation.
1306 config ARM_ERRATA_743622
1307 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1310 This option enables the workaround for the 743622 Cortex-A9
1311 (r2p*) erratum. Under very rare conditions, a faulty
1312 optimisation in the Cortex-A9 Store Buffer may lead to data
1313 corruption. This workaround sets a specific bit in the diagnostic
1314 register of the Cortex-A9 which disables the Store Buffer
1315 optimisation, preventing the defect from occurring. This has no
1316 visible impact on the overall performance or power consumption of the
1319 config ARM_ERRATA_751472
1320 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1323 This option enables the workaround for the 751472 Cortex-A9 (prior
1324 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1325 completion of a following broadcasted operation if the second
1326 operation is received by a CPU before the ICIALLUIS has completed,
1327 potentially leading to corrupted entries in the cache or TLB.
1329 config PL310_ERRATA_753970
1330 bool "PL310 errata: cache sync operation may be faulty"
1331 depends on CACHE_PL310
1333 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1335 Under some condition the effect of cache sync operation on
1336 the store buffer still remains when the operation completes.
1337 This means that the store buffer is always asked to drain and
1338 this prevents it from merging any further writes. The workaround
1339 is to replace the normal offset of cache sync operation (0x730)
1340 by another offset targeting an unmapped PL310 register 0x740.
1341 This has the same effect as the cache sync operation: store buffer
1342 drain and waiting for all buffers empty.
1344 config ARM_ERRATA_754322
1345 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1348 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1349 r3p*) erratum. A speculative memory access may cause a page table walk
1350 which starts prior to an ASID switch but completes afterwards. This
1351 can populate the micro-TLB with a stale entry which may be hit with
1352 the new ASID. This workaround places two dsb instructions in the mm
1353 switching code so that no page table walks can cross the ASID switch.
1355 config ARM_ERRATA_754327
1356 bool "ARM errata: no automatic Store Buffer drain"
1357 depends on CPU_V7 && SMP
1359 This option enables the workaround for the 754327 Cortex-A9 (prior to
1360 r2p0) erratum. The Store Buffer does not have any automatic draining
1361 mechanism and therefore a livelock may occur if an external agent
1362 continuously polls a memory location waiting to observe an update.
1363 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1364 written polling loops from denying visibility of updates to memory.
1366 config ARM_ERRATA_364296
1367 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1368 depends on CPU_V6 && !SMP
1370 This options enables the workaround for the 364296 ARM1136
1371 r0p2 erratum (possible cache data corruption with
1372 hit-under-miss enabled). It sets the undocumented bit 31 in
1373 the auxiliary control register and the FI bit in the control
1374 register, thus disabling hit-under-miss without putting the
1375 processor into full low interrupt latency mode. ARM11MPCore
1378 config ARM_ERRATA_764369
1379 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1380 depends on CPU_V7 && SMP
1382 This option enables the workaround for erratum 764369
1383 affecting Cortex-A9 MPCore with two or more processors (all
1384 current revisions). Under certain timing circumstances, a data
1385 cache line maintenance operation by MVA targeting an Inner
1386 Shareable memory region may fail to proceed up to either the
1387 Point of Coherency or to the Point of Unification of the
1388 system. This workaround adds a DSB instruction before the
1389 relevant cache maintenance functions and sets a specific bit
1390 in the diagnostic control register of the SCU.
1392 config PL310_ERRATA_769419
1393 bool "PL310 errata: no automatic Store Buffer drain"
1394 depends on CACHE_L2X0
1396 On revisions of the PL310 prior to r3p2, the Store Buffer does
1397 not automatically drain. This can cause normal, non-cacheable
1398 writes to be retained when the memory system is idle, leading
1399 to suboptimal I/O performance for drivers using coherent DMA.
1400 This option adds a write barrier to the cpu_idle loop so that,
1401 on systems with an outer cache, the store buffer is drained
1404 config ARM_ERRATA_775420
1405 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1408 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1409 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1410 operation aborts with MMU exception, it might cause the processor
1411 to deadlock. This workaround puts DSB before executing ISB if
1412 an abort may occur on cache maintenance.
1416 source "arch/arm/common/Kconfig"
1426 Find out whether you have ISA slots on your motherboard. ISA is the
1427 name of a bus system, i.e. the way the CPU talks to the other stuff
1428 inside your box. Other bus systems are PCI, EISA, MicroChannel
1429 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1430 newer boards don't support it. If you have ISA, say Y, otherwise N.
1432 # Select ISA DMA controller support
1437 # Select ISA DMA interface
1442 bool "PCI support" if MIGHT_HAVE_PCI
1444 Find out whether you have a PCI motherboard. PCI is the name of a
1445 bus system, i.e. the way the CPU talks to the other stuff inside
1446 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1447 VESA. If you have PCI, say Y, otherwise N.
1453 config PCI_NANOENGINE
1454 bool "BSE nanoEngine PCI support"
1455 depends on SA1100_NANOENGINE
1457 Enable PCI on the BSE nanoEngine board.
1462 # Select the host bridge type
1463 config PCI_HOST_VIA82C505
1465 depends on PCI && ARCH_SHARK
1468 config PCI_HOST_ITE8152
1470 depends on PCI && MACH_ARMCORE
1474 source "drivers/pci/Kconfig"
1476 source "drivers/pcmcia/Kconfig"
1480 menu "Kernel Features"
1485 This option should be selected by machines which have an SMP-
1488 The only effect of this option is to make the SMP-related
1489 options available to the user for configuration.
1492 bool "Symmetric Multi-Processing"
1493 depends on CPU_V6K || CPU_V7
1494 depends on GENERIC_CLOCKEVENTS
1497 select USE_GENERIC_SMP_HELPERS
1498 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1500 This enables support for systems with more than one CPU. If you have
1501 a system with only one CPU, like most personal computers, say N. If
1502 you have a system with more than one CPU, say Y.
1504 If you say N here, the kernel will run on single and multiprocessor
1505 machines, but will use only one CPU of a multiprocessor machine. If
1506 you say Y here, the kernel will run on many, but not all, single
1507 processor machines. On a single processor machine, the kernel will
1508 run faster if you say N here.
1510 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1511 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1512 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1514 If you don't know what to do here, say N.
1517 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1518 depends on EXPERIMENTAL
1519 depends on SMP && !XIP_KERNEL
1522 SMP kernels contain instructions which fail on non-SMP processors.
1523 Enabling this option allows the kernel to modify itself to make
1524 these instructions safe. Disabling it allows about 1K of space
1527 If you don't know what to do here, say Y.
1529 config ARM_CPU_TOPOLOGY
1530 bool "Support cpu topology definition"
1531 depends on SMP && CPU_V7
1534 Support ARM cpu topology definition. The MPIDR register defines
1535 affinity between processors which is then used to describe the cpu
1536 topology of an ARM System.
1539 bool "Multi-core scheduler support"
1540 depends on ARM_CPU_TOPOLOGY
1542 Multi-core scheduler support improves the CPU scheduler's decision
1543 making when dealing with multi-core CPU chips at a cost of slightly
1544 increased overhead in some places. If unsure say N here.
1547 bool "SMT scheduler support"
1548 depends on ARM_CPU_TOPOLOGY
1550 Improves the CPU scheduler's decision making when dealing with
1551 MultiThreading at a cost of slightly increased overhead in some
1552 places. If unsure say N here.
1557 This option enables support for the ARM system coherency unit
1559 config ARM_ARCH_TIMER
1560 bool "Architected timer support"
1563 This option enables support for the ARM architected timer
1569 This options enables support for the ARM timer and watchdog unit
1572 prompt "Memory split"
1575 Select the desired split between kernel and user memory.
1577 If you are not absolutely sure what you are doing, leave this
1581 bool "3G/1G user/kernel split"
1583 bool "2G/2G user/kernel split"
1585 bool "1G/3G user/kernel split"
1590 default 0x40000000 if VMSPLIT_1G
1591 default 0x80000000 if VMSPLIT_2G
1595 int "Maximum number of CPUs (2-32)"
1601 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1602 depends on SMP && HOTPLUG && EXPERIMENTAL
1604 Say Y here to experiment with turning CPUs off and on. CPUs
1605 can be controlled through /sys/devices/system/cpu.
1608 bool "Use local timer interrupts"
1611 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1613 Enable support for local timers on SMP platforms, rather then the
1614 legacy IPI broadcast method. Local timers allows the system
1615 accounting to be spread across the timer interval, preventing a
1616 "thundering herd" at every timer tick.
1620 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1621 default 355 if ARCH_U8500
1622 default 264 if MACH_H4700
1623 default 512 if SOC_OMAP5
1624 default 288 if ARCH_VT8500
1627 Maximum number of GPIOs in the system.
1629 If unsure, leave the default value.
1631 source kernel/Kconfig.preempt
1635 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1636 ARCH_S5PV210 || ARCH_EXYNOS4
1637 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1638 default AT91_TIMER_HZ if ARCH_AT91
1639 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1642 config THUMB2_KERNEL
1643 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1644 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1646 select ARM_ASM_UNIFIED
1649 By enabling this option, the kernel will be compiled in
1650 Thumb-2 mode. A compiler/assembler that understand the unified
1651 ARM-Thumb syntax is needed.
1655 config THUMB2_AVOID_R_ARM_THM_JUMP11
1656 bool "Work around buggy Thumb-2 short branch relocations in gas"
1657 depends on THUMB2_KERNEL && MODULES
1660 Various binutils versions can resolve Thumb-2 branches to
1661 locally-defined, preemptible global symbols as short-range "b.n"
1662 branch instructions.
1664 This is a problem, because there's no guarantee the final
1665 destination of the symbol, or any candidate locations for a
1666 trampoline, are within range of the branch. For this reason, the
1667 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1668 relocation in modules at all, and it makes little sense to add
1671 The symptom is that the kernel fails with an "unsupported
1672 relocation" error when loading some modules.
1674 Until fixed tools are available, passing
1675 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1676 code which hits this problem, at the cost of a bit of extra runtime
1677 stack usage in some cases.
1679 The problem is described in more detail at:
1680 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1682 Only Thumb-2 kernels are affected.
1684 Unless you are sure your tools don't have this problem, say Y.
1686 config ARM_ASM_UNIFIED
1690 bool "Use the ARM EABI to compile the kernel"
1692 This option allows for the kernel to be compiled using the latest
1693 ARM ABI (aka EABI). This is only useful if you are using a user
1694 space environment that is also compiled with EABI.
1696 Since there are major incompatibilities between the legacy ABI and
1697 EABI, especially with regard to structure member alignment, this
1698 option also changes the kernel syscall calling convention to
1699 disambiguate both ABIs and allow for backward compatibility support
1700 (selected with CONFIG_OABI_COMPAT).
1702 To use this you need GCC version 4.0.0 or later.
1705 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1706 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1709 This option preserves the old syscall interface along with the
1710 new (ARM EABI) one. It also provides a compatibility layer to
1711 intercept syscalls that have structure arguments which layout
1712 in memory differs between the legacy ABI and the new ARM EABI
1713 (only for non "thumb" binaries). This option adds a tiny
1714 overhead to all syscalls and produces a slightly larger kernel.
1715 If you know you'll be using only pure EABI user space then you
1716 can say N here. If this option is not selected and you attempt
1717 to execute a legacy ABI binary then the result will be
1718 UNPREDICTABLE (in fact it can be predicted that it won't work
1719 at all). If in doubt say Y.
1721 config ARCH_HAS_HOLES_MEMORYMODEL
1724 config ARCH_SPARSEMEM_ENABLE
1727 config ARCH_SPARSEMEM_DEFAULT
1728 def_bool ARCH_SPARSEMEM_ENABLE
1730 config ARCH_SELECT_MEMORY_MODEL
1731 def_bool ARCH_SPARSEMEM_ENABLE
1733 config HAVE_ARCH_PFN_VALID
1734 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1737 bool "High Memory Support"
1740 The address space of ARM processors is only 4 Gigabytes large
1741 and it has to accommodate user address space, kernel address
1742 space as well as some memory mapped IO. That means that, if you
1743 have a large amount of physical memory and/or IO, not all of the
1744 memory can be "permanently mapped" by the kernel. The physical
1745 memory that is not permanently mapped is called "high memory".
1747 Depending on the selected kernel/user memory split, minimum
1748 vmalloc space and actual amount of RAM, you may not need this
1749 option which should result in a slightly faster kernel.
1754 bool "Allocate 2nd-level pagetables from highmem"
1757 config HW_PERF_EVENTS
1758 bool "Enable hardware performance counter support for perf events"
1759 depends on PERF_EVENTS
1762 Enable hardware performance counter support for perf events. If
1763 disabled, perf events will use software events only.
1767 config FORCE_MAX_ZONEORDER
1768 int "Maximum zone order" if ARCH_SHMOBILE
1769 range 11 64 if ARCH_SHMOBILE
1770 default "12" if SOC_AM33XX
1771 default "9" if SA1111
1774 The kernel memory allocator divides physically contiguous memory
1775 blocks into "zones", where each zone is a power of two number of
1776 pages. This option selects the largest power of two that the kernel
1777 keeps in the memory allocator. If you need to allocate very large
1778 blocks of physically contiguous memory, then you may need to
1779 increase this value.
1781 This config option is actually maximum order plus one. For example,
1782 a value of 11 means that the largest free memory block is 2^10 pages.
1784 config ALIGNMENT_TRAP
1786 depends on CPU_CP15_MMU
1787 default y if !ARCH_EBSA110
1788 select HAVE_PROC_CPU if PROC_FS
1790 ARM processors cannot fetch/store information which is not
1791 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1792 address divisible by 4. On 32-bit ARM processors, these non-aligned
1793 fetch/store instructions will be emulated in software if you say
1794 here, which has a severe performance impact. This is necessary for
1795 correct operation of some network protocols. With an IP-only
1796 configuration it is safe to say N, otherwise say Y.
1798 config UACCESS_WITH_MEMCPY
1799 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1801 default y if CPU_FEROCEON
1803 Implement faster copy_to_user and clear_user methods for CPU
1804 cores where a 8-word STM instruction give significantly higher
1805 memory write throughput than a sequence of individual 32bit stores.
1807 A possible side effect is a slight increase in scheduling latency
1808 between threads sharing the same address space if they invoke
1809 such copy operations with large buffers.
1811 However, if the CPU data cache is using a write-allocate mode,
1812 this option is unlikely to provide any performance gain.
1816 prompt "Enable seccomp to safely compute untrusted bytecode"
1818 This kernel feature is useful for number crunching applications
1819 that may need to compute untrusted bytecode during their
1820 execution. By using pipes or other transports made available to
1821 the process as file descriptors supporting the read/write
1822 syscalls, it's possible to isolate those applications in
1823 their own address space using seccomp. Once seccomp is
1824 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1825 and the task is only allowed to execute a few safe syscalls
1826 defined by each seccomp mode.
1828 config CC_STACKPROTECTOR
1829 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1830 depends on EXPERIMENTAL
1832 This option turns on the -fstack-protector GCC feature. This
1833 feature puts, at the beginning of functions, a canary value on
1834 the stack just before the return address, and validates
1835 the value just before actually returning. Stack based buffer
1836 overflows (that need to overwrite this return address) now also
1837 overwrite the canary, which gets detected and the attack is then
1838 neutralized via a kernel panic.
1839 This feature requires gcc version 4.2 or above.
1846 bool "Xen guest support on ARM (EXPERIMENTAL)"
1847 depends on EXPERIMENTAL && ARM && OF
1849 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1856 bool "Flattened Device Tree support"
1858 select OF_EARLY_FLATTREE
1861 Include support for flattened device tree machine descriptions.
1864 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1867 This is the traditional way of passing data to the kernel at boot
1868 time. If you are solely relying on the flattened device tree (or
1869 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1870 to remove ATAGS support from your kernel binary. If unsure,
1873 config DEPRECATED_PARAM_STRUCT
1874 bool "Provide old way to pass kernel parameters"
1877 This was deprecated in 2001 and announced to live on for 5 years.
1878 Some old boot loaders still use this way.
1880 # Compressed boot loader in ROM. Yes, we really want to ask about
1881 # TEXT and BSS so we preserve their values in the config files.
1882 config ZBOOT_ROM_TEXT
1883 hex "Compressed ROM boot loader base address"
1886 The physical address at which the ROM-able zImage is to be
1887 placed in the target. Platforms which normally make use of
1888 ROM-able zImage formats normally set this to a suitable
1889 value in their defconfig file.
1891 If ZBOOT_ROM is not enabled, this has no effect.
1893 config ZBOOT_ROM_BSS
1894 hex "Compressed ROM boot loader BSS address"
1897 The base address of an area of read/write memory in the target
1898 for the ROM-able zImage which must be available while the
1899 decompressor is running. It must be large enough to hold the
1900 entire decompressed kernel plus an additional 128 KiB.
1901 Platforms which normally make use of ROM-able zImage formats
1902 normally set this to a suitable value in their defconfig file.
1904 If ZBOOT_ROM is not enabled, this has no effect.
1907 bool "Compressed boot loader in ROM/flash"
1908 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1910 Say Y here if you intend to execute your compressed kernel image
1911 (zImage) directly from ROM or flash. If unsure, say N.
1914 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1915 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1916 default ZBOOT_ROM_NONE
1918 Include experimental SD/MMC loading code in the ROM-able zImage.
1919 With this enabled it is possible to write the ROM-able zImage
1920 kernel image to an MMC or SD card and boot the kernel straight
1921 from the reset vector. At reset the processor Mask ROM will load
1922 the first part of the ROM-able zImage which in turn loads the
1923 rest the kernel image to RAM.
1925 config ZBOOT_ROM_NONE
1926 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1928 Do not load image from SD or MMC
1930 config ZBOOT_ROM_MMCIF
1931 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1933 Load image from MMCIF hardware block.
1935 config ZBOOT_ROM_SH_MOBILE_SDHI
1936 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1938 Load image from SDHI hardware block
1942 config ARM_APPENDED_DTB
1943 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1944 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1946 With this option, the boot code will look for a device tree binary
1947 (DTB) appended to zImage
1948 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1950 This is meant as a backward compatibility convenience for those
1951 systems with a bootloader that can't be upgraded to accommodate
1952 the documented boot protocol using a device tree.
1954 Beware that there is very little in terms of protection against
1955 this option being confused by leftover garbage in memory that might
1956 look like a DTB header after a reboot if no actual DTB is appended
1957 to zImage. Do not leave this option active in a production kernel
1958 if you don't intend to always append a DTB. Proper passing of the
1959 location into r2 of a bootloader provided DTB is always preferable
1962 config ARM_ATAG_DTB_COMPAT
1963 bool "Supplement the appended DTB with traditional ATAG information"
1964 depends on ARM_APPENDED_DTB
1966 Some old bootloaders can't be updated to a DTB capable one, yet
1967 they provide ATAGs with memory configuration, the ramdisk address,
1968 the kernel cmdline string, etc. Such information is dynamically
1969 provided by the bootloader and can't always be stored in a static
1970 DTB. To allow a device tree enabled kernel to be used with such
1971 bootloaders, this option allows zImage to extract the information
1972 from the ATAG list and store it at run time into the appended DTB.
1975 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1976 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1978 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1979 bool "Use bootloader kernel arguments if available"
1981 Uses the command-line options passed by the boot loader instead of
1982 the device tree bootargs property. If the boot loader doesn't provide
1983 any, the device tree bootargs property will be used.
1985 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1986 bool "Extend with bootloader kernel arguments"
1988 The command-line arguments provided by the boot loader will be
1989 appended to the the device tree bootargs property.
1994 string "Default kernel command string"
1997 On some architectures (EBSA110 and CATS), there is currently no way
1998 for the boot loader to pass arguments to the kernel. For these
1999 architectures, you should supply some command-line options at build
2000 time by entering them here. As a minimum, you should specify the
2001 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2004 prompt "Kernel command line type" if CMDLINE != ""
2005 default CMDLINE_FROM_BOOTLOADER
2008 config CMDLINE_FROM_BOOTLOADER
2009 bool "Use bootloader kernel arguments if available"
2011 Uses the command-line options passed by the boot loader. If
2012 the boot loader doesn't provide any, the default kernel command
2013 string provided in CMDLINE will be used.
2015 config CMDLINE_EXTEND
2016 bool "Extend bootloader kernel arguments"
2018 The command-line arguments provided by the boot loader will be
2019 appended to the default kernel command string.
2021 config CMDLINE_FORCE
2022 bool "Always use the default kernel command string"
2024 Always use the default kernel command string, even if the boot
2025 loader passes other arguments to the kernel.
2026 This is useful if you cannot or don't want to change the
2027 command-line options your boot loader passes to the kernel.
2031 bool "Kernel Execute-In-Place from ROM"
2032 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2034 Execute-In-Place allows the kernel to run from non-volatile storage
2035 directly addressable by the CPU, such as NOR flash. This saves RAM
2036 space since the text section of the kernel is not loaded from flash
2037 to RAM. Read-write sections, such as the data section and stack,
2038 are still copied to RAM. The XIP kernel is not compressed since
2039 it has to run directly from flash, so it will take more space to
2040 store it. The flash address used to link the kernel object files,
2041 and for storing it, is configuration dependent. Therefore, if you
2042 say Y here, you must know the proper physical address where to
2043 store the kernel image depending on your own flash memory usage.
2045 Also note that the make target becomes "make xipImage" rather than
2046 "make zImage" or "make Image". The final kernel binary to put in
2047 ROM memory will be arch/arm/boot/xipImage.
2051 config XIP_PHYS_ADDR
2052 hex "XIP Kernel Physical Location"
2053 depends on XIP_KERNEL
2054 default "0x00080000"
2056 This is the physical address in your flash memory the kernel will
2057 be linked for and stored to. This address is dependent on your
2061 bool "Kexec system call (EXPERIMENTAL)"
2062 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2064 kexec is a system call that implements the ability to shutdown your
2065 current kernel, and to start another kernel. It is like a reboot
2066 but it is independent of the system firmware. And like a reboot
2067 you can start any kernel with it, not just Linux.
2069 It is an ongoing process to be certain the hardware in a machine
2070 is properly shutdown, so do not be surprised if this code does not
2071 initially work for you. It may help to enable device hotplugging
2075 bool "Export atags in procfs"
2076 depends on ATAGS && KEXEC
2079 Should the atags used to boot the kernel be exported in an "atags"
2080 file in procfs. Useful with kexec.
2083 bool "Build kdump crash kernel (EXPERIMENTAL)"
2084 depends on EXPERIMENTAL
2086 Generate crash dump after being started by kexec. This should
2087 be normally only set in special crash dump kernels which are
2088 loaded in the main kernel with kexec-tools into a specially
2089 reserved region and then later executed after a crash by
2090 kdump/kexec. The crash dump kernel must be compiled to a
2091 memory address not used by the main kernel
2093 For more details see Documentation/kdump/kdump.txt
2095 config AUTO_ZRELADDR
2096 bool "Auto calculation of the decompressed kernel image address"
2097 depends on !ZBOOT_ROM && !ARCH_U300
2099 ZRELADDR is the physical address where the decompressed kernel
2100 image will be placed. If AUTO_ZRELADDR is selected, the address
2101 will be determined at run-time by masking the current IP with
2102 0xf8000000. This assumes the zImage being placed in the first 128MB
2103 from start of memory.
2107 menu "CPU Power Management"
2111 source "drivers/cpufreq/Kconfig"
2114 tristate "CPUfreq driver for i.MX CPUs"
2115 depends on ARCH_MXC && CPU_FREQ
2116 select CPU_FREQ_TABLE
2118 This enables the CPUfreq driver for i.MX CPUs.
2120 config CPU_FREQ_SA1100
2123 config CPU_FREQ_SA1110
2126 config CPU_FREQ_INTEGRATOR
2127 tristate "CPUfreq driver for ARM Integrator CPUs"
2128 depends on ARCH_INTEGRATOR && CPU_FREQ
2131 This enables the CPUfreq driver for ARM Integrator CPUs.
2133 For details, take a look at <file:Documentation/cpu-freq>.
2139 depends on CPU_FREQ && ARCH_PXA && PXA25x
2141 select CPU_FREQ_TABLE
2142 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2147 Internal configuration node for common cpufreq on Samsung SoC
2149 config CPU_FREQ_S3C24XX
2150 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2151 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2154 This enables the CPUfreq driver for the Samsung S3C24XX family
2157 For details, take a look at <file:Documentation/cpu-freq>.
2161 config CPU_FREQ_S3C24XX_PLL
2162 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2163 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2165 Compile in support for changing the PLL frequency from the
2166 S3C24XX series CPUfreq driver. The PLL takes time to settle
2167 after a frequency change, so by default it is not enabled.
2169 This also means that the PLL tables for the selected CPU(s) will
2170 be built which may increase the size of the kernel image.
2172 config CPU_FREQ_S3C24XX_DEBUG
2173 bool "Debug CPUfreq Samsung driver core"
2174 depends on CPU_FREQ_S3C24XX
2176 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2178 config CPU_FREQ_S3C24XX_IODEBUG
2179 bool "Debug CPUfreq Samsung driver IO timing"
2180 depends on CPU_FREQ_S3C24XX
2182 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2184 config CPU_FREQ_S3C24XX_DEBUGFS
2185 bool "Export debugfs for CPUFreq"
2186 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2188 Export status information via debugfs.
2192 source "drivers/cpuidle/Kconfig"
2196 menu "Floating point emulation"
2198 comment "At least one emulation must be selected"
2201 bool "NWFPE math emulation"
2202 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2204 Say Y to include the NWFPE floating point emulator in the kernel.
2205 This is necessary to run most binaries. Linux does not currently
2206 support floating point hardware so you need to say Y here even if
2207 your machine has an FPA or floating point co-processor podule.
2209 You may say N here if you are going to load the Acorn FPEmulator
2210 early in the bootup.
2213 bool "Support extended precision"
2214 depends on FPE_NWFPE
2216 Say Y to include 80-bit support in the kernel floating-point
2217 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2218 Note that gcc does not generate 80-bit operations by default,
2219 so in most cases this option only enlarges the size of the
2220 floating point emulator without any good reason.
2222 You almost surely want to say N here.
2225 bool "FastFPE math emulation (EXPERIMENTAL)"
2226 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2228 Say Y here to include the FAST floating point emulator in the kernel.
2229 This is an experimental much faster emulator which now also has full
2230 precision for the mantissa. It does not support any exceptions.
2231 It is very simple, and approximately 3-6 times faster than NWFPE.
2233 It should be sufficient for most programs. It may be not suitable
2234 for scientific calculations, but you have to check this for yourself.
2235 If you do not feel you need a faster FP emulation you should better
2239 bool "VFP-format floating point maths"
2240 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2242 Say Y to include VFP support code in the kernel. This is needed
2243 if your hardware includes a VFP unit.
2245 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2246 release notes and additional status information.
2248 Say N if your target does not have VFP hardware.
2256 bool "Advanced SIMD (NEON) Extension support"
2257 depends on VFPv3 && CPU_V7
2259 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2264 menu "Userspace binary formats"
2266 source "fs/Kconfig.binfmt"
2269 tristate "RISC OS personality"
2272 Say Y here to include the kernel code necessary if you want to run
2273 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2274 experimental; if this sounds frightening, say N and sleep in peace.
2275 You can also say M here to compile this support as a module (which
2276 will be called arthur).
2280 menu "Power management options"
2282 source "kernel/power/Kconfig"
2284 config ARCH_SUSPEND_POSSIBLE
2285 depends on !ARCH_S5PC100
2286 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2287 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2290 config ARM_CPU_SUSPEND
2295 source "net/Kconfig"
2297 source "drivers/Kconfig"
2301 source "arch/arm/Kconfig.debug"
2303 source "security/Kconfig"
2305 source "crypto/Kconfig"
2307 source "lib/Kconfig"