4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_DEVMEM_IS_ALLOWED
6 select ARCH_HAS_ELF_RANDOMIZE
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_HAVE_CUSTOM_GPIO_H
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_MIGHT_HAVE_PC_PARPORT
11 select ARCH_SUPPORTS_ATOMIC_RMW
12 select ARCH_USE_BUILTIN_BSWAP
13 select ARCH_USE_CMPXCHG_LOCKREF
14 select ARCH_WANT_IPC_PARSE_VERSION
15 select BUILDTIME_EXTABLE_SORT if MMU
16 select CLONE_BACKWARDS
17 select CPU_PM if (SUSPEND || CPU_IDLE)
18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
20 select EDAC_ATOMIC_SCRUB
21 select GENERIC_ALLOCATOR
22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
24 select GENERIC_EARLY_IOREMAP
25 select GENERIC_IDLE_POLL_SETUP
26 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW
28 select GENERIC_IRQ_SHOW_LEVEL
29 select GENERIC_PCI_IOMAP
30 select GENERIC_SCHED_CLOCK
31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
34 select HANDLE_DOMAIN_IRQ
35 select HARDIRQS_SW_RESEND
36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
38 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
39 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
40 select HAVE_ARCH_MMAP_RND_BITS if MMU
41 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
42 select HAVE_ARCH_TRACEHOOK
43 select HAVE_ARM_SMCCC if CPU_V7
45 select HAVE_CC_STACKPROTECTOR
46 select HAVE_CONTEXT_TRACKING
47 select HAVE_C_RECORDMCOUNT
48 select HAVE_DEBUG_KMEMLEAK
49 select HAVE_DMA_API_DEBUG
50 select HAVE_DMA_CONTIGUOUS if MMU
51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
53 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
54 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
55 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
56 select HAVE_GENERIC_DMA_COHERENT
57 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
58 select HAVE_IDE if PCI || ISA || PCMCIA
59 select HAVE_IRQ_TIME_ACCOUNTING
60 select HAVE_KERNEL_GZIP
61 select HAVE_KERNEL_LZ4
62 select HAVE_KERNEL_LZMA
63 select HAVE_KERNEL_LZO
65 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
66 select HAVE_KRETPROBES if (HAVE_KPROBES)
68 select HAVE_MOD_ARCH_SPECIFIC
69 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
70 select HAVE_OPTPROBES if !THUMB2_KERNEL
71 select HAVE_PERF_EVENTS
73 select HAVE_PERF_USER_STACK_DUMP
74 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
75 select HAVE_REGS_AND_STACK_ACCESS_API
76 select HAVE_SYSCALL_TRACEPOINTS
78 select HAVE_VIRT_CPU_ACCOUNTING_GEN
79 select IRQ_FORCED_THREADING
80 select MODULES_USE_ELF_REL
82 select OF_EARLY_FLATTREE if OF
83 select OF_RESERVED_MEM if OF
85 select OLD_SIGSUSPEND3
86 select PERF_USE_VMALLOC
88 select SYS_SUPPORTS_APM_EMULATION
89 # Above selects are sorted alphabetically; please add new ones
90 # according to that. Thanks.
92 The ARM series is a line of low-power-consumption RISC chip designs
93 licensed by ARM Ltd and targeted at embedded applications and
94 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
95 manufactured, but legacy ARM-based PC hardware remains popular in
96 Europe. There is an ARM Linux project with a web page at
97 <http://www.arm.linux.org.uk/>.
99 config ARM_HAS_SG_CHAIN
100 select ARCH_HAS_SG_CHAIN
103 config NEED_SG_DMA_LENGTH
106 config ARM_DMA_USE_IOMMU
108 select ARM_HAS_SG_CHAIN
109 select NEED_SG_DMA_LENGTH
113 config ARM_DMA_IOMMU_ALIGNMENT
114 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
118 DMA mapping framework by default aligns all buffers to the smallest
119 PAGE_SIZE order which is greater than or equal to the requested buffer
120 size. This works well for buffers up to a few hundreds kilobytes, but
121 for larger buffers it just a waste of address space. Drivers which has
122 relatively small addressing window (like 64Mib) might run out of
123 virtual space with just a few allocations.
125 With this parameter you can specify the maximum PAGE_SIZE order for
126 DMA IOMMU buffers. Larger buffers will be aligned only to this
127 specified order. The order is expressed as a power of two multiplied
132 config MIGHT_HAVE_PCI
135 config SYS_SUPPORTS_APM_EMULATION
140 select GENERIC_ALLOCATOR
151 The Extended Industry Standard Architecture (EISA) bus was
152 developed as an open alternative to the IBM MicroChannel bus.
154 The EISA bus provided some of the features of the IBM MicroChannel
155 bus while maintaining backward compatibility with cards made for
156 the older ISA bus. The EISA bus saw limited use between 1988 and
157 1995 when it was made obsolete by the PCI bus.
159 Say Y here if you are building a kernel for an EISA-based machine.
166 config STACKTRACE_SUPPORT
170 config LOCKDEP_SUPPORT
174 config TRACE_IRQFLAGS_SUPPORT
178 config RWSEM_XCHGADD_ALGORITHM
182 config ARCH_HAS_ILOG2_U32
185 config ARCH_HAS_ILOG2_U64
188 config ARCH_HAS_BANDGAP
191 config FIX_EARLYCON_MEM
194 config GENERIC_HWEIGHT
198 config GENERIC_CALIBRATE_DELAY
202 config ARCH_MAY_HAVE_PC_FDC
208 config NEED_DMA_MAP_STATE
211 config ARCH_SUPPORTS_UPROBES
214 config ARCH_HAS_DMA_SET_COHERENT_MASK
217 config GENERIC_ISA_DMA
223 config NEED_RET_TO_USER
231 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
232 default DRAM_BASE if REMAP_VECTORS_TO_RAM
235 The base address of exception vectors. This must be two pages
238 config ARM_PATCH_PHYS_VIRT
239 bool "Patch physical to virtual translations at runtime" if EMBEDDED
241 depends on !XIP_KERNEL && MMU
243 Patch phys-to-virt and virt-to-phys translation functions at
244 boot and module load time according to the position of the
245 kernel in system memory.
247 This can only be used with non-XIP MMU kernels where the base
248 of physical memory is at a 16MB boundary.
250 Only disable this option if you know that you do not require
251 this feature (eg, building a kernel for a single machine) and
252 you need to shrink the kernel to the minimal size.
254 config NEED_MACH_IO_H
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
261 config NEED_MACH_MEMORY_H
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT
271 default DRAM_BASE if !MMU
272 default 0x00000000 if ARCH_EBSA110 || \
277 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
278 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
279 default 0x20000000 if ARCH_S5PV210
280 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
281 default 0xc0000000 if ARCH_SA1100
283 Please provide the physical address corresponding to the
284 location of main memory in your system.
290 config PGTABLE_LEVELS
292 default 3 if ARM_LPAE
295 source "init/Kconfig"
297 source "kernel/Kconfig.freezer"
302 bool "MMU-based Paged Memory Management Support"
305 Select if you want MMU-based virtualised addressing space
306 support by paged memory management. If unsure, say 'Y'.
308 config ARCH_MMAP_RND_BITS_MIN
311 config ARCH_MMAP_RND_BITS_MAX
312 default 14 if PAGE_OFFSET=0x40000000
313 default 15 if PAGE_OFFSET=0x80000000
317 # The "ARM system type" choice list is ordered alphabetically by option
318 # text. Please add new entries in the option alphabetic order.
321 prompt "ARM system type"
322 default ARM_SINGLE_ARMV7M if !MMU
323 default ARCH_MULTIPLATFORM if MMU
325 config ARCH_MULTIPLATFORM
326 bool "Allow multiple platforms to be selected"
328 select ARCH_WANT_OPTIONAL_GPIOLIB
329 select ARM_HAS_SG_CHAIN
330 select ARM_PATCH_PHYS_VIRT
334 select GENERIC_CLOCKEVENTS
335 select MIGHT_HAVE_PCI
336 select MULTI_IRQ_HANDLER
340 config ARM_SINGLE_ARMV7M
341 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
349 select GENERIC_CLOCKEVENTS
356 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
357 select ARCH_REQUIRE_GPIOLIB
362 select GENERIC_CLOCKEVENTS
366 Support for Cirrus Logic 711x/721x/731x based boards.
369 bool "Cortina Systems Gemini"
370 select ARCH_REQUIRE_GPIOLIB
373 select GENERIC_CLOCKEVENTS
375 Support for the Cortina Systems Gemini family SoCs
379 select ARCH_USES_GETTIMEOFFSET
382 select NEED_MACH_IO_H
383 select NEED_MACH_MEMORY_H
386 This is an evaluation board for the StrongARM processor available
387 from Digital. It has limited hardware on-board, including an
388 Ethernet interface, two PCMCIA sockets, two serial ports and a
393 select ARCH_HAS_HOLES_MEMORYMODEL
394 select ARCH_REQUIRE_GPIOLIB
396 select ARM_PATCH_PHYS_VIRT
402 select GENERIC_CLOCKEVENTS
404 This enables support for the Cirrus EP93xx series of CPUs.
406 config ARCH_FOOTBRIDGE
410 select GENERIC_CLOCKEVENTS
412 select NEED_MACH_IO_H if !MMU
413 select NEED_MACH_MEMORY_H
415 Support for systems based on the DC21285 companion chip
416 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
419 bool "Hilscher NetX based"
423 select GENERIC_CLOCKEVENTS
425 This enables support for systems based on the Hilscher NetX Soc
431 select NEED_MACH_MEMORY_H
432 select NEED_RET_TO_USER
438 Support for Intel's IOP13XX (XScale) family of processors.
443 select ARCH_REQUIRE_GPIOLIB
446 select NEED_RET_TO_USER
450 Support for Intel's 80219 and IOP32X (XScale) family of
456 select ARCH_REQUIRE_GPIOLIB
459 select NEED_RET_TO_USER
463 Support for Intel's IOP33X (XScale) family of processors.
468 select ARCH_HAS_DMA_SET_COHERENT_MASK
469 select ARCH_REQUIRE_GPIOLIB
470 select ARCH_SUPPORTS_BIG_ENDIAN
473 select DMABOUNCE if PCI
474 select GENERIC_CLOCKEVENTS
475 select MIGHT_HAVE_PCI
476 select NEED_MACH_IO_H
477 select USB_EHCI_BIG_ENDIAN_DESC
478 select USB_EHCI_BIG_ENDIAN_MMIO
480 Support for Intel's IXP4XX (XScale) family of processors.
484 select ARCH_REQUIRE_GPIOLIB
486 select GENERIC_CLOCKEVENTS
487 select MIGHT_HAVE_PCI
488 select MULTI_IRQ_HANDLER
492 select PLAT_ORION_LEGACY
494 select PM_GENERIC_DOMAINS if PM
496 Support for the Marvell Dove SoC 88AP510
499 bool "Micrel/Kendin KS8695"
500 select ARCH_REQUIRE_GPIOLIB
503 select GENERIC_CLOCKEVENTS
504 select NEED_MACH_MEMORY_H
506 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
507 System-on-Chip devices.
510 bool "Nuvoton W90X900 CPU"
511 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
517 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
518 At present, the w90x900 has been renamed nuc900, regarding
519 the ARM series product line, you can login the following
520 link address to know more.
522 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
523 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
527 select ARCH_REQUIRE_GPIOLIB
530 select CLKSRC_LPC32XX
533 select GENERIC_CLOCKEVENTS
536 Support for the NXP LPC32XX family of processors
539 bool "PXA2xx/PXA3xx-based"
542 select ARCH_REQUIRE_GPIOLIB
543 select ARM_CPU_SUSPEND if PM
550 select CPU_XSCALE if !CPU_XSC3
551 select GENERIC_CLOCKEVENTS
555 select MULTI_IRQ_HANDLER
559 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
565 select ARCH_MAY_HAVE_PC_FDC
566 select ARCH_SPARSEMEM_ENABLE
567 select ARCH_USES_GETTIMEOFFSET
571 select HAVE_PATA_PLATFORM
573 select NEED_MACH_IO_H
574 select NEED_MACH_MEMORY_H
577 On the Acorn Risc-PC, Linux can support the internal IDE disk and
578 CD-ROM interface, serial and parallel port, and the floppy drive.
583 select ARCH_REQUIRE_GPIOLIB
584 select ARCH_SPARSEMEM_ENABLE
588 select CLKSRC_OF if OF
591 select GENERIC_CLOCKEVENTS
595 select MULTI_IRQ_HANDLER
596 select NEED_MACH_MEMORY_H
599 Support for StrongARM 11x0 based boards.
602 bool "Samsung S3C24XX SoCs"
603 select ARCH_REQUIRE_GPIOLIB
606 select CLKSRC_SAMSUNG_PWM
607 select GENERIC_CLOCKEVENTS
609 select HAVE_S3C2410_I2C if I2C
610 select HAVE_S3C2410_WATCHDOG if WATCHDOG
611 select HAVE_S3C_RTC if RTC_CLASS
612 select MULTI_IRQ_HANDLER
613 select NEED_MACH_IO_H
616 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
617 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
618 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
619 Samsung SMDK2410 development board (and derivatives).
623 select ARCH_HAS_HOLES_MEMORYMODEL
624 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_ALLOCATOR
628 select GENERIC_CLOCKEVENTS
629 select GENERIC_IRQ_CHIP
634 Support for TI's DaVinci platform.
639 select ARCH_HAS_HOLES_MEMORYMODEL
641 select ARCH_REQUIRE_GPIOLIB
644 select GENERIC_CLOCKEVENTS
645 select GENERIC_IRQ_CHIP
648 select MULTI_IRQ_HANDLER
649 select NEED_MACH_IO_H if PCCARD
650 select NEED_MACH_MEMORY_H
653 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
657 menu "Multiple platform selection"
658 depends on ARCH_MULTIPLATFORM
660 comment "CPU Core family selection"
663 bool "ARMv4 based platforms (FA526)"
664 depends on !ARCH_MULTI_V6_V7
665 select ARCH_MULTI_V4_V5
668 config ARCH_MULTI_V4T
669 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
670 depends on !ARCH_MULTI_V6_V7
671 select ARCH_MULTI_V4_V5
672 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
673 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
674 CPU_ARM925T || CPU_ARM940T)
677 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
678 depends on !ARCH_MULTI_V6_V7
679 select ARCH_MULTI_V4_V5
680 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
681 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
682 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
684 config ARCH_MULTI_V4_V5
688 bool "ARMv6 based platforms (ARM11)"
689 select ARCH_MULTI_V6_V7
693 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
695 select ARCH_MULTI_V6_V7
699 config ARCH_MULTI_V6_V7
701 select MIGHT_HAVE_CACHE_L2X0
703 config ARCH_MULTI_CPU_AUTO
704 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
710 bool "Dummy Virtual Machine"
711 depends on ARCH_MULTI_V7
714 select ARM_GIC_V2M if PCI_MSI
717 select HAVE_ARM_ARCH_TIMER
720 # This is sorted alphabetically by mach-* pathname. However, plat-*
721 # Kconfigs may be included either alphabetically (according to the
722 # plat- suffix) or along side the corresponding mach-* source.
724 source "arch/arm/mach-mvebu/Kconfig"
726 source "arch/arm/mach-alpine/Kconfig"
728 source "arch/arm/mach-artpec/Kconfig"
730 source "arch/arm/mach-asm9260/Kconfig"
732 source "arch/arm/mach-at91/Kconfig"
734 source "arch/arm/mach-axxia/Kconfig"
736 source "arch/arm/mach-bcm/Kconfig"
738 source "arch/arm/mach-berlin/Kconfig"
740 source "arch/arm/mach-clps711x/Kconfig"
742 source "arch/arm/mach-cns3xxx/Kconfig"
744 source "arch/arm/mach-davinci/Kconfig"
746 source "arch/arm/mach-digicolor/Kconfig"
748 source "arch/arm/mach-dove/Kconfig"
750 source "arch/arm/mach-ep93xx/Kconfig"
752 source "arch/arm/mach-footbridge/Kconfig"
754 source "arch/arm/mach-gemini/Kconfig"
756 source "arch/arm/mach-highbank/Kconfig"
758 source "arch/arm/mach-hisi/Kconfig"
760 source "arch/arm/mach-integrator/Kconfig"
762 source "arch/arm/mach-iop32x/Kconfig"
764 source "arch/arm/mach-iop33x/Kconfig"
766 source "arch/arm/mach-iop13xx/Kconfig"
768 source "arch/arm/mach-ixp4xx/Kconfig"
770 source "arch/arm/mach-keystone/Kconfig"
772 source "arch/arm/mach-ks8695/Kconfig"
774 source "arch/arm/mach-meson/Kconfig"
776 source "arch/arm/mach-moxart/Kconfig"
778 source "arch/arm/mach-mv78xx0/Kconfig"
780 source "arch/arm/mach-imx/Kconfig"
782 source "arch/arm/mach-mediatek/Kconfig"
784 source "arch/arm/mach-mxs/Kconfig"
786 source "arch/arm/mach-netx/Kconfig"
788 source "arch/arm/mach-nomadik/Kconfig"
790 source "arch/arm/mach-nspire/Kconfig"
792 source "arch/arm/plat-omap/Kconfig"
794 source "arch/arm/mach-omap1/Kconfig"
796 source "arch/arm/mach-omap2/Kconfig"
798 source "arch/arm/mach-orion5x/Kconfig"
800 source "arch/arm/mach-picoxcell/Kconfig"
802 source "arch/arm/mach-pxa/Kconfig"
803 source "arch/arm/plat-pxa/Kconfig"
805 source "arch/arm/mach-mmp/Kconfig"
807 source "arch/arm/mach-oxnas/Kconfig"
809 source "arch/arm/mach-qcom/Kconfig"
811 source "arch/arm/mach-realview/Kconfig"
813 source "arch/arm/mach-rockchip/Kconfig"
815 source "arch/arm/mach-sa1100/Kconfig"
817 source "arch/arm/mach-socfpga/Kconfig"
819 source "arch/arm/mach-spear/Kconfig"
821 source "arch/arm/mach-sti/Kconfig"
823 source "arch/arm/mach-s3c24xx/Kconfig"
825 source "arch/arm/mach-s3c64xx/Kconfig"
827 source "arch/arm/mach-s5pv210/Kconfig"
829 source "arch/arm/mach-exynos/Kconfig"
830 source "arch/arm/plat-samsung/Kconfig"
832 source "arch/arm/mach-shmobile/Kconfig"
834 source "arch/arm/mach-sunxi/Kconfig"
836 source "arch/arm/mach-prima2/Kconfig"
838 source "arch/arm/mach-tango/Kconfig"
840 source "arch/arm/mach-tegra/Kconfig"
842 source "arch/arm/mach-u300/Kconfig"
844 source "arch/arm/mach-uniphier/Kconfig"
846 source "arch/arm/mach-ux500/Kconfig"
848 source "arch/arm/mach-versatile/Kconfig"
850 source "arch/arm/mach-vexpress/Kconfig"
851 source "arch/arm/plat-versatile/Kconfig"
853 source "arch/arm/mach-vt8500/Kconfig"
855 source "arch/arm/mach-w90x900/Kconfig"
857 source "arch/arm/mach-zx/Kconfig"
859 source "arch/arm/mach-zynq/Kconfig"
861 # ARMv7-M architecture
863 bool "Energy Micro efm32"
864 depends on ARM_SINGLE_ARMV7M
865 select ARCH_REQUIRE_GPIOLIB
867 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
871 bool "NXP LPC18xx/LPC43xx"
872 depends on ARM_SINGLE_ARMV7M
873 select ARCH_HAS_RESET_CONTROLLER
875 select CLKSRC_LPC32XX
878 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
879 high performance microcontrollers.
882 bool "STMicrolectronics STM32"
883 depends on ARM_SINGLE_ARMV7M
884 select ARCH_HAS_RESET_CONTROLLER
885 select ARMV7M_SYSTICK
888 select RESET_CONTROLLER
890 Support for STMicroelectronics STM32 processors.
892 config MACH_STM32F429
893 bool "STMicrolectronics STM32F429"
894 depends on ARCH_STM32
898 bool "ARM MPS2 paltform"
899 depends on ARM_SINGLE_ARMV7M
903 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
904 with a range of available cores like Cortex-M3/M4/M7.
906 Please, note that depends which Application Note is used memory map
907 for the platform may vary, so adjustment of RAM base might be needed.
909 # Definitions to make life easier
915 select GENERIC_CLOCKEVENTS
921 select GENERIC_IRQ_CHIP
924 config PLAT_ORION_LEGACY
931 config PLAT_VERSATILE
934 source "arch/arm/firmware/Kconfig"
936 source arch/arm/mm/Kconfig
939 bool "Enable iWMMXt support"
940 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
941 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
943 Enable support for iWMMXt context switching at run time if
944 running on a CPU that supports it.
946 config MULTI_IRQ_HANDLER
949 Allow each machine to specify it's own IRQ handler at run time.
952 source "arch/arm/Kconfig-nommu"
955 config PJ4B_ERRATA_4742
956 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
957 depends on CPU_PJ4B && MACH_ARMADA_370
960 When coming out of either a Wait for Interrupt (WFI) or a Wait for
961 Event (WFE) IDLE states, a specific timing sensitivity exists between
962 the retiring WFI/WFE instructions and the newly issued subsequent
963 instructions. This sensitivity can result in a CPU hang scenario.
965 The software must insert either a Data Synchronization Barrier (DSB)
966 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
969 config ARM_ERRATA_326103
970 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
973 Executing a SWP instruction to read-only memory does not set bit 11
974 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
975 treat the access as a read, preventing a COW from occurring and
976 causing the faulting task to livelock.
978 config ARM_ERRATA_411920
979 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
980 depends on CPU_V6 || CPU_V6K
982 Invalidation of the Instruction Cache operation can
983 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
984 It does not affect the MPCore. This option enables the ARM Ltd.
985 recommended workaround.
987 config ARM_ERRATA_430973
988 bool "ARM errata: Stale prediction on replaced interworking branch"
991 This option enables the workaround for the 430973 Cortex-A8
992 r1p* erratum. If a code sequence containing an ARM/Thumb
993 interworking branch is replaced with another code sequence at the
994 same virtual address, whether due to self-modifying code or virtual
995 to physical address re-mapping, Cortex-A8 does not recover from the
996 stale interworking branch prediction. This results in Cortex-A8
997 executing the new code sequence in the incorrect ARM or Thumb state.
998 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
999 and also flushes the branch target cache at every context switch.
1000 Note that setting specific bits in the ACTLR register may not be
1001 available in non-secure mode.
1003 config ARM_ERRATA_458693
1004 bool "ARM errata: Processor deadlock when a false hazard is created"
1006 depends on !ARCH_MULTIPLATFORM
1008 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1009 erratum. For very specific sequences of memory operations, it is
1010 possible for a hazard condition intended for a cache line to instead
1011 be incorrectly associated with a different cache line. This false
1012 hazard might then cause a processor deadlock. The workaround enables
1013 the L1 caching of the NEON accesses and disables the PLD instruction
1014 in the ACTLR register. Note that setting specific bits in the ACTLR
1015 register may not be available in non-secure mode.
1017 config ARM_ERRATA_460075
1018 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1020 depends on !ARCH_MULTIPLATFORM
1022 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1023 erratum. Any asynchronous access to the L2 cache may encounter a
1024 situation in which recent store transactions to the L2 cache are lost
1025 and overwritten with stale memory contents from external memory. The
1026 workaround disables the write-allocate mode for the L2 cache via the
1027 ACTLR register. Note that setting specific bits in the ACTLR register
1028 may not be available in non-secure mode.
1030 config ARM_ERRATA_742230
1031 bool "ARM errata: DMB operation may be faulty"
1032 depends on CPU_V7 && SMP
1033 depends on !ARCH_MULTIPLATFORM
1035 This option enables the workaround for the 742230 Cortex-A9
1036 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1037 between two write operations may not ensure the correct visibility
1038 ordering of the two writes. This workaround sets a specific bit in
1039 the diagnostic register of the Cortex-A9 which causes the DMB
1040 instruction to behave as a DSB, ensuring the correct behaviour of
1043 config ARM_ERRATA_742231
1044 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1045 depends on CPU_V7 && SMP
1046 depends on !ARCH_MULTIPLATFORM
1048 This option enables the workaround for the 742231 Cortex-A9
1049 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1050 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1051 accessing some data located in the same cache line, may get corrupted
1052 data due to bad handling of the address hazard when the line gets
1053 replaced from one of the CPUs at the same time as another CPU is
1054 accessing it. This workaround sets specific bits in the diagnostic
1055 register of the Cortex-A9 which reduces the linefill issuing
1056 capabilities of the processor.
1058 config ARM_ERRATA_643719
1059 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1060 depends on CPU_V7 && SMP
1063 This option enables the workaround for the 643719 Cortex-A9 (prior to
1064 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1065 register returns zero when it should return one. The workaround
1066 corrects this value, ensuring cache maintenance operations which use
1067 it behave as intended and avoiding data corruption.
1069 config ARM_ERRATA_720789
1070 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1073 This option enables the workaround for the 720789 Cortex-A9 (prior to
1074 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1075 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1076 As a consequence of this erratum, some TLB entries which should be
1077 invalidated are not, resulting in an incoherency in the system page
1078 tables. The workaround changes the TLB flushing routines to invalidate
1079 entries regardless of the ASID.
1081 config ARM_ERRATA_743622
1082 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1084 depends on !ARCH_MULTIPLATFORM
1086 This option enables the workaround for the 743622 Cortex-A9
1087 (r2p*) erratum. Under very rare conditions, a faulty
1088 optimisation in the Cortex-A9 Store Buffer may lead to data
1089 corruption. This workaround sets a specific bit in the diagnostic
1090 register of the Cortex-A9 which disables the Store Buffer
1091 optimisation, preventing the defect from occurring. This has no
1092 visible impact on the overall performance or power consumption of the
1095 config ARM_ERRATA_751472
1096 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1098 depends on !ARCH_MULTIPLATFORM
1100 This option enables the workaround for the 751472 Cortex-A9 (prior
1101 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1102 completion of a following broadcasted operation if the second
1103 operation is received by a CPU before the ICIALLUIS has completed,
1104 potentially leading to corrupted entries in the cache or TLB.
1106 config ARM_ERRATA_754322
1107 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1110 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1111 r3p*) erratum. A speculative memory access may cause a page table walk
1112 which starts prior to an ASID switch but completes afterwards. This
1113 can populate the micro-TLB with a stale entry which may be hit with
1114 the new ASID. This workaround places two dsb instructions in the mm
1115 switching code so that no page table walks can cross the ASID switch.
1117 config ARM_ERRATA_754327
1118 bool "ARM errata: no automatic Store Buffer drain"
1119 depends on CPU_V7 && SMP
1121 This option enables the workaround for the 754327 Cortex-A9 (prior to
1122 r2p0) erratum. The Store Buffer does not have any automatic draining
1123 mechanism and therefore a livelock may occur if an external agent
1124 continuously polls a memory location waiting to observe an update.
1125 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1126 written polling loops from denying visibility of updates to memory.
1128 config ARM_ERRATA_364296
1129 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1132 This options enables the workaround for the 364296 ARM1136
1133 r0p2 erratum (possible cache data corruption with
1134 hit-under-miss enabled). It sets the undocumented bit 31 in
1135 the auxiliary control register and the FI bit in the control
1136 register, thus disabling hit-under-miss without putting the
1137 processor into full low interrupt latency mode. ARM11MPCore
1140 config ARM_ERRATA_764369
1141 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1142 depends on CPU_V7 && SMP
1144 This option enables the workaround for erratum 764369
1145 affecting Cortex-A9 MPCore with two or more processors (all
1146 current revisions). Under certain timing circumstances, a data
1147 cache line maintenance operation by MVA targeting an Inner
1148 Shareable memory region may fail to proceed up to either the
1149 Point of Coherency or to the Point of Unification of the
1150 system. This workaround adds a DSB instruction before the
1151 relevant cache maintenance functions and sets a specific bit
1152 in the diagnostic control register of the SCU.
1154 config ARM_ERRATA_775420
1155 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1158 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1159 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1160 operation aborts with MMU exception, it might cause the processor
1161 to deadlock. This workaround puts DSB before executing ISB if
1162 an abort may occur on cache maintenance.
1164 config ARM_ERRATA_798181
1165 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1166 depends on CPU_V7 && SMP
1168 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1169 adequately shooting down all use of the old entries. This
1170 option enables the Linux kernel workaround for this erratum
1171 which sends an IPI to the CPUs that are running the same ASID
1172 as the one being invalidated.
1174 config ARM_ERRATA_773022
1175 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1178 This option enables the workaround for the 773022 Cortex-A15
1179 (up to r0p4) erratum. In certain rare sequences of code, the
1180 loop buffer may deliver incorrect instructions. This
1181 workaround disables the loop buffer to avoid the erratum.
1185 source "arch/arm/common/Kconfig"
1192 Find out whether you have ISA slots on your motherboard. ISA is the
1193 name of a bus system, i.e. the way the CPU talks to the other stuff
1194 inside your box. Other bus systems are PCI, EISA, MicroChannel
1195 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1196 newer boards don't support it. If you have ISA, say Y, otherwise N.
1198 # Select ISA DMA controller support
1203 # Select ISA DMA interface
1208 bool "PCI support" if MIGHT_HAVE_PCI
1210 Find out whether you have a PCI motherboard. PCI is the name of a
1211 bus system, i.e. the way the CPU talks to the other stuff inside
1212 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1213 VESA. If you have PCI, say Y, otherwise N.
1219 config PCI_DOMAINS_GENERIC
1220 def_bool PCI_DOMAINS
1222 config PCI_NANOENGINE
1223 bool "BSE nanoEngine PCI support"
1224 depends on SA1100_NANOENGINE
1226 Enable PCI on the BSE nanoEngine board.
1231 config PCI_HOST_ITE8152
1233 depends on PCI && MACH_ARMCORE
1237 source "drivers/pci/Kconfig"
1239 source "drivers/pcmcia/Kconfig"
1243 menu "Kernel Features"
1248 This option should be selected by machines which have an SMP-
1251 The only effect of this option is to make the SMP-related
1252 options available to the user for configuration.
1255 bool "Symmetric Multi-Processing"
1256 depends on CPU_V6K || CPU_V7
1257 depends on GENERIC_CLOCKEVENTS
1259 depends on MMU || ARM_MPU
1262 This enables support for systems with more than one CPU. If you have
1263 a system with only one CPU, say N. If you have a system with more
1264 than one CPU, say Y.
1266 If you say N here, the kernel will run on uni- and multiprocessor
1267 machines, but will use only one CPU of a multiprocessor machine. If
1268 you say Y here, the kernel will run on many, but not all,
1269 uniprocessor machines. On a uniprocessor machine, the kernel
1270 will run faster if you say N here.
1272 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1273 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1274 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1276 If you don't know what to do here, say N.
1279 bool "Allow booting SMP kernel on uniprocessor systems"
1280 depends on SMP && !XIP_KERNEL && MMU
1283 SMP kernels contain instructions which fail on non-SMP processors.
1284 Enabling this option allows the kernel to modify itself to make
1285 these instructions safe. Disabling it allows about 1K of space
1288 If you don't know what to do here, say Y.
1290 config ARM_CPU_TOPOLOGY
1291 bool "Support cpu topology definition"
1292 depends on SMP && CPU_V7
1295 Support ARM cpu topology definition. The MPIDR register defines
1296 affinity between processors which is then used to describe the cpu
1297 topology of an ARM System.
1300 bool "Multi-core scheduler support"
1301 depends on ARM_CPU_TOPOLOGY
1303 Multi-core scheduler support improves the CPU scheduler's decision
1304 making when dealing with multi-core CPU chips at a cost of slightly
1305 increased overhead in some places. If unsure say N here.
1308 bool "SMT scheduler support"
1309 depends on ARM_CPU_TOPOLOGY
1311 Improves the CPU scheduler's decision making when dealing with
1312 MultiThreading at a cost of slightly increased overhead in some
1313 places. If unsure say N here.
1318 This option enables support for the ARM system coherency unit
1320 config HAVE_ARM_ARCH_TIMER
1321 bool "Architected timer support"
1323 select ARM_ARCH_TIMER
1324 select GENERIC_CLOCKEVENTS
1326 This option enables support for the ARM architected timer
1330 select CLKSRC_OF if OF
1332 This options enables support for the ARM timer and watchdog unit
1335 bool "Multi-Cluster Power Management"
1336 depends on CPU_V7 && SMP
1338 This option provides the common power management infrastructure
1339 for (multi-)cluster based systems, such as big.LITTLE based
1342 config MCPM_QUAD_CLUSTER
1346 To avoid wasting resources unnecessarily, MCPM only supports up
1347 to 2 clusters by default.
1348 Platforms with 3 or 4 clusters that use MCPM must select this
1349 option to allow the additional clusters to be managed.
1352 bool "big.LITTLE support (Experimental)"
1353 depends on CPU_V7 && SMP
1356 This option enables support selections for the big.LITTLE
1357 system architecture.
1360 bool "big.LITTLE switcher support"
1361 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1364 The big.LITTLE "switcher" provides the core functionality to
1365 transparently handle transition between a cluster of A15's
1366 and a cluster of A7's in a big.LITTLE system.
1368 config BL_SWITCHER_DUMMY_IF
1369 tristate "Simple big.LITTLE switcher user interface"
1370 depends on BL_SWITCHER && DEBUG_KERNEL
1372 This is a simple and dummy char dev interface to control
1373 the big.LITTLE switcher core code. It is meant for
1374 debugging purposes only.
1377 prompt "Memory split"
1381 Select the desired split between kernel and user memory.
1383 If you are not absolutely sure what you are doing, leave this
1387 bool "3G/1G user/kernel split"
1388 config VMSPLIT_3G_OPT
1389 bool "3G/1G user/kernel split (for full 1G low memory)"
1391 bool "2G/2G user/kernel split"
1393 bool "1G/3G user/kernel split"
1398 default PHYS_OFFSET if !MMU
1399 default 0x40000000 if VMSPLIT_1G
1400 default 0x80000000 if VMSPLIT_2G
1401 default 0xB0000000 if VMSPLIT_3G_OPT
1405 int "Maximum number of CPUs (2-32)"
1411 bool "Support for hot-pluggable CPUs"
1414 Say Y here to experiment with turning CPUs off and on. CPUs
1415 can be controlled through /sys/devices/system/cpu.
1418 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1419 depends on HAVE_ARM_SMCCC
1422 Say Y here if you want Linux to communicate with system firmware
1423 implementing the PSCI specification for CPU-centric power
1424 management operations described in ARM document number ARM DEN
1425 0022A ("Power State Coordination Interface System Software on
1428 # The GPIO number here must be sorted by descending number. In case of
1429 # a multiplatform kernel, we just want the highest value required by the
1430 # selected platforms.
1433 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1435 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1436 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1437 default 416 if ARCH_SUNXI
1438 default 392 if ARCH_U8500
1439 default 352 if ARCH_VT8500
1440 default 288 if ARCH_ROCKCHIP
1441 default 264 if MACH_H4700
1444 Maximum number of GPIOs in the system.
1446 If unsure, leave the default value.
1448 source kernel/Kconfig.preempt
1452 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1453 ARCH_S5PV210 || ARCH_EXYNOS4
1454 default 128 if SOC_AT91RM9200
1458 depends on HZ_FIXED = 0
1459 prompt "Timer frequency"
1483 default HZ_FIXED if HZ_FIXED != 0
1484 default 100 if HZ_100
1485 default 200 if HZ_200
1486 default 250 if HZ_250
1487 default 300 if HZ_300
1488 default 500 if HZ_500
1492 def_bool HIGH_RES_TIMERS
1494 config THUMB2_KERNEL
1495 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1496 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1497 default y if CPU_THUMBONLY
1499 select ARM_ASM_UNIFIED
1502 By enabling this option, the kernel will be compiled in
1503 Thumb-2 mode. A compiler/assembler that understand the unified
1504 ARM-Thumb syntax is needed.
1508 config THUMB2_AVOID_R_ARM_THM_JUMP11
1509 bool "Work around buggy Thumb-2 short branch relocations in gas"
1510 depends on THUMB2_KERNEL && MODULES
1513 Various binutils versions can resolve Thumb-2 branches to
1514 locally-defined, preemptible global symbols as short-range "b.n"
1515 branch instructions.
1517 This is a problem, because there's no guarantee the final
1518 destination of the symbol, or any candidate locations for a
1519 trampoline, are within range of the branch. For this reason, the
1520 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1521 relocation in modules at all, and it makes little sense to add
1524 The symptom is that the kernel fails with an "unsupported
1525 relocation" error when loading some modules.
1527 Until fixed tools are available, passing
1528 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1529 code which hits this problem, at the cost of a bit of extra runtime
1530 stack usage in some cases.
1532 The problem is described in more detail at:
1533 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1535 Only Thumb-2 kernels are affected.
1537 Unless you are sure your tools don't have this problem, say Y.
1539 config ARM_ASM_UNIFIED
1542 config ARM_PATCH_IDIV
1543 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1544 depends on CPU_32v7 && !XIP_KERNEL
1547 The ARM compiler inserts calls to __aeabi_idiv() and
1548 __aeabi_uidiv() when it needs to perform division on signed
1549 and unsigned integers. Some v7 CPUs have support for the sdiv
1550 and udiv instructions that can be used to implement those
1553 Enabling this option allows the kernel to modify itself to
1554 replace the first two instructions of these library functions
1555 with the sdiv or udiv plus "bx lr" instructions when the CPU
1556 it is running on supports them. Typically this will be faster
1557 and less power intensive than running the original library
1558 code to do integer division.
1561 bool "Use the ARM EABI to compile the kernel"
1563 This option allows for the kernel to be compiled using the latest
1564 ARM ABI (aka EABI). This is only useful if you are using a user
1565 space environment that is also compiled with EABI.
1567 Since there are major incompatibilities between the legacy ABI and
1568 EABI, especially with regard to structure member alignment, this
1569 option also changes the kernel syscall calling convention to
1570 disambiguate both ABIs and allow for backward compatibility support
1571 (selected with CONFIG_OABI_COMPAT).
1573 To use this you need GCC version 4.0.0 or later.
1576 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1577 depends on AEABI && !THUMB2_KERNEL
1579 This option preserves the old syscall interface along with the
1580 new (ARM EABI) one. It also provides a compatibility layer to
1581 intercept syscalls that have structure arguments which layout
1582 in memory differs between the legacy ABI and the new ARM EABI
1583 (only for non "thumb" binaries). This option adds a tiny
1584 overhead to all syscalls and produces a slightly larger kernel.
1586 The seccomp filter system will not be available when this is
1587 selected, since there is no way yet to sensibly distinguish
1588 between calling conventions during filtering.
1590 If you know you'll be using only pure EABI user space then you
1591 can say N here. If this option is not selected and you attempt
1592 to execute a legacy ABI binary then the result will be
1593 UNPREDICTABLE (in fact it can be predicted that it won't work
1594 at all). If in doubt say N.
1596 config ARCH_HAS_HOLES_MEMORYMODEL
1599 config ARCH_SPARSEMEM_ENABLE
1602 config ARCH_SPARSEMEM_DEFAULT
1603 def_bool ARCH_SPARSEMEM_ENABLE
1605 config ARCH_SELECT_MEMORY_MODEL
1606 def_bool ARCH_SPARSEMEM_ENABLE
1608 config HAVE_ARCH_PFN_VALID
1609 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1611 config HAVE_GENERIC_RCU_GUP
1616 bool "High Memory Support"
1619 The address space of ARM processors is only 4 Gigabytes large
1620 and it has to accommodate user address space, kernel address
1621 space as well as some memory mapped IO. That means that, if you
1622 have a large amount of physical memory and/or IO, not all of the
1623 memory can be "permanently mapped" by the kernel. The physical
1624 memory that is not permanently mapped is called "high memory".
1626 Depending on the selected kernel/user memory split, minimum
1627 vmalloc space and actual amount of RAM, you may not need this
1628 option which should result in a slightly faster kernel.
1633 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1637 The VM uses one page of physical memory for each page table.
1638 For systems with a lot of processes, this can use a lot of
1639 precious low memory, eventually leading to low memory being
1640 consumed by page tables. Setting this option will allow
1641 user-space 2nd level page tables to reside in high memory.
1643 config CPU_SW_DOMAIN_PAN
1644 bool "Enable use of CPU domains to implement privileged no-access"
1645 depends on MMU && !ARM_LPAE
1648 Increase kernel security by ensuring that normal kernel accesses
1649 are unable to access userspace addresses. This can help prevent
1650 use-after-free bugs becoming an exploitable privilege escalation
1651 by ensuring that magic values (such as LIST_POISON) will always
1652 fault when dereferenced.
1654 CPUs with low-vector mappings use a best-efforts implementation.
1655 Their lower 1MB needs to remain accessible for the vectors, but
1656 the remainder of userspace will become appropriately inaccessible.
1658 config HW_PERF_EVENTS
1662 config SYS_SUPPORTS_HUGETLBFS
1666 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1670 config ARCH_WANT_GENERAL_HUGETLB
1673 config ARM_MODULE_PLTS
1674 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1677 Allocate PLTs when loading modules so that jumps and calls whose
1678 targets are too far away for their relative offsets to be encoded
1679 in the instructions themselves can be bounced via veneers in the
1680 module's PLT. This allows modules to be allocated in the generic
1681 vmalloc area after the dedicated module memory area has been
1682 exhausted. The modules will use slightly more memory, but after
1683 rounding up to page size, the actual memory footprint is usually
1686 Say y if you are getting out of memory errors while loading modules
1690 config FORCE_MAX_ZONEORDER
1691 int "Maximum zone order"
1692 default "12" if SOC_AM33XX
1693 default "9" if SA1111 || ARCH_EFM32
1696 The kernel memory allocator divides physically contiguous memory
1697 blocks into "zones", where each zone is a power of two number of
1698 pages. This option selects the largest power of two that the kernel
1699 keeps in the memory allocator. If you need to allocate very large
1700 blocks of physically contiguous memory, then you may need to
1701 increase this value.
1703 This config option is actually maximum order plus one. For example,
1704 a value of 11 means that the largest free memory block is 2^10 pages.
1706 config ALIGNMENT_TRAP
1708 depends on CPU_CP15_MMU
1709 default y if !ARCH_EBSA110
1710 select HAVE_PROC_CPU if PROC_FS
1712 ARM processors cannot fetch/store information which is not
1713 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1714 address divisible by 4. On 32-bit ARM processors, these non-aligned
1715 fetch/store instructions will be emulated in software if you say
1716 here, which has a severe performance impact. This is necessary for
1717 correct operation of some network protocols. With an IP-only
1718 configuration it is safe to say N, otherwise say Y.
1720 config UACCESS_WITH_MEMCPY
1721 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1723 default y if CPU_FEROCEON
1725 Implement faster copy_to_user and clear_user methods for CPU
1726 cores where a 8-word STM instruction give significantly higher
1727 memory write throughput than a sequence of individual 32bit stores.
1729 A possible side effect is a slight increase in scheduling latency
1730 between threads sharing the same address space if they invoke
1731 such copy operations with large buffers.
1733 However, if the CPU data cache is using a write-allocate mode,
1734 this option is unlikely to provide any performance gain.
1738 prompt "Enable seccomp to safely compute untrusted bytecode"
1740 This kernel feature is useful for number crunching applications
1741 that may need to compute untrusted bytecode during their
1742 execution. By using pipes or other transports made available to
1743 the process as file descriptors supporting the read/write
1744 syscalls, it's possible to isolate those applications in
1745 their own address space using seccomp. Once seccomp is
1746 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1747 and the task is only allowed to execute a few safe syscalls
1748 defined by each seccomp mode.
1757 bool "Enable paravirtualization code"
1759 This changes the kernel so it can modify itself when it is run
1760 under a hypervisor, potentially improving performance significantly
1761 over full virtualization.
1763 config PARAVIRT_TIME_ACCOUNTING
1764 bool "Paravirtual steal time accounting"
1768 Select this option to enable fine granularity task steal time
1769 accounting. Time spent executing other tasks in parallel with
1770 the current vCPU is discounted from the vCPU power. To account for
1771 that, there can be a small performance impact.
1773 If in doubt, say N here.
1780 bool "Xen guest support on ARM"
1781 depends on ARM && AEABI && OF
1782 depends on CPU_V7 && !CPU_V6
1783 depends on !GENERIC_ATOMIC64
1785 select ARCH_DMA_ADDR_T_64BIT
1790 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1797 bool "Flattened Device Tree support"
1801 Include support for flattened device tree machine descriptions.
1804 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1807 This is the traditional way of passing data to the kernel at boot
1808 time. If you are solely relying on the flattened device tree (or
1809 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1810 to remove ATAGS support from your kernel binary. If unsure,
1813 config DEPRECATED_PARAM_STRUCT
1814 bool "Provide old way to pass kernel parameters"
1817 This was deprecated in 2001 and announced to live on for 5 years.
1818 Some old boot loaders still use this way.
1820 # Compressed boot loader in ROM. Yes, we really want to ask about
1821 # TEXT and BSS so we preserve their values in the config files.
1822 config ZBOOT_ROM_TEXT
1823 hex "Compressed ROM boot loader base address"
1826 The physical address at which the ROM-able zImage is to be
1827 placed in the target. Platforms which normally make use of
1828 ROM-able zImage formats normally set this to a suitable
1829 value in their defconfig file.
1831 If ZBOOT_ROM is not enabled, this has no effect.
1833 config ZBOOT_ROM_BSS
1834 hex "Compressed ROM boot loader BSS address"
1837 The base address of an area of read/write memory in the target
1838 for the ROM-able zImage which must be available while the
1839 decompressor is running. It must be large enough to hold the
1840 entire decompressed kernel plus an additional 128 KiB.
1841 Platforms which normally make use of ROM-able zImage formats
1842 normally set this to a suitable value in their defconfig file.
1844 If ZBOOT_ROM is not enabled, this has no effect.
1847 bool "Compressed boot loader in ROM/flash"
1848 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1849 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1851 Say Y here if you intend to execute your compressed kernel image
1852 (zImage) directly from ROM or flash. If unsure, say N.
1854 config ARM_APPENDED_DTB
1855 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1858 With this option, the boot code will look for a device tree binary
1859 (DTB) appended to zImage
1860 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1862 This is meant as a backward compatibility convenience for those
1863 systems with a bootloader that can't be upgraded to accommodate
1864 the documented boot protocol using a device tree.
1866 Beware that there is very little in terms of protection against
1867 this option being confused by leftover garbage in memory that might
1868 look like a DTB header after a reboot if no actual DTB is appended
1869 to zImage. Do not leave this option active in a production kernel
1870 if you don't intend to always append a DTB. Proper passing of the
1871 location into r2 of a bootloader provided DTB is always preferable
1874 config ARM_ATAG_DTB_COMPAT
1875 bool "Supplement the appended DTB with traditional ATAG information"
1876 depends on ARM_APPENDED_DTB
1878 Some old bootloaders can't be updated to a DTB capable one, yet
1879 they provide ATAGs with memory configuration, the ramdisk address,
1880 the kernel cmdline string, etc. Such information is dynamically
1881 provided by the bootloader and can't always be stored in a static
1882 DTB. To allow a device tree enabled kernel to be used with such
1883 bootloaders, this option allows zImage to extract the information
1884 from the ATAG list and store it at run time into the appended DTB.
1887 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1888 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1890 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1891 bool "Use bootloader kernel arguments if available"
1893 Uses the command-line options passed by the boot loader instead of
1894 the device tree bootargs property. If the boot loader doesn't provide
1895 any, the device tree bootargs property will be used.
1897 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1898 bool "Extend with bootloader kernel arguments"
1900 The command-line arguments provided by the boot loader will be
1901 appended to the the device tree bootargs property.
1906 string "Default kernel command string"
1909 On some architectures (EBSA110 and CATS), there is currently no way
1910 for the boot loader to pass arguments to the kernel. For these
1911 architectures, you should supply some command-line options at build
1912 time by entering them here. As a minimum, you should specify the
1913 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1916 prompt "Kernel command line type" if CMDLINE != ""
1917 default CMDLINE_FROM_BOOTLOADER
1920 config CMDLINE_FROM_BOOTLOADER
1921 bool "Use bootloader kernel arguments if available"
1923 Uses the command-line options passed by the boot loader. If
1924 the boot loader doesn't provide any, the default kernel command
1925 string provided in CMDLINE will be used.
1927 config CMDLINE_EXTEND
1928 bool "Extend bootloader kernel arguments"
1930 The command-line arguments provided by the boot loader will be
1931 appended to the default kernel command string.
1933 config CMDLINE_FORCE
1934 bool "Always use the default kernel command string"
1936 Always use the default kernel command string, even if the boot
1937 loader passes other arguments to the kernel.
1938 This is useful if you cannot or don't want to change the
1939 command-line options your boot loader passes to the kernel.
1943 bool "Kernel Execute-In-Place from ROM"
1944 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1946 Execute-In-Place allows the kernel to run from non-volatile storage
1947 directly addressable by the CPU, such as NOR flash. This saves RAM
1948 space since the text section of the kernel is not loaded from flash
1949 to RAM. Read-write sections, such as the data section and stack,
1950 are still copied to RAM. The XIP kernel is not compressed since
1951 it has to run directly from flash, so it will take more space to
1952 store it. The flash address used to link the kernel object files,
1953 and for storing it, is configuration dependent. Therefore, if you
1954 say Y here, you must know the proper physical address where to
1955 store the kernel image depending on your own flash memory usage.
1957 Also note that the make target becomes "make xipImage" rather than
1958 "make zImage" or "make Image". The final kernel binary to put in
1959 ROM memory will be arch/arm/boot/xipImage.
1963 config XIP_PHYS_ADDR
1964 hex "XIP Kernel Physical Location"
1965 depends on XIP_KERNEL
1966 default "0x00080000"
1968 This is the physical address in your flash memory the kernel will
1969 be linked for and stored to. This address is dependent on your
1973 bool "Kexec system call (EXPERIMENTAL)"
1974 depends on (!SMP || PM_SLEEP_SMP)
1978 kexec is a system call that implements the ability to shutdown your
1979 current kernel, and to start another kernel. It is like a reboot
1980 but it is independent of the system firmware. And like a reboot
1981 you can start any kernel with it, not just Linux.
1983 It is an ongoing process to be certain the hardware in a machine
1984 is properly shutdown, so do not be surprised if this code does not
1985 initially work for you.
1988 bool "Export atags in procfs"
1989 depends on ATAGS && KEXEC
1992 Should the atags used to boot the kernel be exported in an "atags"
1993 file in procfs. Useful with kexec.
1996 bool "Build kdump crash kernel (EXPERIMENTAL)"
1998 Generate crash dump after being started by kexec. This should
1999 be normally only set in special crash dump kernels which are
2000 loaded in the main kernel with kexec-tools into a specially
2001 reserved region and then later executed after a crash by
2002 kdump/kexec. The crash dump kernel must be compiled to a
2003 memory address not used by the main kernel
2005 For more details see Documentation/kdump/kdump.txt
2007 config AUTO_ZRELADDR
2008 bool "Auto calculation of the decompressed kernel image address"
2010 ZRELADDR is the physical address where the decompressed kernel
2011 image will be placed. If AUTO_ZRELADDR is selected, the address
2012 will be determined at run-time by masking the current IP with
2013 0xf8000000. This assumes the zImage being placed in the first 128MB
2014 from start of memory.
2020 bool "UEFI runtime support"
2021 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2023 select EFI_PARAMS_FROM_FDT
2026 select EFI_RUNTIME_WRAPPERS
2028 This option provides support for runtime services provided
2029 by UEFI firmware (such as non-volatile variables, realtime
2030 clock, and platform reset). A UEFI stub is also provided to
2031 allow the kernel to be booted as an EFI application. This
2032 is only useful for kernels that may run on systems that have
2037 menu "CPU Power Management"
2039 source "drivers/cpufreq/Kconfig"
2041 source "drivers/cpuidle/Kconfig"
2045 menu "Floating point emulation"
2047 comment "At least one emulation must be selected"
2050 bool "NWFPE math emulation"
2051 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2053 Say Y to include the NWFPE floating point emulator in the kernel.
2054 This is necessary to run most binaries. Linux does not currently
2055 support floating point hardware so you need to say Y here even if
2056 your machine has an FPA or floating point co-processor podule.
2058 You may say N here if you are going to load the Acorn FPEmulator
2059 early in the bootup.
2062 bool "Support extended precision"
2063 depends on FPE_NWFPE
2065 Say Y to include 80-bit support in the kernel floating-point
2066 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2067 Note that gcc does not generate 80-bit operations by default,
2068 so in most cases this option only enlarges the size of the
2069 floating point emulator without any good reason.
2071 You almost surely want to say N here.
2074 bool "FastFPE math emulation (EXPERIMENTAL)"
2075 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2077 Say Y here to include the FAST floating point emulator in the kernel.
2078 This is an experimental much faster emulator which now also has full
2079 precision for the mantissa. It does not support any exceptions.
2080 It is very simple, and approximately 3-6 times faster than NWFPE.
2082 It should be sufficient for most programs. It may be not suitable
2083 for scientific calculations, but you have to check this for yourself.
2084 If you do not feel you need a faster FP emulation you should better
2088 bool "VFP-format floating point maths"
2089 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2091 Say Y to include VFP support code in the kernel. This is needed
2092 if your hardware includes a VFP unit.
2094 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2095 release notes and additional status information.
2097 Say N if your target does not have VFP hardware.
2105 bool "Advanced SIMD (NEON) Extension support"
2106 depends on VFPv3 && CPU_V7
2108 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2111 config KERNEL_MODE_NEON
2112 bool "Support for NEON in kernel mode"
2113 depends on NEON && AEABI
2115 Say Y to include support for NEON in kernel mode.
2119 menu "Userspace binary formats"
2121 source "fs/Kconfig.binfmt"
2125 menu "Power management options"
2127 source "kernel/power/Kconfig"
2129 config ARCH_SUSPEND_POSSIBLE
2130 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2131 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2134 config ARM_CPU_SUSPEND
2135 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2136 depends on ARCH_SUSPEND_POSSIBLE
2138 config ARCH_HIBERNATION_POSSIBLE
2141 default y if ARCH_SUSPEND_POSSIBLE
2145 source "net/Kconfig"
2147 source "drivers/Kconfig"
2149 source "drivers/firmware/Kconfig"
2153 source "arch/arm/Kconfig.debug"
2155 source "security/Kconfig"
2157 source "crypto/Kconfig"
2159 source "arch/arm/crypto/Kconfig"
2162 source "lib/Kconfig"
2164 source "arch/arm/kvm/Kconfig"