1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Wesley Cheng <quic_wcheng@quicinc.com>
54 description: Offset and length of register set for QSCRATCH wrapper
66 description: specifies a phandle to PM domain provider node
74 Several clocks are used, depending on the variant. Typical ones are::
75 - cfg_noc:: System Config NOC clock.
76 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
77 60MHz for HS operation.
78 - iface:: System bus AXI clock.
79 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
81 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
82 mode. Its frequency should be 19.2MHz.
103 Different types of interrupts are used based on HS PHY used on target:
104 - pwr_event: Used for wakeup based on other power events.
105 - hs_phY_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
106 hs_phy_irq which is not triggered by default and its
107 functionality is mutually exclusive to that of
108 {dp/dm}_hs_phy_irq and qusb2_phy_irq.
109 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
110 expose only a single IRQ whose behavior can be modified
111 by the QUSB2PHY_INTR_CTRL register. The required DPSE/
112 DMSE configuration is done in QUSB2PHY_INTR_CTRL register
113 of PHY address space.
114 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/
115 DM pads of the SoC. These are used for wakeup
116 only on SoCs with non-QUSB2 targets with
117 exception of SDM670/SDM845/SM6350.
118 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
126 qcom,select-utmi-as-pipe-clk:
128 If present, disable USB3 pipe_clk requirement.
129 Used when dwc3 operates without SSPHY and only
130 HS/FS/LS modes are supported.
135 # Required child node:
139 $ref: snps,dwc3.yaml#
140 unevaluatedProperties: false
183 - description: Master/Core clock, has to be >= 125 MHz
184 for SS operation and >= 60MHz for HS operation.
298 - const: noc_aggr_north
299 - const: noc_aggr_south
431 - const: dp_hs_phy_irq
432 - const: dm_hs_phy_irq
469 - const: dp_hs_phy_irq
470 - const: dm_hs_phy_irq
473 additionalProperties: false
477 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
478 #include <dt-bindings/interrupt-controller/arm-gic.h>
479 #include <dt-bindings/interrupt-controller/irq.h>
481 #address-cells = <2>;
485 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
486 reg = <0 0x0a6f8800 0 0x400>;
488 #address-cells = <2>;
491 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
492 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
493 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
494 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
495 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
496 clock-names = "cfg_noc",
502 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
503 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
504 assigned-clock-rates = <19200000>, <150000000>;
506 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,
509 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
510 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
511 interrupt-names = "pwr_event", "hs_phy_irq",
512 "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq";
514 power-domains = <&gcc USB30_PRIM_GDSC>;
516 resets = <&gcc GCC_USB30_PRIM_BCR>;
519 compatible = "snps,dwc3";
520 reg = <0 0x0a600000 0 0xcd00>;
521 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
522 iommus = <&apps_smmu 0x740 0>;
523 snps,dis_u2_susphy_quirk;
524 snps,dis_enblslpm_quirk;
525 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
526 phy-names = "usb2-phy", "usb3-phy";