1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Wesley Cheng <quic_wcheng@quicinc.com>
52 description: Offset and length of register set for QSCRATCH wrapper
64 description: specifies a phandle to PM domain provider node
72 Several clocks are used, depending on the variant. Typical ones are::
73 - cfg_noc:: System Config NOC clock.
74 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
75 60MHz for HS operation.
76 - iface:: System bus AXI clock.
77 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
79 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
80 mode. Its frequency should be 19.2MHz.
107 qcom,select-utmi-as-pipe-clk:
109 If present, disable USB3 pipe_clk requirement.
110 Used when dwc3 operates without SSPHY and only
111 HS/FS/LS modes are supported.
116 # Required child node:
120 $ref: snps,dwc3.yaml#
121 unevaluatedProperties: false
164 - description: Master/Core clock, has to be >= 125 MHz
165 for SS operation and >= 60MHz for HS operation.
278 - const: noc_aggr_north
279 - const: noc_aggr_south
384 - description: The interrupt that is asserted
385 when a wakeup event is received on USB2 bus.
386 - description: The interrupt that is asserted
387 when a wakeup event is received on USB3 bus.
388 - description: Wakeup event on DM line.
389 - description: Wakeup event on DP line.
394 - const: dm_hs_phy_irq
395 - const: dp_hs_phy_irq
449 - const: dp_hs_phy_irq
450 - const: dm_hs_phy_irq
466 - const: dp_hs_phy_irq
467 - const: dm_hs_phy_irq
485 - const: dp_hs_phy_irq
486 - const: dm_hs_phy_irq
489 additionalProperties: false
493 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
494 #include <dt-bindings/interrupt-controller/arm-gic.h>
495 #include <dt-bindings/interrupt-controller/irq.h>
497 #address-cells = <2>;
501 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
502 reg = <0 0x0a6f8800 0 0x400>;
504 #address-cells = <2>;
507 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
508 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
509 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
510 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
511 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
512 clock-names = "cfg_noc",
518 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
519 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
520 assigned-clock-rates = <19200000>, <150000000>;
522 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
525 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
526 interrupt-names = "hs_phy_irq", "ss_phy_irq",
527 "dm_hs_phy_irq", "dp_hs_phy_irq";
529 power-domains = <&gcc USB30_PRIM_GDSC>;
531 resets = <&gcc GCC_USB30_PRIM_BCR>;
534 compatible = "snps,dwc3";
535 reg = <0 0x0a600000 0 0xcd00>;
536 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
537 iommus = <&apps_smmu 0x740 0>;
538 snps,dis_u2_susphy_quirk;
539 snps,dis_enblslpm_quirk;
540 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
541 phy-names = "usb2-phy", "usb3-phy";