1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Generic Binding
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
16 but not for both at the same time.
20 pattern: "^spi(@.*|-[0-9a-f])*$"
30 GPIOs used as chip selects.
31 If that property is used, the number of chip selects will be
32 increased automatically with max(cs-gpios, hardware chip selects).
34 So if, for example, the controller has 4 CS lines, and the
35 cs-gpios looks like this
36 cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
38 Then it should be configured so that num_chipselect = 4, with
46 $ref: /schemas/types.yaml#/definitions/uint32
48 Total number of chip selects.
51 $ref: /schemas/types.yaml#/definitions/flag
53 The SPI controller acts as a slave, instead of a master.
76 Compatible of the SPI device.
87 Compatible of the SPI device.
93 Chip select used by the device.
96 $ref: /schemas/types.yaml#/definitions/flag
98 The device requires 3-wire mode.
101 $ref: /schemas/types.yaml#/definitions/flag
103 The device requires shifted clock phase (CPHA) mode.
106 $ref: /schemas/types.yaml#/definitions/flag
108 The device requires inverse clock polarity (CPOL) mode.
111 $ref: /schemas/types.yaml#/definitions/flag
113 The device requires the chip select active high.
116 $ref: /schemas/types.yaml#/definitions/flag
118 The device requires the LSB first mode.
121 $ref: /schemas/types.yaml#/definitions/uint32
123 Maximum SPI clocking speed of the device in Hz.
127 Bus width to the SPI bus used for read transfers.
128 $ref: /schemas/types.yaml#/definitions/uint32
134 Delay, in microseconds, after a read transfer.
138 Bus width to the SPI bus used for write transfers.
139 $ref: /schemas/types.yaml#/definitions/uint32
145 Delay, in microseconds, after a write transfer.
151 additionalProperties: true
156 #address-cells = <1>;
158 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
160 interrupts = <2 13 0 2 14 0>;
161 interrupt-parent = <&mpc5200_pic>;
164 compatible = "micrel,ks8995m";
165 spi-max-frequency = <1000000>;
170 compatible = "ti,tlv320aic26";
171 spi-max-frequency = <100000>;