1 Mediatek AFE PCM controller for mt2701
4 - compatible = "mediatek,mt2701-audio";
5 - reg: register location and size
6 - interrupts: should contain AFE and ASYS interrupts
7 - interrupt-names: should be "afe" and "asys"
8 - power-domains: should define the power domain
9 - clock-names: should have these clock names:
10 "infra_sys_audio_clk",
15 "top_audio_48k_timing",
16 "top_audio_44k_timing",
22 "top_hadds2_pll_294M",
57 afe: mt2701-afe-pcm@11220000 {
58 compatible = "mediatek,mt2701-audio";
59 reg = <0 0x11220000 0 0x2000>,
60 <0 0x112A0000 0 0x20000>;
61 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
62 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
63 interrupt-names = "afe", "asys";
64 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
65 clocks = <&infracfg CLK_INFRA_AUDIO>,
66 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
67 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
68 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
69 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
70 <&topckgen CLK_TOP_AUD_48K_TIMING>,
71 <&topckgen CLK_TOP_AUD_44K_TIMING>,
72 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
73 <&topckgen CLK_TOP_APLL_SEL>,
74 <&topckgen CLK_TOP_AUD1PLL_98M>,
75 <&topckgen CLK_TOP_AUD2PLL_90M>,
76 <&topckgen CLK_TOP_HADDS2PLL_98M>,
77 <&topckgen CLK_TOP_HADDS2PLL_294M>,
78 <&topckgen CLK_TOP_AUDPLL>,
79 <&topckgen CLK_TOP_AUDPLL_D4>,
80 <&topckgen CLK_TOP_AUDPLL_D8>,
81 <&topckgen CLK_TOP_AUDPLL_D16>,
82 <&topckgen CLK_TOP_AUDPLL_D24>,
83 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
85 <&topckgen CLK_TOP_SYSPLL1_D4>,
86 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
87 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
88 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
89 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
90 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
91 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
92 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
93 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
94 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
95 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
96 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
97 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
98 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
99 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
100 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
101 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
102 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
103 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
104 <&topckgen CLK_TOP_ASM_M_SEL>,
105 <&topckgen CLK_TOP_ASM_H_SEL>,
106 <&topckgen CLK_TOP_UNIVPLL2_D4>,
107 <&topckgen CLK_TOP_UNIVPLL2_D2>,
108 <&topckgen CLK_TOP_SYSPLL_D5>;
110 clock-names = "infra_sys_audio_clk",
111 "top_audio_mux1_sel",
112 "top_audio_mux2_sel",
113 "top_audio_mux1_div",
114 "top_audio_mux2_div",
115 "top_audio_48k_timing",
116 "top_audio_44k_timing",
117 "top_audpll_mux_sel",
121 "top_hadds2_pll_98M",
122 "top_hadds2_pll_294M",
131 "top_aud_k1_src_sel",
132 "top_aud_k2_src_sel",
133 "top_aud_k3_src_sel",
134 "top_aud_k4_src_sel",
135 "top_aud_k5_src_sel",
136 "top_aud_k6_src_sel",
137 "top_aud_k1_src_div",
138 "top_aud_k2_src_div",
139 "top_aud_k3_src_div",
140 "top_aud_k4_src_div",
141 "top_aud_k5_src_div",
142 "top_aud_k6_src_div",