1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMH RSC
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Resource Power Manager Hardened (RPMH) is the mechanism for communicating
14 with the hardened resource accelerators on Qualcomm SoCs. Requests to the
15 resources can be written to the Trigger Command Set (TCS) registers and
16 using a (addr, val) pair and triggered. Messages in the TCS are then sent in
17 sequence over an internal bus.
19 The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
20 (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
21 active/wake resource requests. Multiple such DRVs can exist in a SoC and can
22 be written to from Linux. The structure of each DRV follows the same template
23 with a few variations that are captured by the properties here.
25 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
26 have powered off to facilitate idle power saving. TCS could be classified as::
27 ACTIVE - Triggered by Linux
28 SLEEP - Triggered by F/W
29 WAKE - Triggered by F/W
30 CONTROL - Triggered by F/W
31 See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
33 The order in which they are described in the DT, should match the hardware
36 Requests can be made for the state of a resource, when the subsystem is
37 active or idle. When all subsystems like Modem, GPU, CPU are idle, the
38 resource state will be an aggregate of the sleep votes from each of those
39 subsystems. Clients may request a sleep value for their shared resources in
40 addition to the active mode requests.
42 Drivers that want to use the RSC to communicate with RPMH must specify their
43 bindings as child nodes of the RSC controllers they wish to communicate with.
53 The interrupt that trips when a message complete/response is received for
54 this DRV from the accelerators.
55 Number of interrupts must match number of DRV blocks.
59 Name for the RSC. The name would be used in trace logs.
62 $ref: /schemas/types.yaml#/definitions/uint32
64 The ID of the DRV in the RSC block that will be used by this controller.
67 $ref: /schemas/types.yaml#/definitions/uint32-matrix
79 - description: Number of TCS
81 The tuple defining the configuration of TCS. Must have two cells which
82 describe each TCS type. The order of the TCS must match the hardware
86 $ref: /schemas/types.yaml#/definitions/uint32
88 The offset of the TCS blocks.
103 $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
106 $ref: /schemas/clock/qcom,rpmhcc.yaml#
109 $ref: /schemas/power/qcom,rpmpd.yaml#
113 $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
124 additionalProperties: false
128 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
129 // 2, the register offsets for DRV2 start at 0D00, the register
130 // calculations are like this::
132 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
133 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
135 #include <dt-bindings/interrupt-controller/arm-gic.h>
136 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
139 compatible = "qcom,rpmh-rsc";
140 reg = <0x179c0000 0x10000>,
141 <0x179d0000 0x10000>,
142 <0x179e0000 0x10000>;
143 reg-names = "drv-0", "drv-1", "drv-2";
144 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
148 qcom,tcs-offset = <0xd00>;
150 qcom,tcs-config = <ACTIVE_TCS 2>,
157 // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
158 // register offsets for DRV0 start at 01C00, the register calculations are
161 // TCS-OFFSET: 0x1C00
162 #include <dt-bindings/interrupt-controller/arm-gic.h>
163 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
166 compatible = "qcom,rpmh-rsc";
167 reg = <0xaf20000 0x10000>;
169 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
171 qcom,tcs-offset = <0x1c00>;
173 qcom,tcs-config = <ACTIVE_TCS 0>,
180 #include <dt-bindings/interrupt-controller/arm-gic.h>
181 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
182 #include <dt-bindings/power/qcom-rpmpd.h>
185 compatible = "qcom,rpmh-rsc";
186 reg = <0x18200000 0x10000>,
187 <0x18210000 0x10000>,
188 <0x18220000 0x10000>;
189 reg-names = "drv-0", "drv-1", "drv-2";
190 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
194 qcom,tcs-offset = <0xd00>;
196 qcom,tcs-config = <ACTIVE_TCS 2>,
202 compatible = "qcom,sm8350-rpmh-clk";
205 clocks = <&xo_board>;
209 compatible = "qcom,sm8350-rpmhpd";
210 #power-domain-cells = <1>;
211 operating-points-v2 = <&rpmhpd_opp_table>;
213 rpmhpd_opp_table: opp-table {
214 compatible = "operating-points-v2";
216 rpmhpd_opp_ret: opp1 {
217 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
220 rpmhpd_opp_min_svs: opp2 {
221 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
224 rpmhpd_opp_low_svs: opp3 {
225 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
228 rpmhpd_opp_svs: opp4 {
229 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
232 rpmhpd_opp_svs_l1: opp5 {
233 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
236 rpmhpd_opp_nom: opp6 {
237 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
240 rpmhpd_opp_nom_l1: opp7 {
241 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
244 rpmhpd_opp_nom_l2: opp8 {
245 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
248 rpmhpd_opp_turbo: opp9 {
249 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
252 rpmhpd_opp_turbo_l1: opp10 {
253 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
259 compatible = "qcom,bcm-voter";