1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMH RSC
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Resource Power Manager Hardened (RPMH) is the mechanism for communicating
14 with the hardened resource accelerators on Qualcomm SoCs. Requests to the
15 resources can be written to the Trigger Command Set (TCS) registers and
16 using a (addr, val) pair and triggered. Messages in the TCS are then sent in
17 sequence over an internal bus.
19 The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
20 (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
21 active/wake resource requests. Multiple such DRVs can exist in a SoC and can
22 be written to from Linux. The structure of each DRV follows the same template
23 with a few variations that are captured by the properties here.
25 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
26 have powered off to facilitate idle power saving. TCS could be classified as::
27 ACTIVE - Triggered by Linux
28 SLEEP - Triggered by F/W
29 WAKE - Triggered by F/W
30 CONTROL - Triggered by F/W
31 See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
33 The order in which they are described in the DT, should match the hardware
36 Requests can be made for the state of a resource, when the subsystem is
37 active or idle. When all subsystems like Modem, GPU, CPU are idle, the
38 resource state will be an aggregate of the sleep votes from each of those
39 subsystems. Clients may request a sleep value for their shared resources in
40 addition to the active mode requests.
42 Drivers that want to use the RSC to communicate with RPMH must specify their
43 bindings as child nodes of the RSC controllers they wish to communicate with.
53 The interrupt that trips when a message complete/response is received for
54 this DRV from the accelerators.
55 Number of interrupts must match number of DRV blocks.
59 Name for the RSC. The name would be used in trace logs.
62 $ref: /schemas/types.yaml#/definitions/uint32
64 The ID of the DRV in the RSC block that will be used by this controller.
67 $ref: /schemas/types.yaml#/definitions/uint32-matrix
70 - description: TCS type
72 - description: Number of TCS
74 - description: TCS type
76 - description: Number of TCS
78 - description: TCS type
80 - description: Numbe r of TCS
82 - description: TCS type
84 - description: Number of TCS
86 The tuple defining the configuration of TCS. Must have two cells which
87 describe each TCS type. The order of the TCS must match the hardware
89 Cell 1 (TCS Type):: TCS types to be specified::
94 Cell 2 (Number of TCS):: <u32>
97 $ref: /schemas/types.yaml#/definitions/uint32
99 The offset of the TCS blocks.
114 $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
117 $ref: /schemas/clock/qcom,rpmhcc.yaml#
120 $ref: /schemas/power/qcom,rpmpd.yaml#
124 $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
135 additionalProperties: false
139 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
140 // 2, the register offsets for DRV2 start at 0D00, the register
141 // calculations are like this::
143 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
144 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
146 #include <dt-bindings/interrupt-controller/arm-gic.h>
147 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
150 compatible = "qcom,rpmh-rsc";
151 reg = <0x179c0000 0x10000>,
152 <0x179d0000 0x10000>,
153 <0x179e0000 0x10000>;
154 reg-names = "drv-0", "drv-1", "drv-2";
155 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
159 qcom,tcs-offset = <0xd00>;
161 qcom,tcs-config = <ACTIVE_TCS 2>,
168 // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
169 // register offsets for DRV0 start at 01C00, the register calculations are
172 // TCS-OFFSET: 0x1C00
173 #include <dt-bindings/interrupt-controller/arm-gic.h>
174 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
177 compatible = "qcom,rpmh-rsc";
178 reg = <0xaf20000 0x10000>;
180 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
182 qcom,tcs-offset = <0x1c00>;
184 qcom,tcs-config = <ACTIVE_TCS 0>,
191 #include <dt-bindings/interrupt-controller/arm-gic.h>
192 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
193 #include <dt-bindings/power/qcom-rpmpd.h>
196 compatible = "qcom,rpmh-rsc";
197 reg = <0x18200000 0x10000>,
198 <0x18210000 0x10000>,
199 <0x18220000 0x10000>;
200 reg-names = "drv-0", "drv-1", "drv-2";
201 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
205 qcom,tcs-offset = <0xd00>;
207 qcom,tcs-config = <ACTIVE_TCS 2>,
213 compatible = "qcom,sm8350-rpmh-clk";
216 clocks = <&xo_board>;
220 compatible = "qcom,sm8350-rpmhpd";
221 #power-domain-cells = <1>;
222 operating-points-v2 = <&rpmhpd_opp_table>;
224 rpmhpd_opp_table: opp-table {
225 compatible = "operating-points-v2";
227 rpmhpd_opp_ret: opp1 {
228 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
231 rpmhpd_opp_min_svs: opp2 {
232 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
235 rpmhpd_opp_low_svs: opp3 {
236 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
239 rpmhpd_opp_svs: opp4 {
240 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
243 rpmhpd_opp_svs_l1: opp5 {
244 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
247 rpmhpd_opp_nom: opp6 {
248 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
251 rpmhpd_opp_nom_l1: opp7 {
252 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
255 rpmhpd_opp_nom_l2: opp8 {
256 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
259 rpmhpd_opp_turbo: opp9 {
260 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
263 rpmhpd_opp_turbo_l1: opp10 {
264 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
270 compatible = "qcom,bcm-voter";