Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: Qualcomm QMP PHY controller
   9
  10 maintainers:
  11   - Manu Gautam <mgautam@codeaurora.org>
  12
  13 description:
  14   QMP phy controller supports physical layer functionality for a number of
  15   controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
  16
  17 properties:
  18   compatible:
  19     enum:
  20       - qcom,ipq8074-qmp-pcie-phy
  21       - qcom,ipq8074-qmp-usb3-phy
  22       - qcom,msm8996-qmp-pcie-phy
  23       - qcom,msm8996-qmp-ufs-phy
  24       - qcom,msm8996-qmp-usb3-phy
  25       - qcom,msm8998-qmp-pcie-phy
  26       - qcom,msm8998-qmp-ufs-phy
  27       - qcom,msm8998-qmp-usb3-phy
  28       - qcom,sc8180x-qmp-ufs-phy
  29       - qcom,sc8180x-qmp-usb3-phy
  30       - qcom,sdm845-qhp-pcie-phy
  31       - qcom,sdm845-qmp-pcie-phy
  32       - qcom,sdm845-qmp-ufs-phy
  33       - qcom,sdm845-qmp-usb3-uni-phy
  34       - qcom,sm8150-qmp-ufs-phy
  35       - qcom,sm8150-qmp-usb3-phy
  36       - qcom,sm8150-qmp-usb3-uni-phy
  37       - qcom,sm8250-qmp-ufs-phy
  38       - qcom,sm8250-qmp-gen3x1-pcie-phy
  39       - qcom,sm8250-qmp-gen3x2-pcie-phy
  40       - qcom,sm8250-qmp-modem-pcie-phy
  41       - qcom,sm8250-qmp-usb3-phy
  42       - qcom,sm8250-qmp-usb3-uni-phy
  43       - qcom,sm8350-qmp-ufs-phy
  44       - qcom,sm8350-qmp-usb3-phy
  45       - qcom,sm8350-qmp-usb3-uni-phy
  46       - qcom,sdx55-qmp-usb3-uni-phy
  47
  48   reg:
  49     minItems: 1
  50     maxItems: 2
  51     items:
  52       - description: Address and length of PHY's common serdes block.
  53       - description: Address and length of PHY's DP_COM control block.
  54
  55   "#clock-cells":
  56     enum: [ 1, 2 ]
  57
  58   "#address-cells":
  59     enum: [ 1, 2 ]
  60
  61   "#size-cells":
  62     enum: [ 1, 2 ]
  63
  64   ranges: true
  65
  66   clocks:
  67     minItems: 1
  68     maxItems: 4
  69
  70   clock-names:
  71     minItems: 1
  72     maxItems: 4
  73
  74   resets:
  75     minItems: 1
  76     maxItems: 3
  77
  78   reset-names:
  79     minItems: 1
  80     maxItems: 3
  81
  82   vdda-phy-supply:
  83     description:
  84       Phandle to a regulator supply to PHY core block.
  85
  86   vdda-pll-supply:
  87     description:
  88       Phandle to 1.8V regulator supply to PHY refclk pll block.
  89
  90   vddp-ref-clk-supply:
  91     description:
  92       Phandle to a regulator supply to any specific refclk pll block.
  93
  94 #Required nodes:
  95 patternProperties:
  96   "^phy@[0-9a-f]+$":
  97     type: object
  98     description:
  99       Each device node of QMP phy is required to have as many child nodes as
 100       the number of lanes the PHY has.
 101
 102 required:
 103   - compatible
 104   - reg
 105   - "#clock-cells"
 106   - "#address-cells"
 107   - "#size-cells"
 108   - ranges
 109   - clocks
 110   - clock-names
 111   - resets
 112   - reset-names
 113   - vdda-phy-supply
 114   - vdda-pll-supply
 115
 116 additionalProperties: false
 117
 118 allOf:
 119   - if:
 120       properties:
 121         compatible:
 122           contains:
 123             enum:
 124               - qcom,sdm845-qmp-usb3-uni-phy
 125     then:
 126       properties:
 127         clocks:
 128           items:
 129             - description: Phy aux clock.
 130             - description: Phy config clock.
 131             - description: 19.2 MHz ref clk.
 132             - description: Phy common block aux clock.
 133         clock-names:
 134           items:
 135             - const: aux
 136             - const: cfg_ahb
 137             - const: ref
 138             - const: com_aux
 139         resets:
 140           items:
 141             - description: reset of phy block.
 142             - description: phy common block reset.
 143         reset-names:
 144           items:
 145             - const: phy
 146             - const: common
 147   - if:
 148       properties:
 149         compatible:
 150           contains:
 151             enum:
 152               - qcom,sdx55-qmp-usb3-uni-phy
 153     then:
 154       properties:
 155         clocks:
 156           items:
 157             - description: Phy aux clock.
 158             - description: Phy config clock.
 159             - description: 19.2 MHz ref clk.
 160         clock-names:
 161           items:
 162             - const: aux
 163             - const: cfg_ahb
 164             - const: ref
 165         resets:
 166           items:
 167             - description: reset of phy block.
 168             - description: phy common block reset.
 169         reset-names:
 170           items:
 171             - const: phy
 172             - const: common
 173   - if:
 174       properties:
 175         compatible:
 176           contains:
 177             enum:
 178               - qcom,msm8996-qmp-pcie-phy
 179     then:
 180       properties:
 181         clocks:
 182           items:
 183             - description: Phy aux clock.
 184             - description: Phy config clock.
 185             - description: 19.2 MHz ref clk.
 186         clock-names:
 187           items:
 188             - const: aux
 189             - const: cfg_ahb
 190             - const: ref
 191         resets:
 192           items:
 193             - description: reset of phy block.
 194             - description: phy common block reset.
 195             - description: phy's ahb cfg block reset.
 196         reset-names:
 197           items:
 198             - const: phy
 199             - const: common
 200             - const: cfg
 201   - if:
 202       properties:
 203         compatible:
 204           contains:
 205             enum:
 206               - qcom,ipq8074-qmp-usb3-phy
 207               - qcom,msm8996-qmp-usb3-phy
 208               - qcom,msm8998-qmp-pcie-phy
 209               - qcom,msm8998-qmp-usb3-phy
 210     then:
 211       properties:
 212         clocks:
 213           items:
 214             - description: Phy aux clock.
 215             - description: Phy config clock.
 216             - description: 19.2 MHz ref clk.
 217         clock-names:
 218           items:
 219             - const: aux
 220             - const: cfg_ahb
 221             - const: ref
 222         resets:
 223           items:
 224             - description: reset of phy block.
 225             - description: phy common block reset.
 226         reset-names:
 227           items:
 228             - const: phy
 229             - const: common
 230   - if:
 231       properties:
 232         compatible:
 233           contains:
 234             enum:
 235               - qcom,msm8996-qmp-ufs-phy
 236     then:
 237       properties:
 238         clocks:
 239           items:
 240             - description: 19.2 MHz ref clk.
 241         clock-names:
 242           items:
 243             - const: ref
 244         resets:
 245           items:
 246             - description: PHY reset in the UFS controller.
 247         reset-names:
 248           items:
 249             - const: ufsphy
 250   - if:
 251       properties:
 252         compatible:
 253           contains:
 254             enum:
 255               - qcom,msm8998-qmp-ufs-phy
 256               - qcom,sdm845-qmp-ufs-phy
 257               - qcom,sm8150-qmp-ufs-phy
 258               - qcom,sm8250-qmp-ufs-phy
 259     then:
 260       properties:
 261         clocks:
 262           items:
 263             - description: 19.2 MHz ref clk.
 264             - description: Phy reference aux clock.
 265         clock-names:
 266           items:
 267             - const: ref
 268             - const: ref_aux
 269         resets:
 270           items:
 271             - description: PHY reset in the UFS controller.
 272         reset-names:
 273           items:
 274             - const: ufsphy
 275   - if:
 276       properties:
 277         compatible:
 278           contains:
 279             enum:
 280               - qcom,ipq8074-qmp-pcie-phy
 281     then:
 282       properties:
 283         clocks:
 284           items:
 285             - description: pipe clk.
 286         clock-names:
 287           items:
 288             - const: pipe_clk
 289         resets:
 290           items:
 291             - description: reset of phy block.
 292             - description: phy common block reset.
 293         reset-names:
 294           items:
 295             - const: phy
 296             - const: common
 297   - if:
 298       properties:
 299         compatible:
 300           contains:
 301             enum:
 302               - qcom,sdm845-qhp-pcie-phy
 303               - qcom,sdm845-qmp-pcie-phy
 304               - qcom,sm8250-qmp-gen3x1-pcie-phy
 305               - qcom,sm8250-qmp-gen3x2-pcie-phy
 306               - qcom,sm8250-qmp-modem-pcie-phy
 307     then:
 308       properties:
 309         clocks:
 310           items:
 311             - description: Phy aux clock.
 312             - description: Phy config clock.
 313             - description: 19.2 MHz ref clk.
 314             - description: Phy refgen clk.
 315         clock-names:
 316           items:
 317             - const: aux
 318             - const: cfg_ahb
 319             - const: ref
 320             - const: refgen
 321         resets:
 322           items:
 323             - description: reset of phy block.
 324         reset-names:
 325           items:
 326             - const: phy
 327   - if:
 328       properties:
 329         compatible:
 330           contains:
 331             enum:
 332               - qcom,sm8150-qmp-usb3-phy
 333               - qcom,sm8150-qmp-usb3-uni-phy
 334               - qcom,sm8250-qmp-usb3-uni-phy
 335               - qcom,sm8350-qmp-usb3-uni-phy
 336     then:
 337       properties:
 338         clocks:
 339           items:
 340             - description: Phy aux clock.
 341             - description: 19.2 MHz ref clk source.
 342             - description: 19.2 MHz ref clk.
 343             - description: Phy common block aux clock.
 344         clock-names:
 345           items:
 346             - const: aux
 347             - const: ref_clk_src
 348             - const: ref
 349             - const: com_aux
 350         resets:
 351           items:
 352             - description: reset of phy block.
 353             - description: phy common block reset.
 354         reset-names:
 355           items:
 356             - const: phy
 357             - const: common
 358   - if:
 359       properties:
 360         compatible:
 361           contains:
 362             enum:
 363               - qcom,sm8250-qmp-usb3-phy
 364               - qcom,sm8350-qmp-usb3-phy
 365     then:
 366       properties:
 367         clocks:
 368           items:
 369             - description: Phy aux clock.
 370             - description: 19.2 MHz ref clk.
 371             - description: Phy common block aux clock.
 372         clock-names:
 373           items:
 374             - const: aux
 375             - const: ref_clk_src
 376             - const: com_aux
 377         resets:
 378           items:
 379             - description: reset of phy block.
 380             - description: phy common block reset.
 381         reset-names:
 382           items:
 383             - const: phy
 384             - const: common
 385
 386 examples:
 387   - |
 388     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 389     usb_2_qmpphy: phy-wrapper@88eb000 {
 390         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
 391         reg = <0x088eb000 0x18c>;
 392         #clock-cells = <1>;
 393         #address-cells = <1>;
 394         #size-cells = <1>;
 395         ranges = <0x0 0x088eb000 0x2000>;
 396
 397         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
 398                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 399                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
 400                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
 401         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
 402
 403         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
 404                  <&gcc GCC_USB3_PHY_SEC_BCR>;
 405         reset-names = "phy", "common";
 406
 407         vdda-phy-supply = <&vdda_usb2_ss_1p2>;
 408         vdda-pll-supply = <&vdda_usb2_ss_core>;
 409
 410         usb_2_ssphy: phy@200 {
 411                 reg = <0x200 0x128>,
 412                       <0x400 0x1fc>,
 413                       <0x800 0x218>,
 414                       <0x600 0x70>;
 415                 #clock-cells = <0>;
 416                 #phy-cells = <0>;
 417                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
 418                 clock-names = "pipe0";
 419                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
 420             };
 421         };