1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP PHY controller
11 - Vinod Koul <vkoul@kernel.org>
14 QMP phy controller supports physical layer functionality for a number of
15 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
20 - qcom,ipq6018-qmp-pcie-phy
21 - qcom,ipq6018-qmp-usb3-phy
22 - qcom,ipq8074-qmp-pcie-phy
23 - qcom,ipq8074-qmp-usb3-phy
24 - qcom,msm8996-qmp-pcie-phy
25 - qcom,msm8996-qmp-ufs-phy
26 - qcom,msm8996-qmp-usb3-phy
27 - qcom,msm8998-qmp-pcie-phy
28 - qcom,msm8998-qmp-ufs-phy
29 - qcom,msm8998-qmp-usb3-phy
30 - qcom,qcm2290-qmp-usb3-phy
31 - qcom,sc7180-qmp-usb3-phy
32 - qcom,sc8180x-qmp-pcie-phy
33 - qcom,sc8180x-qmp-ufs-phy
34 - qcom,sc8180x-qmp-usb3-phy
35 - qcom,sc8280xp-qmp-ufs-phy
36 - qcom,sdm845-qhp-pcie-phy
37 - qcom,sdm845-qmp-pcie-phy
38 - qcom,sdm845-qmp-ufs-phy
39 - qcom,sdm845-qmp-usb3-phy
40 - qcom,sdm845-qmp-usb3-uni-phy
41 - qcom,sm6115-qmp-ufs-phy
42 - qcom,sm8150-qmp-ufs-phy
43 - qcom,sm8150-qmp-usb3-phy
44 - qcom,sm8150-qmp-usb3-uni-phy
45 - qcom,sm8250-qmp-ufs-phy
46 - qcom,sm8250-qmp-gen3x1-pcie-phy
47 - qcom,sm8250-qmp-gen3x2-pcie-phy
48 - qcom,sm8250-qmp-modem-pcie-phy
49 - qcom,sm8250-qmp-usb3-phy
50 - qcom,sm8250-qmp-usb3-uni-phy
51 - qcom,sm8350-qmp-ufs-phy
52 - qcom,sm8350-qmp-usb3-phy
53 - qcom,sm8350-qmp-usb3-uni-phy
54 - qcom,sm8450-qmp-gen3x1-pcie-phy
55 - qcom,sm8450-qmp-gen4x2-pcie-phy
56 - qcom,sm8450-qmp-ufs-phy
57 - qcom,sm8450-qmp-usb3-phy
58 - qcom,sdx55-qmp-pcie-phy
59 - qcom,sdx55-qmp-usb3-uni-phy
64 - description: Address and length of PHY's common serdes block.
65 - description: Address and length of PHY's DP_COM control block.
96 Phandle to a regulator supply to PHY core block.
100 Phandle to 1.8V regulator supply to PHY refclk pll block.
104 Phandle to a regulator supply to any specific refclk pll block.
111 Each device node of QMP phy is required to have as many child nodes as
112 the number of lanes the PHY has.
126 additionalProperties: false
134 - qcom,sdm845-qmp-usb3-uni-phy
139 - description: Phy aux clock.
140 - description: Phy config clock.
141 - description: 19.2 MHz ref clk.
142 - description: Phy common block aux clock.
151 - description: reset of phy block.
152 - description: phy common block reset.
165 - qcom,sdx55-qmp-usb3-uni-phy
170 - description: Phy aux clock.
171 - description: Phy config clock.
172 - description: 19.2 MHz ref clk.
180 - description: reset of phy block.
181 - description: phy common block reset.
194 - qcom,msm8996-qmp-pcie-phy
199 - description: Phy aux clock.
200 - description: Phy config clock.
201 - description: 19.2 MHz ref clk.
209 - description: reset of phy block.
210 - description: phy common block reset.
211 - description: phy's ahb cfg block reset.
225 - qcom,ipq8074-qmp-usb3-phy
226 - qcom,msm8996-qmp-usb3-phy
227 - qcom,msm8998-qmp-pcie-phy
228 - qcom,msm8998-qmp-usb3-phy
233 - description: Phy aux clock.
234 - description: Phy config clock.
235 - description: 19.2 MHz ref clk.
243 - description: reset of phy block.
244 - description: phy common block reset.
257 - qcom,msm8996-qmp-ufs-phy
262 - description: 19.2 MHz ref clk.
268 - description: PHY reset in the UFS controller.
280 - qcom,msm8998-qmp-ufs-phy
281 - qcom,sdm845-qmp-ufs-phy
282 - qcom,sm8150-qmp-ufs-phy
283 - qcom,sm8250-qmp-ufs-phy
284 - qcom,sc8180x-qmp-ufs-phy
285 - qcom,sc8280xp-qmp-ufs-phy
290 - description: 19.2 MHz ref clk.
291 - description: Phy reference aux clock.
298 - description: PHY reset in the UFS controller.
310 - qcom,ipq6018-qmp-pcie-phy
311 - qcom,ipq8074-qmp-pcie-phy
316 - description: Phy aux clock.
317 - description: Phy config clock.
324 - description: reset of phy block.
325 - description: phy common block reset.
335 - qcom,sc8180x-qmp-pcie-phy
336 - qcom,sdm845-qhp-pcie-phy
337 - qcom,sdm845-qmp-pcie-phy
338 - qcom,sdx55-qmp-pcie-phy
339 - qcom,sm8250-qmp-gen3x1-pcie-phy
340 - qcom,sm8250-qmp-gen3x2-pcie-phy
341 - qcom,sm8250-qmp-modem-pcie-phy
342 - qcom,sm8450-qmp-gen3x1-pcie-phy
343 - qcom,sm8450-qmp-gen4x2-pcie-phy
348 - description: Phy aux clock.
349 - description: Phy config clock.
350 - description: 19.2 MHz ref clk.
351 - description: Phy refgen clk.
360 - description: reset of phy block.
372 - qcom,sm8150-qmp-usb3-phy
373 - qcom,sm8150-qmp-usb3-uni-phy
374 - qcom,sm8250-qmp-usb3-uni-phy
375 - qcom,sm8350-qmp-usb3-uni-phy
380 - description: Phy aux clock.
381 - description: 19.2 MHz ref clk source.
382 - description: 19.2 MHz ref clk.
383 - description: Phy common block aux clock.
392 - description: reset of phy block.
393 - description: phy common block reset.
406 - qcom,sm8250-qmp-usb3-phy
407 - qcom,sm8350-qmp-usb3-phy
412 - description: Phy aux clock.
413 - description: 19.2 MHz ref clk.
414 - description: Phy common block aux clock.
422 - description: reset of phy block.
423 - description: phy common block reset.
436 - qcom,qcm2290-qmp-usb3-phy
441 - description: Phy config clock.
442 - description: 19.2 MHz ref clk.
443 - description: Phy common block aux clock.
451 - description: phy_phy reset.
452 - description: reset of phy block.
463 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
464 usb_2_qmpphy: phy-wrapper@88eb000 {
465 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
466 reg = <0x088eb000 0x18c>;
468 #address-cells = <1>;
470 ranges = <0x0 0x088eb000 0x2000>;
472 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
473 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
474 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
475 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
476 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
478 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
479 <&gcc GCC_USB3_PHY_SEC_BCR>;
480 reset-names = "phy", "common";
482 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
483 vdda-pll-supply = <&vdda_usb2_ss_core>;
485 usb_2_ssphy: phy@200 {
492 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
493 clock-names = "pipe0";
494 clock-output-names = "usb3_uni_phy_pipe_clk_src";