1 * Synopsys Designware PCIe interface
4 - compatible: should contain "snps,dw-pcie" to identify the
5 core, plus an identifier for the specific instance, such
6 as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".
7 - reg: base addresses and lengths of the pcie controller,
8 the phy controller, additional register for the phy controller.
9 - interrupts: interrupt values for level interrupt,
10 pulse interrupt, special interrupt.
11 - clocks: from common clock binding: handle to pci clock.
12 - clock-names: from common clock binding: should be "pcie" and "pcie_bus".
13 - #address-cells: set to <3>
14 - #size-cells: set to <2>
15 - device_type: set to "pci"
16 - ranges: ranges for the PCI memory and I/O regions
17 - #interrupt-cells: set to <1>
18 - interrupt-map-mask and interrupt-map: standard PCI properties
19 to define the mapping of the PCIe interface to interrupt
21 - num-lanes: number of lanes to use
24 - reset-gpio: gpio pin number of power good signal
26 Optional properties for fsl,imx6q-pcie
27 - power-on-gpio: gpio pin number of power-enable signal
28 - wake-up-gpio: gpio pin number of incoming wakeup signal
29 - disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal
33 SoC specific DT Entry:
36 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
37 reg = <0x290000 0x1000
40 interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
41 clocks = <&clock 28>, <&clock 27>;
42 clock-names = "pcie", "pcie_bus";
46 ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
47 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
48 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
49 #interrupt-cells = <1>;
50 interrupt-map-mask = <0 0 0 0>;
51 interrupt-map = <0x0 0 &gic 53>;
56 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
57 reg = <0x2a0000 0x1000
60 interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
61 clocks = <&clock 29>, <&clock 27>;
62 clock-names = "pcie", "pcie_bus";
66 ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
67 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
68 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
69 #interrupt-cells = <1>;
70 interrupt-map-mask = <0 0 0 0>;
71 interrupt-map = <0x0 0 &gic 56>;
75 Board specific DT Entry:
78 reset-gpio = <&pin_ctrl 5 0>;
82 reset-gpio = <&pin_ctrl 22 0>;