1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
15 communication and can be configured as an ethernet switch. It provides the
16 gigabit media independent interface (GMII),reduced gigabit media
17 independent interface (RGMII), reduced media independent interface (RMII),
18 the management data input output (MDIO) for physical layer device (PHY)
24 - const: ti,cpsw-switch
26 - const: ti,am335x-cpsw-switch
27 - const: ti,cpsw-switch
29 - const: ti,am4372-cpsw-switch
30 - const: ti,cpsw-switch
32 - const: ti,dra7-cpsw-switch
33 - const: ti,cpsw-switch
38 The physical base address and size of full the CPSW module IO range
50 description: CPSW functional clock
58 - description: RX_THRESH interrupt
59 - description: RX interrupt
60 - description: TX interrupt
61 - description: MISC interrupt
73 $ref: /schemas/types.yaml#/definitions/phandle
75 Phandle to the system control device node which provides access to
76 efuse IO range with MAC addresses
89 description: CPSW external ports
91 $ref: ethernet-controller.yaml#
97 description: CPSW port number
101 description: phandle on phy-gmii-sel PHY
104 description: label associated with this port
107 $ref: /schemas/types.yaml#/definitions/uint32
111 Specifies default PORT VID to be used to segregate
112 ports. Default value - CPSW port number.
121 The Common Platform Time Sync (CPTS) module
126 description: CPTS reference clock
133 $ref: /schemas/types.yaml#/definitions/uint32
135 Numerator to convert input clock ticks into ns
138 $ref: /schemas/types.yaml#/definitions/uint32
140 Denominator to convert input clock ticks into ns.
141 Mult and shift will be calculated basing on CPTS rftclk frequency if
142 both cpts_clock_shift and cpts_clock_mult properties are not provided.
153 $ref: "ti,davinci-mdio.yaml#"
167 additionalProperties: false
171 #include <dt-bindings/interrupt-controller/irq.h>
172 #include <dt-bindings/interrupt-controller/arm-gic.h>
173 #include <dt-bindings/clock/dra7.h>
176 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
178 ranges = <0 0 0x4000>;
179 clocks = <&gmac_main_clk>;
181 #address-cells = <1>;
183 syscon = <&scm_conf>;
185 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
189 interrupt-names = "rx_thresh", "rx", "tx", "misc";
192 #address-cells = <1>;
198 mac-address = [ 00 00 00 00 00 00 ];
199 phys = <&phy_gmii_sel 1>;
200 phy-handle = <ðphy0_sw>;
202 ti,dual-emac-pvid = <1>;
208 mac-address = [ 00 00 00 00 00 00 ];
209 phys = <&phy_gmii_sel 2>;
210 phy-handle = <ðphy1_sw>;
212 ti,dual-emac-pvid = <2>;
216 davinci_mdio_sw: mdio@1000 {
217 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
218 reg = <0x1000 0x100>;
219 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
221 #address-cells = <1>;
223 bus_freq = <1000000>;
225 ethphy0_sw: ethernet-phy@0 {
229 ethphy1_sw: ethernet-phy@1 {
235 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
236 clock-names = "cpts";