3 Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
4 supports high resolution encoding and decoding functionalities.
7 - compatible : must be one of the following string:
8 "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder.
9 "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
10 "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
11 "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
12 "mediatek,mt8192-vcodec-enc" for MT8192 encoder.
13 - reg : Physical base address of the video codec registers and length of
15 - interrupts : interrupt number to the cpu.
16 - mediatek,larb : must contain the local arbiters in the current Socs.
17 - clocks : list of clock specifiers, corresponding to entries in
18 the clock-names property.
19 - clock-names: avc encoder must contain "venc_sel", vp8 encoder must
20 contain "venc_lt_sel", decoder must contain "vcodecpll", "univpll_d2",
21 "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel",
23 - iommus : should point to the respective IOMMU block with master port as
24 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
26 - dma-ranges : describes the dma address range space that the codec hw access.
27 One of the two following nodes:
28 - mediatek,vpu : the node of the video processor unit, if using VPU.
29 - mediatek,scp : the node of the SCP unit, if using SCP.
34 vcodec_dec: vcodec@16000000 {
35 compatible = "mediatek,mt8173-vcodec-dec";
36 reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
37 <0 0x16020000 0 0x1000>, /*VDEC_MISC*/
38 <0 0x16021000 0 0x800>, /*VDEC_LD*/
39 <0 0x16021800 0 0x800>, /*VDEC_TOP*/
40 <0 0x16022000 0 0x1000>, /*VDEC_CM*/
41 <0 0x16023000 0 0x1000>, /*VDEC_AD*/
42 <0 0x16024000 0 0x1000>, /*VDEC_AV*/
43 <0 0x16025000 0 0x1000>, /*VDEC_PP*/
44 <0 0x16026800 0 0x800>, /*VP8_VD*/
45 <0 0x16027000 0 0x800>, /*VP6_VD*/
46 <0 0x16027800 0 0x800>, /*VP8_VL*/
47 <0 0x16028400 0 0x400>; /*VP9_VD*/
48 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
49 mediatek,larb = <&larb1>;
50 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
51 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
52 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
53 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
54 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
55 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
56 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
57 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
58 mediatek,vpu = <&vpu>;
59 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
60 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
61 <&topckgen CLK_TOP_UNIVPLL_D2>,
62 <&topckgen CLK_TOP_CCI400_SEL>,
63 <&topckgen CLK_TOP_VDEC_SEL>,
64 <&topckgen CLK_TOP_VCODECPLL>,
65 <&apmixedsys CLK_APMIXED_VENCPLL>,
66 <&topckgen CLK_TOP_VENC_LT_SEL>,
67 <&topckgen CLK_TOP_VCODECPLL_370P5>;
68 clock-names = "vcodecpll",
76 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
77 <&topckgen CLK_TOP_CCI400_SEL>,
78 <&topckgen CLK_TOP_VDEC_SEL>,
79 <&apmixedsys CLK_APMIXED_VCODECPLL>,
80 <&apmixedsys CLK_APMIXED_VENCPLL>;
81 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
82 <&topckgen CLK_TOP_UNIVPLL_D2>,
83 <&topckgen CLK_TOP_VCODECPLL>;
84 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
87 vcodec_enc_avc: vcodec@18002000 {
88 compatible = "mediatek,mt8173-vcodec-enc";
89 reg = <0 0x18002000 0 0x1000>;
90 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
91 iommus = <&iommu M4U_PORT_VENC_RCPU>,
92 <&iommu M4U_PORT_VENC_REC>,
93 <&iommu M4U_PORT_VENC_BSDMA>,
94 <&iommu M4U_PORT_VENC_SV_COMV>,
95 <&iommu M4U_PORT_VENC_RD_COMV>,
96 <&iommu M4U_PORT_VENC_CUR_LUMA>,
97 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
98 <&iommu M4U_PORT_VENC_REF_LUMA>,
99 <&iommu M4U_PORT_VENC_REF_CHROMA>,
100 <&iommu M4U_PORT_VENC_NBM_RDMA>,
101 <&iommu M4U_PORT_VENC_NBM_WDMA>;
102 mediatek,larb = <&larb3>;
103 mediatek,vpu = <&vpu>;
104 clocks = <&topckgen CLK_TOP_VENC_SEL>;
105 clock-names = "venc_sel";
106 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
107 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
110 vcodec_enc_vp8: vcodec@19002000 {
111 compatible = "mediatek,mt8173-vcodec-enc-vp8";
112 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
113 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
114 iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
115 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
116 <&iommu M4U_PORT_VENC_BSDMA_SET2>,
117 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
118 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
119 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
120 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
121 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
122 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
123 mediatek,larb = <&larb5>;
124 mediatek,vpu = <&vpu>;
125 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
126 clock-names = "venc_lt_sel";
127 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
128 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;