Documentation/devicetree/bindings/media/mediatek-vcodec.txt

   1 Mediatek Video Codec
   2
   3 Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
   4 supports high resolution encoding and decoding functionalities.
   5
   6 Required properties:
   7 - compatible : must be one of the following string:
   8   "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder.
   9   "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
  10   "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
  11   "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
  12 - reg : Physical base address of the video codec registers and length of
  13   memory mapped region.
  14 - interrupts : interrupt number to the cpu.
  15 - mediatek,larb : must contain the local arbiters in the current Socs.
  16 - clocks : list of clock specifiers, corresponding to entries in
  17   the clock-names property.
  18 - clock-names: avc encoder must contain "venc_sel", vp8 encoder must
  19   contain "venc_lt_sel", decoder must contain "vcodecpll", "univpll_d2",
  20   "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel",
  21   "vdec_bus_clk_src".
  22 - iommus : should point to the respective IOMMU block with master port as
  23   argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
  24   for details.
  25 One of the two following nodes:
  26 - mediatek,vpu : the node of the video processor unit, if using VPU.
  27 - mediatek,scp : the node of the SCP unit, if using SCP.
  28
  29
  30 Example:
  31
  32 vcodec_dec: vcodec@16000000 {
  33     compatible = "mediatek,mt8173-vcodec-dec";
  34     reg = <0 0x16000000 0 0x100>,   /*VDEC_SYS*/
  35           <0 0x16020000 0 0x1000>,  /*VDEC_MISC*/
  36           <0 0x16021000 0 0x800>,   /*VDEC_LD*/
  37           <0 0x16021800 0 0x800>,   /*VDEC_TOP*/
  38           <0 0x16022000 0 0x1000>,  /*VDEC_CM*/
  39           <0 0x16023000 0 0x1000>,  /*VDEC_AD*/
  40           <0 0x16024000 0 0x1000>,  /*VDEC_AV*/
  41           <0 0x16025000 0 0x1000>,  /*VDEC_PP*/
  42           <0 0x16026800 0 0x800>,   /*VP8_VD*/
  43           <0 0x16027000 0 0x800>,   /*VP6_VD*/
  44           <0 0x16027800 0 0x800>,   /*VP8_VL*/
  45           <0 0x16028400 0 0x400>;   /*VP9_VD*/
  46     interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
  47     mediatek,larb = <&larb1>;
  48     iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
  49              <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
  50              <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
  51              <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
  52              <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
  53              <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
  54              <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
  55              <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
  56     mediatek,vpu = <&vpu>;
  57     power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
  58     clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
  59              <&topckgen CLK_TOP_UNIVPLL_D2>,
  60              <&topckgen CLK_TOP_CCI400_SEL>,
  61              <&topckgen CLK_TOP_VDEC_SEL>,
  62              <&topckgen CLK_TOP_VCODECPLL>,
  63              <&apmixedsys CLK_APMIXED_VENCPLL>,
  64              <&topckgen CLK_TOP_VENC_LT_SEL>,
  65              <&topckgen CLK_TOP_VCODECPLL_370P5>;
  66     clock-names = "vcodecpll",
  67                   "univpll_d2",
  68                   "clk_cci400_sel",
  69                   "vdec_sel",
  70                   "vdecpll",
  71                   "vencpll",
  72                   "venc_lt_sel",
  73                   "vdec_bus_clk_src";
  74     assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
  75                       <&topckgen CLK_TOP_CCI400_SEL>,
  76                       <&topckgen CLK_TOP_VDEC_SEL>,
  77                       <&apmixedsys CLK_APMIXED_VCODECPLL>,
  78                       <&apmixedsys CLK_APMIXED_VENCPLL>;
  79     assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
  80                              <&topckgen CLK_TOP_UNIVPLL_D2>,
  81                              <&topckgen CLK_TOP_VCODECPLL>;
  82     assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
  83   };
  84
  85 vcodec_enc_avc: vcodec@18002000 {
  86     compatible = "mediatek,mt8173-vcodec-enc";
  87     reg = <0 0x18002000 0 0x1000>;
  88     interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
  89     iommus = <&iommu M4U_PORT_VENC_RCPU>,
  90              <&iommu M4U_PORT_VENC_REC>,
  91              <&iommu M4U_PORT_VENC_BSDMA>,
  92              <&iommu M4U_PORT_VENC_SV_COMV>,
  93              <&iommu M4U_PORT_VENC_RD_COMV>,
  94              <&iommu M4U_PORT_VENC_CUR_LUMA>,
  95              <&iommu M4U_PORT_VENC_CUR_CHROMA>,
  96              <&iommu M4U_PORT_VENC_REF_LUMA>,
  97              <&iommu M4U_PORT_VENC_REF_CHROMA>,
  98              <&iommu M4U_PORT_VENC_NBM_RDMA>,
  99              <&iommu M4U_PORT_VENC_NBM_WDMA>;
 100     mediatek,larb = <&larb3>;
 101     mediatek,vpu = <&vpu>;
 102     clocks = <&topckgen CLK_TOP_VENC_SEL>;
 103     clock-names = "venc_sel";
 104     assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
 105     assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
 106   };
 107
 108 vcodec_enc_vp8: vcodec@19002000 {
 109     compatible = "mediatek,mt8173-vcodec-enc-vp8";
 110     reg =  <0 0x19002000 0 0x1000>;     /* VENC_LT_SYS */
 111     interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
 112     iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
 113              <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
 114              <&iommu M4U_PORT_VENC_BSDMA_SET2>,
 115              <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
 116              <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
 117              <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
 118              <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
 119              <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
 120              <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
 121     mediatek,larb = <&larb5>;
 122     mediatek,vpu = <&vpu>;
 123     clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
 124     clock-names = "venc_lt_sel";
 125     assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
 126     assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
 127   };