1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX Messaging Unit (MU)
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The Messaging Unit module enables two processors within the SoC to
14 communicate and coordinate by passing messages (e.g. data, status
15 and control) through the MU interface. The MU also provides the ability
16 for one processor to signal the other processor using interrupts.
18 Because the MU manages the messaging between processors, the MU uses
19 different clocks (from each side of the different peripheral buses).
20 Therefore, the MU must synchronize the accesses from one side to the
21 other. The MU accomplishes synchronization using two sets of matching
22 registers (Processor A-facing, Processor B-facing).
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
29 - const: fsl,imx8ulp-mu
30 - const: fsl,imx8-mu-scu
31 - const: fsl,imx8ulp-mu-s4
41 - const: fsl,imx6sx-mu
42 - description: To communicate with i.MX8 SCU with fast IPC
44 - const: fsl,imx8-mu-scu
48 - const: fsl,imx6sx-mu
58 <&phandle type channel>
59 phandle : Label name of controller
61 channel : Channel number
63 This MU support 4 type of unidirectional channels, each type
64 has 4 channels. A total of 16 channels. Following types are
66 0 - TX channel with 32bit transmit register and IRQ transmit
67 acknowledgment support.
68 1 - RX channel with 32bit receive register and IRQ support
69 2 - TX doorbell channel. Without own register and no ACK support.
70 3 - RX doorbell channel.
77 description: boolean, if present, means it is for side B MU.
89 additionalProperties: false
93 #include <dt-bindings/interrupt-controller/arm-gic.h>
96 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
97 reg = <0x5d1b0000 0x10000>;
98 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;