1 Qualcomm Camera Control Interface (CCI) I2C controller
8 Definition: must be one of:
17 Value type: <prop-encoded-array>
18 Definition: base address CCI I2C controller and length of memory
23 Value type: <prop-encoded-array>
24 Definition: specifies the CCI I2C interrupt. The format of the
25 specifier is defined by the binding document describing
26 the node's interrupt parent.
30 Value type: <prop-encoded-array>
31 Definition: a list of phandle, should contain an entry for each
32 entries in clock-names.
37 Definition: a list of clock names, must include "cci" clock.
40 Usage: required for "qcom,msm8996-cci"
41 Value type: <prop-encoded-array>
46 The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996,
47 sdm845, sm8250 and sm8450), described as subdevices named "i2c-bus@0" and
55 Definition: Index of the CCI bus/master
60 Definition: Desired I2C bus clock frequency in Hz, defaults to 100
66 compatible = "qcom,msm8996-cci";
69 reg = <0xa0c000 0x1000>;
70 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
71 clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
72 <&mmcc CAMSS_TOP_AHB_CLK>,
73 <&mmcc CAMSS_CCI_AHB_CLK>,
74 <&mmcc CAMSS_CCI_CLK>,
75 <&mmcc CAMSS_AHB_CLK>;
76 clock-names = "mmss_mmagic_ahb",
84 clock-frequency = <400000>;
91 clock-frequency = <400000>;