Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Global Clock & Reset Controller on IPQ9574
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Anusha Rao <quic_anusha@quicinc.com>
  12
  13 description: |
  14   Qualcomm global clock control module provides the clocks, resets and power
  15   domains on IPQ9574
  16
  17   See also::
  18     include/dt-bindings/clock/qcom,ipq9574-gcc.h
  19     include/dt-bindings/reset/qcom,ipq9574-gcc.h
  20
  21 properties:
  22   compatible:
  23     const: qcom,ipq9574-gcc
  24
  25   clocks:
  26     items:
  27       - description: Board XO source
  28       - description: Sleep clock source
  29       - description: Bias PLL ubi clock source
  30       - description: PCIE30 PHY0 pipe clock source
  31       - description: PCIE30 PHY1 pipe clock source
  32       - description: PCIE30 PHY2 pipe clock source
  33       - description: PCIE30 PHY3 pipe clock source
  34       - description: USB3 PHY pipe clock source
  35
  36 required:
  37   - compatible
  38   - clocks
  39
  40 allOf:
  41   - $ref: qcom,gcc.yaml#
  42
  43 unevaluatedProperties: false
  44
  45 examples:
  46   - |
  47     clock-controller@1800000 {
  48       compatible = "qcom,ipq9574-gcc";
  49       reg = <0x01800000 0x80000>;
  50       clocks = <&xo_board_clk>,
  51                <&sleep_clk>,
  52                <&bias_pll_ubi_nc_clk>,
  53                <&pcie30_phy0_pipe_clk>,
  54                <&pcie30_phy1_pipe_clk>,
  55                <&pcie30_phy2_pipe_clk>,
  56                <&pcie30_phy3_pipe_clk>,
  57                <&usb3phy_0_cc_pipe_clk>;
  58       #clock-cells = <1>;
  59       #reset-cells = <1>;
  60       #power-domain-cells = <1>;
  61     };
  62 ...