1 NXP i.MX System Controller Firmware (SCFW)
2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
6 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
7 (QM, QP), and i.MX8QX (QXP, DX).
9 The AP communicates with the SC using a multi-ported MU module found
10 in the LSIO subsystem. The current definition of this MU module provides
11 5 remote AP connections to the SC to support up to 5 execution environments
12 (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
13 with the LSIO DSC IP bus. The SC firmware will communicate with this MU
16 System Controller Device Node:
17 ============================================================
19 The scu node with the following properties shall be under the /firmware/ node.
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
25 "rx0", "rx1", "rx2", "rx3".
26 - mboxes: List of phandle of 4 MU channels for tx and 4 MU channels
27 for rx. All 8 MU channels must be in the same MU instance.
28 Cross instances are not allowed. The MU instance can only
29 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
30 to make sure use the one which is not conflict with other
31 execution environments. e.g. ATF.
33 Channel 0 must be "tx0" or "rx0".
34 Channel 1 must be "tx1" or "rx1".
35 Channel 2 must be "tx2" or "rx2".
36 Channel 3 must be "tx3" or "rx3".
38 mboxes = <&lsio_mu1 0 0
46 See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
47 for detailed mailbox binding.
49 i.MX SCU Client Device Node:
50 ============================================================
52 Client nodes are maintained as children of the relevant IMX-SCU device node.
54 Power domain bindings based on SCU Message Protocol
55 ------------------------------------------------------------
57 This binding for the SCU power domain providers uses the generic power
61 - compatible: Should be "fsl,imx8qxp-scu-pd".
62 - #power-domain-cells: Must be 1. Contains the Resource ID used by
64 See detailed Resource ID list from:
65 include/dt-bindings/firmware/imx/rsrc.h
67 Clock bindings based on SCU Message Protocol
68 ------------------------------------------------------------
70 This binding uses the common clock binding[1].
73 - compatible: Should be "fsl,imx8qxp-clock".
74 - #clock-cells: Should be 1. Contains the Clock ID value.
75 - clocks: List of clock specifiers, must contain an entry for
76 each required entry in clock-names
77 - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
79 The clock consumer should specify the desired clock by having the clock
80 ID in its "clocks" phandle cell.
82 See the full list of clock IDs from:
83 include/dt-bindings/clock/imx8qxp-clock.h
85 Pinctrl bindings based on SCU Message Protocol
86 ------------------------------------------------------------
88 This binding uses the i.MX common pinctrl binding[3].
91 - compatible: Should be one of:
95 Required properties for Pinctrl sub nodes:
96 - fsl,pins: Each entry consists of 3 integers which represents
97 the mux and config setting for one pin. The first 2
98 integers <pin_id mux_mode> are specified using a
99 PIN_FUNC_ID macro, which can be found in
100 <dt-bindings/pinctrl/pads-imx8qm.h>,
101 <dt-bindings/pinctrl/pads-imx8qxp.h>.
102 The last integer CONFIG is the pad setting value like
105 Please refer to i.MX8QXP Reference Manual for detailed
108 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
109 [2] Documentation/devicetree/bindings/power/power_domain.txt
110 [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
112 RTC bindings based on SCU Message Protocol
113 ------------------------------------------------------------
116 - compatible: should be "fsl,imx8qxp-sc-rtc";
120 lsio_mu1: mailbox@5d1c0000 {
127 compatible = "fsl,imx-scu";
128 mbox-names = "tx0", "tx1", "tx2", "tx3",
129 "rx0", "rx1", "rx2", "rx3";
130 mboxes = <&lsio_mu1 0 0
140 compatible = "fsl,imx8qxp-clk";
145 compatible = "fsl,imx8qxp-iomuxc";
147 pinctrl_lpuart0: lpuart0grp {
149 SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
150 SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
157 compatible = "fsl,imx8qxp-scu-pd";
158 #power-domain-cells = <1>;
162 compatible = "fsl,imx8qxp-sc-rtc";
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_lpuart0>;
171 clocks = <&clk IMX8QXP_UART0_CLK>,
172 <&clk IMX8QXP_UART0_IPG_CLK>;
173 clock-names = "per", "ipg";
174 power-domains = <&pd IMX_SC_R_UART_0>;