4 ========================================
5 eBPF Instruction Set Specification, v1.0
6 ========================================
8 This document specifies version 1.0 of the eBPF instruction set.
10 Documentation conventions
11 =========================
13 For brevity and consistency, this document refers to families
14 of types using a shorthand syntax and refers to several expository,
15 mnemonic functions when describing the semantics of instructions.
16 The range of valid values for those types and the semantics of those
17 functions are defined in the following subsections.
21 This document refers to integer types with the notation `SN` to specify
22 a type's signedness (`S`) and bit width (`N`), respectively.
24 .. table:: Meaning of signedness notation.
33 .. table:: Meaning of bit-width notation.
45 For example, `u32` is a type whose valid values are all the 32-bit unsigned
46 numbers and `s16` is a types whose valid values are all the 16-bit signed
51 * `htobe16`: Takes an unsigned 16-bit number in host-endian format and
52 returns the equivalent number as an unsigned 16-bit number in big-endian
54 * `htobe32`: Takes an unsigned 32-bit number in host-endian format and
55 returns the equivalent number as an unsigned 32-bit number in big-endian
57 * `htobe64`: Takes an unsigned 64-bit number in host-endian format and
58 returns the equivalent number as an unsigned 64-bit number in big-endian
60 * `htole16`: Takes an unsigned 16-bit number in host-endian format and
61 returns the equivalent number as an unsigned 16-bit number in little-endian
63 * `htole32`: Takes an unsigned 32-bit number in host-endian format and
64 returns the equivalent number as an unsigned 32-bit number in little-endian
66 * `htole64`: Takes an unsigned 64-bit number in host-endian format and
67 returns the equivalent number as an unsigned 64-bit number in little-endian
69 * `bswap16`: Takes an unsigned 16-bit number in either big- or little-endian
70 format and returns the equivalent number with the same bit width but
72 * `bswap32`: Takes an unsigned 32-bit number in either big- or little-endian
73 format and returns the equivalent number with the same bit width but
75 * `bswap64`: Takes an unsigned 64-bit number in either big- or little-endian
76 format and returns the equivalent number with the same bit width but
86 To `sign extend an` ``X`` `-bit number, A, to a` ``Y`` `-bit number, B ,` means to
88 #. Copy all ``X`` bits from `A` to the lower ``X`` bits of `B`.
89 #. Set the value of the remaining ``Y`` - ``X`` bits of `B` to the value of
90 the most-significant bit of `A`.
92 .. admonition:: Example
94 Sign extend an 8-bit number ``A`` to a 16-bit number ``B`` on a big-endian platform:
100 Registers and calling convention
101 ================================
103 eBPF has 10 general purpose registers and a read-only frame pointer register,
104 all of which are 64-bits wide.
106 The eBPF calling convention is defined as:
108 * R0: return value from function calls, and exit value for eBPF programs
109 * R1 - R5: arguments for function calls
110 * R6 - R9: callee saved registers that function calls will preserve
111 * R10: read-only frame pointer to access stack
113 R0 - R5 are scratch registers and eBPF programs needs to spill/fill them if
114 necessary across calls.
119 eBPF has two instruction encodings:
121 * the basic instruction encoding, which uses 64 bits to encode an instruction
122 * the wide instruction encoding, which appends a second 64-bit immediate (i.e.,
123 constant) value after the basic instruction for a total of 128 bits.
125 The fields conforming an encoded basic instruction are stored in the
128 opcode:8 src_reg:4 dst_reg:4 offset:16 imm:32 // In little-endian BPF.
129 opcode:8 dst_reg:4 src_reg:4 offset:16 imm:32 // In big-endian BPF.
132 signed integer immediate value
135 signed integer offset used with pointer arithmetic
138 the source register number (0-10), except where otherwise specified
139 (`64-bit immediate instructions`_ reuse this field for other purposes)
142 destination register number (0-10)
147 Note that the contents of multi-byte fields ('imm' and 'offset') are
148 stored using big-endian byte ordering in big-endian BPF and
149 little-endian byte ordering in little-endian BPF.
153 opcode offset imm assembly
155 07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little
157 07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big
159 Note that most instructions do not use all of the fields.
160 Unused fields shall be cleared to zero.
162 As discussed below in `64-bit immediate instructions`_, a 64-bit immediate
163 instruction uses a 64-bit immediate value that is constructed as follows.
164 The 64 bits following the basic instruction contain a pseudo instruction
165 using the same format but with opcode, dst_reg, src_reg, and offset all set to zero,
166 and imm containing the high 32 bits of the immediate value.
168 This is depicted in the following figure::
171 .-----------------------------.
173 code:8 regs:8 offset:16 imm:32 unused:32 imm:32
178 Thus the 64-bit immediate value is constructed as follows:
180 imm64 = (next_imm << 32) | imm
182 where 'next_imm' refers to the imm value of the pseudo instruction
183 following the basic instruction. The unused bytes in the pseudo
184 instruction are reserved and shall be cleared to zero.
189 The three LSB bits of the 'opcode' field store the instruction class:
191 ========= ===== =============================== ===================================
192 class value description reference
193 ========= ===== =============================== ===================================
194 BPF_LD 0x00 non-standard load operations `Load and store instructions`_
195 BPF_LDX 0x01 load into register operations `Load and store instructions`_
196 BPF_ST 0x02 store from immediate operations `Load and store instructions`_
197 BPF_STX 0x03 store from register operations `Load and store instructions`_
198 BPF_ALU 0x04 32-bit arithmetic operations `Arithmetic and jump instructions`_
199 BPF_JMP 0x05 64-bit jump operations `Arithmetic and jump instructions`_
200 BPF_JMP32 0x06 32-bit jump operations `Arithmetic and jump instructions`_
201 BPF_ALU64 0x07 64-bit arithmetic operations `Arithmetic and jump instructions`_
202 ========= ===== =============================== ===================================
204 Arithmetic and jump instructions
205 ================================
207 For arithmetic and jump instructions (``BPF_ALU``, ``BPF_ALU64``, ``BPF_JMP`` and
208 ``BPF_JMP32``), the 8-bit 'opcode' field is divided into three parts:
210 ============== ====== =================
211 4 bits (MSB) 1 bit 3 bits (LSB)
212 ============== ====== =================
213 code source instruction class
214 ============== ====== =================
217 the operation code, whose meaning varies by instruction class
220 the source operand location, which unless otherwise specified is one of:
222 ====== ===== ==============================================
223 source value description
224 ====== ===== ==============================================
225 BPF_K 0x00 use 32-bit 'imm' value as source operand
226 BPF_X 0x08 use 'src_reg' register value as source operand
227 ====== ===== ==============================================
229 **instruction class**
230 the instruction class (see `Instruction classes`_)
232 Arithmetic instructions
233 -----------------------
235 ``BPF_ALU`` uses 32-bit wide operands while ``BPF_ALU64`` uses 64-bit wide operands for
236 otherwise identical operations.
237 The 'code' field encodes the operation as below, where 'src' and 'dst' refer
238 to the values of the source and destination registers, respectively.
240 ========= ===== ======= ==========================================================
241 code value offset description
242 ========= ===== ======= ==========================================================
243 BPF_ADD 0x00 0 dst += src
244 BPF_SUB 0x10 0 dst -= src
245 BPF_MUL 0x20 0 dst \*= src
246 BPF_DIV 0x30 0 dst = (src != 0) ? (dst / src) : 0
247 BPF_SDIV 0x30 1 dst = (src != 0) ? (dst s/ src) : 0
248 BPF_OR 0x40 0 dst \|= src
249 BPF_AND 0x50 0 dst &= src
250 BPF_LSH 0x60 0 dst <<= (src & mask)
251 BPF_RSH 0x70 0 dst >>= (src & mask)
252 BPF_NEG 0x80 0 dst = -dst
253 BPF_MOD 0x90 0 dst = (src != 0) ? (dst % src) : dst
254 BPF_SMOD 0x90 1 dst = (src != 0) ? (dst s% src) : dst
255 BPF_XOR 0xa0 0 dst ^= src
256 BPF_MOV 0xb0 0 dst = src
257 BPF_MOVSX 0xb0 8/16/32 dst = (s8,s16,s32)src
258 BPF_ARSH 0xc0 0 :term:`sign extending<Sign Extend>` dst >>= (src & mask)
259 BPF_END 0xd0 0 byte swap operations (see `Byte swap instructions`_ below)
260 ========= ===== ======= ==========================================================
262 Underflow and overflow are allowed during arithmetic operations, meaning
263 the 64-bit or 32-bit value will wrap. If eBPF program execution would
264 result in division by zero, the destination register is instead set to zero.
265 If execution would result in modulo by zero, for ``BPF_ALU64`` the value of
266 the destination register is unchanged whereas for ``BPF_ALU`` the upper
267 32 bits of the destination register are zeroed.
269 ``BPF_ADD | BPF_X | BPF_ALU`` means::
271 dst = (u32) ((u32) dst + (u32) src)
273 where '(u32)' indicates that the upper 32 bits are zeroed.
275 ``BPF_ADD | BPF_X | BPF_ALU64`` means::
279 ``BPF_XOR | BPF_K | BPF_ALU`` means::
281 dst = (u32) dst ^ (u32) imm32
283 ``BPF_XOR | BPF_K | BPF_ALU64`` means::
287 Note that most instructions have instruction offset of 0. Only three instructions
288 (``BPF_SDIV``, ``BPF_SMOD``, ``BPF_MOVSX``) have a non-zero offset.
290 The division and modulo operations support both unsigned and signed flavors.
292 For unsigned operations (``BPF_DIV`` and ``BPF_MOD``), for ``BPF_ALU``,
293 'imm' is interpreted as a 32-bit unsigned value. For ``BPF_ALU64``,
294 'imm' is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then
295 interpreted as a 64-bit unsigned value.
297 For signed operations (``BPF_SDIV`` and ``BPF_SMOD``), for ``BPF_ALU``,
298 'imm' is interpreted as a 32-bit signed value. For ``BPF_ALU64``, 'imm'
299 is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then
300 interpreted as a 64-bit signed value.
302 The ``BPF_MOVSX`` instruction does a move operation with sign extension.
303 ``BPF_ALU | BPF_MOVSX`` :term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into 32
304 bit operands, and zeroes the remaining upper 32 bits.
305 ``BPF_ALU64 | BPF_MOVSX`` :term:`sign extends<Sign Extend>` 8-bit, 16-bit, and 32-bit
306 operands into 64 bit operands.
308 Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31)
309 for 32-bit operations.
311 Byte swap instructions
312 ----------------------
314 The byte swap instructions use instruction classes of ``BPF_ALU`` and ``BPF_ALU64``
315 and a 4-bit 'code' field of ``BPF_END``.
317 The byte swap instructions operate on the destination register
318 only and do not use a separate source register or immediate value.
320 For ``BPF_ALU``, the 1-bit source operand field in the opcode is used to
321 select what byte order the operation converts from or to. For
322 ``BPF_ALU64``, the 1-bit source operand field in the opcode is reserved
323 and must be set to 0.
325 ========= ========= ===== =================================================
326 class source value description
327 ========= ========= ===== =================================================
328 BPF_ALU BPF_TO_LE 0x00 convert between host byte order and little endian
329 BPF_ALU BPF_TO_BE 0x08 convert between host byte order and big endian
330 BPF_ALU64 Reserved 0x00 do byte swap unconditionally
331 ========= ========= ===== =================================================
333 The 'imm' field encodes the width of the swap operations. The following widths
334 are supported: 16, 32 and 64.
338 ``BPF_ALU | BPF_TO_LE | BPF_END`` with imm = 16/32/64 means::
344 ``BPF_ALU | BPF_TO_BE | BPF_END`` with imm = 16/32/64 means::
350 ``BPF_ALU64 | BPF_TO_LE | BPF_END`` with imm = 16/32/64 means::
359 ``BPF_JMP32`` uses 32-bit wide operands while ``BPF_JMP`` uses 64-bit wide operands for
360 otherwise identical operations.
361 The 'code' field encodes the operation as below:
363 ======== ===== === =========================================== =========================================
364 code value src description notes
365 ======== ===== === =========================================== =========================================
366 BPF_JA 0x0 0x0 PC += offset BPF_JMP class
367 BPF_JA 0x0 0x0 PC += imm BPF_JMP32 class
368 BPF_JEQ 0x1 any PC += offset if dst == src
369 BPF_JGT 0x2 any PC += offset if dst > src unsigned
370 BPF_JGE 0x3 any PC += offset if dst >= src unsigned
371 BPF_JSET 0x4 any PC += offset if dst & src
372 BPF_JNE 0x5 any PC += offset if dst != src
373 BPF_JSGT 0x6 any PC += offset if dst > src signed
374 BPF_JSGE 0x7 any PC += offset if dst >= src signed
375 BPF_CALL 0x8 0x0 call helper function by address see `Helper functions`_
376 BPF_CALL 0x8 0x1 call PC += offset see `Program-local functions`_
377 BPF_CALL 0x8 0x2 call helper function by BTF ID see `Helper functions`_
378 BPF_EXIT 0x9 0x0 return BPF_JMP only
379 BPF_JLT 0xa any PC += offset if dst < src unsigned
380 BPF_JLE 0xb any PC += offset if dst <= src unsigned
381 BPF_JSLT 0xc any PC += offset if dst < src signed
382 BPF_JSLE 0xd any PC += offset if dst <= src signed
383 ======== ===== === =========================================== =========================================
385 The eBPF program needs to store the return value into register R0 before doing a
390 ``BPF_JSGE | BPF_X | BPF_JMP32`` (0x7e) means::
392 if (s32)dst s>= (s32)src goto +offset
394 where 's>=' indicates a signed '>=' comparison.
396 ``BPF_JA | BPF_K | BPF_JMP32`` (0x06) means::
400 where 'imm' means the branch offset comes from insn 'imm' field.
402 Note that there are two flavors of ``BPF_JA`` instructions. The
403 ``BPF_JMP`` class permits a 16-bit jump offset specified by the 'offset'
404 field, whereas the ``BPF_JMP32`` class permits a 32-bit jump offset
405 specified by the 'imm' field. A > 16-bit conditional jump may be
406 converted to a < 16-bit conditional jump plus a 32-bit unconditional
412 Helper functions are a concept whereby BPF programs can call into a
413 set of function calls exposed by the underlying platform.
415 Historically, each helper function was identified by an address
416 encoded in the imm field. The available helper functions may differ
417 for each program type, but address values are unique across all program types.
419 Platforms that support the BPF Type Format (BTF) support identifying
420 a helper function by a BTF ID encoded in the imm field, where the BTF ID
421 identifies the helper name and type.
423 Program-local functions
424 ~~~~~~~~~~~~~~~~~~~~~~~
425 Program-local functions are functions exposed by the same BPF program as the
426 caller, and are referenced by offset from the call instruction, similar to
427 ``BPF_JA``. A ``BPF_EXIT`` within the program-local function will return to
430 Load and store instructions
431 ===========================
433 For load and store instructions (``BPF_LD``, ``BPF_LDX``, ``BPF_ST``, and ``BPF_STX``), the
434 8-bit 'opcode' field is divided as:
436 ============ ====== =================
437 3 bits (MSB) 2 bits 3 bits (LSB)
438 ============ ====== =================
439 mode size instruction class
440 ============ ====== =================
442 The mode modifier is one of:
444 ============= ===== ==================================== =============
445 mode modifier value description reference
446 ============= ===== ==================================== =============
447 BPF_IMM 0x00 64-bit immediate instructions `64-bit immediate instructions`_
448 BPF_ABS 0x20 legacy BPF packet access (absolute) `Legacy BPF Packet access instructions`_
449 BPF_IND 0x40 legacy BPF packet access (indirect) `Legacy BPF Packet access instructions`_
450 BPF_MEM 0x60 regular load and store operations `Regular load and store operations`_
451 BPF_MEMSX 0x80 sign-extension load operations `Sign-extension load operations`_
452 BPF_ATOMIC 0xc0 atomic operations `Atomic operations`_
453 ============= ===== ==================================== =============
455 The size modifier is one of:
457 ============= ===== =====================
458 size modifier value description
459 ============= ===== =====================
460 BPF_W 0x00 word (4 bytes)
461 BPF_H 0x08 half word (2 bytes)
463 BPF_DW 0x18 double word (8 bytes)
464 ============= ===== =====================
466 Regular load and store operations
467 ---------------------------------
469 The ``BPF_MEM`` mode modifier is used to encode regular load and store
470 instructions that transfer data between a register and memory.
472 ``BPF_MEM | <size> | BPF_STX`` means::
474 *(size *) (dst + offset) = src
476 ``BPF_MEM | <size> | BPF_ST`` means::
478 *(size *) (dst + offset) = imm32
480 ``BPF_MEM | <size> | BPF_LDX`` means::
482 dst = *(unsigned size *) (src + offset)
484 Where size is one of: ``BPF_B``, ``BPF_H``, ``BPF_W``, or ``BPF_DW`` and
485 'unsigned size' is one of u8, u16, u32 or u64.
487 Sign-extension load operations
488 ------------------------------
490 The ``BPF_MEMSX`` mode modifier is used to encode :term:`sign-extension<Sign Extend>` load
491 instructions that transfer data between a register and memory.
493 ``BPF_MEMSX | <size> | BPF_LDX`` means::
495 dst = *(signed size *) (src + offset)
497 Where size is one of: ``BPF_B``, ``BPF_H`` or ``BPF_W``, and
498 'signed size' is one of s8, s16 or s32.
503 Atomic operations are operations that operate on memory and can not be
504 interrupted or corrupted by other access to the same memory region
505 by other eBPF programs or means outside of this specification.
507 All atomic operations supported by eBPF are encoded as store operations
508 that use the ``BPF_ATOMIC`` mode modifier as follows:
510 * ``BPF_ATOMIC | BPF_W | BPF_STX`` for 32-bit operations
511 * ``BPF_ATOMIC | BPF_DW | BPF_STX`` for 64-bit operations
512 * 8-bit and 16-bit wide atomic operations are not supported.
514 The 'imm' field is used to encode the actual atomic operation.
515 Simple atomic operation use a subset of the values defined to encode
516 arithmetic operations in the 'imm' field to encode the atomic operation:
518 ======== ===== ===========
519 imm value description
520 ======== ===== ===========
521 BPF_ADD 0x00 atomic add
522 BPF_OR 0x40 atomic or
523 BPF_AND 0x50 atomic and
524 BPF_XOR 0xa0 atomic xor
525 ======== ===== ===========
528 ``BPF_ATOMIC | BPF_W | BPF_STX`` with 'imm' = BPF_ADD means::
530 *(u32 *)(dst + offset) += src
532 ``BPF_ATOMIC | BPF_DW | BPF_STX`` with 'imm' = BPF ADD means::
534 *(u64 *)(dst + offset) += src
536 In addition to the simple atomic operations, there also is a modifier and
537 two complex atomic operations:
539 =========== ================ ===========================
540 imm value description
541 =========== ================ ===========================
542 BPF_FETCH 0x01 modifier: return old value
543 BPF_XCHG 0xe0 | BPF_FETCH atomic exchange
544 BPF_CMPXCHG 0xf0 | BPF_FETCH atomic compare and exchange
545 =========== ================ ===========================
547 The ``BPF_FETCH`` modifier is optional for simple atomic operations, and
548 always set for the complex atomic operations. If the ``BPF_FETCH`` flag
549 is set, then the operation also overwrites ``src`` with the value that
550 was in memory before it was modified.
552 The ``BPF_XCHG`` operation atomically exchanges ``src`` with the value
553 addressed by ``dst + offset``.
555 The ``BPF_CMPXCHG`` operation atomically compares the value addressed by
556 ``dst + offset`` with ``R0``. If they match, the value addressed by
557 ``dst + offset`` is replaced with ``src``. In either case, the
558 value that was at ``dst + offset`` before the operation is zero-extended
559 and loaded back to ``R0``.
561 64-bit immediate instructions
562 -----------------------------
564 Instructions with the ``BPF_IMM`` 'mode' modifier use the wide instruction
565 encoding defined in `Instruction encoding`_, and use the 'src' field of the
566 basic instruction to hold an opcode subtype.
568 The following table defines a set of ``BPF_IMM | BPF_DW | BPF_LD`` instructions
569 with opcode subtypes in the 'src' field, using new terms such as "map"
570 defined further below:
572 ========================= ====== === ========================================= =========== ==============
573 opcode construction opcode src pseudocode imm type dst type
574 ========================= ====== === ========================================= =========== ==============
575 BPF_IMM | BPF_DW | BPF_LD 0x18 0x0 dst = imm64 integer integer
576 BPF_IMM | BPF_DW | BPF_LD 0x18 0x1 dst = map_by_fd(imm) map fd map
577 BPF_IMM | BPF_DW | BPF_LD 0x18 0x2 dst = map_val(map_by_fd(imm)) + next_imm map fd data pointer
578 BPF_IMM | BPF_DW | BPF_LD 0x18 0x3 dst = var_addr(imm) variable id data pointer
579 BPF_IMM | BPF_DW | BPF_LD 0x18 0x4 dst = code_addr(imm) integer code pointer
580 BPF_IMM | BPF_DW | BPF_LD 0x18 0x5 dst = map_by_idx(imm) map index map
581 BPF_IMM | BPF_DW | BPF_LD 0x18 0x6 dst = map_val(map_by_idx(imm)) + next_imm map index data pointer
582 ========================= ====== === ========================================= =========== ==============
586 * map_by_fd(imm) means to convert a 32-bit file descriptor into an address of a map (see `Maps`_)
587 * map_by_idx(imm) means to convert a 32-bit index into an address of a map
588 * map_val(map) gets the address of the first value in a given map
589 * var_addr(imm) gets the address of a platform variable (see `Platform Variables`_) with a given id
590 * code_addr(imm) gets the address of the instruction at a specified relative offset in number of (64-bit) instructions
591 * the 'imm type' can be used by disassemblers for display
592 * the 'dst type' can be used for verification and JIT compilation purposes
597 Maps are shared memory regions accessible by eBPF programs on some platforms.
598 A map can have various semantics as defined in a separate document, and may or
599 may not have a single contiguous memory region, but the 'map_val(map)' is
600 currently only defined for maps that do have a single contiguous memory region.
602 Each map can have a file descriptor (fd) if supported by the platform, where
603 'map_by_fd(imm)' means to get the map with the specified file descriptor. Each
604 BPF program can also be defined to use a set of maps associated with the
605 program at load time, and 'map_by_idx(imm)' means to get the map with the given
606 index in the set associated with the BPF program containing the instruction.
611 Platform variables are memory regions, identified by integer ids, exposed by
612 the runtime and accessible by BPF programs on some platforms. The
613 'var_addr(imm)' operation means to get the address of the memory region
614 identified by the given id.
616 Legacy BPF Packet access instructions
617 -------------------------------------
619 eBPF previously introduced special instructions for access to packet data that were
620 carried over from classic BPF. However, these instructions are
621 deprecated and should no longer be used.